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150
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1 # RUN: llc -march=amdgcn -mcpu=fiji -start-before si-peephole-sdwa -o - %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
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2 # RUN: llc -march=amdgcn -mcpu=gfx900 -start-before si-peephole-sdwa -o - %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN %s
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3
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4 # GCN-LABEL: {{^}}sdwa_imm_operand:
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5 # GCN: v_mov_b32_e32 v[[SHIFT:[0-9]+]], 2
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6 # GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 2
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7 # GCN: BB0_1:
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8 # GCN: v_lshlrev_b32_sdwa v{{[0-9]+}}, v[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
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9 # GCN: v_lshlrev_b32_sdwa v{{[0-9]+}}, v[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
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10
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11 # GCN-LABEL: {{^}}sdwa_sgpr_operand:
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12 # VI: v_mov_b32_e32 v[[SHIFT:[0-9]+]], 2
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13 # VI-NOT: v_mov_b32_e32 v{{[0-9]+}}, 2
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14 # VI: BB1_1:
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15 # VI: v_lshlrev_b32_sdwa v{{[0-9]+}}, v[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
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16 # VI: v_lshlrev_b32_sdwa v{{[0-9]+}}, v[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
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17
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18 # GFX9: s_mov_b32 s[[SHIFT:[0-9]+]], 2
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19 # GFX9-NOT: v_mov_b32_e32 v{{[0-9]+}}, 2
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20 # GFX9: BB1_1:
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21 # GFX9: v_lshlrev_b32_sdwa v{{[0-9]+}}, s[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
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22 # GFX9: v_lshlrev_b32_sdwa v{{[0-9]+}}, s[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
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23
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24 --- |
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25 ; ModuleID = 'sdwa-scalar-ops.opt.ll'
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26 source_filename = "sdwa-scalar-ops.opt.ll"
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27 target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
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28
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29 define amdgpu_kernel void @sdwa_imm_operand(i32 addrspace(1)* nocapture %arg) {
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30 bb:
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31 br label %bb2
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32
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33 bb1: ; preds = %bb2
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34 ret void
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35
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36 bb2: ; preds = %bb2, %bb
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37 %lsr.iv = phi i64 [ %lsr.iv.next, %bb2 ], [ 0, %bb ]
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38 %bc = bitcast i32 addrspace(1)* %arg to i8 addrspace(1)*
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39 %uglygep4 = getelementptr i8, i8 addrspace(1)* %bc, i64 %lsr.iv
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40 %uglygep45 = bitcast i8 addrspace(1)* %uglygep4 to i32 addrspace(1)*
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41 %tmp5 = load i32, i32 addrspace(1)* %uglygep45, align 4
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42 %tmp6 = lshr i32 %tmp5, 8
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43 %tmp7 = and i32 %tmp6, 255
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44 %tmp8 = zext i32 %tmp7 to i64
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45 %tmp9 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp8
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46 store i32 1, i32 addrspace(1)* %tmp9, align 4
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47 %scevgep = getelementptr i32, i32 addrspace(1)* %uglygep45, i64 1
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48 %tmp13 = load i32, i32 addrspace(1)* %scevgep, align 4
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49 %tmp14 = lshr i32 %tmp13, 8
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50 %tmp15 = and i32 %tmp14, 255
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51 %tmp16 = zext i32 %tmp15 to i64
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52 %tmp17 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp16
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53 store i32 1, i32 addrspace(1)* %tmp17, align 4
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54 %lsr.iv.next = add nuw nsw i64 %lsr.iv, 8
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55 %tmp1 = trunc i64 %lsr.iv.next to i32
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56 %tmp19 = icmp eq i32 %tmp1, 4096
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57 br i1 %tmp19, label %bb1, label %bb2
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58 }
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59
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60 define amdgpu_kernel void @sdwa_sgpr_operand(i32 addrspace(1)* nocapture %arg) {
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61 bb:
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62 br label %bb2
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63
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64 bb1: ; preds = %bb2
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65 ret void
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66
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67 bb2: ; preds = %bb2, %bb
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68 %lsr.iv = phi i64 [ %lsr.iv.next, %bb2 ], [ 0, %bb ]
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69 %bc = bitcast i32 addrspace(1)* %arg to i8 addrspace(1)*
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70 %uglygep4 = getelementptr i8, i8 addrspace(1)* %bc, i64 %lsr.iv
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71 %uglygep45 = bitcast i8 addrspace(1)* %uglygep4 to i32 addrspace(1)*
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72 %tmp5 = load i32, i32 addrspace(1)* %uglygep45, align 4
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73 %tmp6 = lshr i32 %tmp5, 8
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74 %tmp7 = and i32 %tmp6, 255
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75 %tmp8 = zext i32 %tmp7 to i64
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76 %tmp9 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp8
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77 store i32 1, i32 addrspace(1)* %tmp9, align 4
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78 %scevgep = getelementptr i32, i32 addrspace(1)* %uglygep45, i64 1
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79 %tmp13 = load i32, i32 addrspace(1)* %scevgep, align 4
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80 %tmp14 = lshr i32 %tmp13, 8
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81 %tmp15 = and i32 %tmp14, 255
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82 %tmp16 = zext i32 %tmp15 to i64
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83 %tmp17 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp16
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84 store i32 1, i32 addrspace(1)* %tmp17, align 4
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85 %lsr.iv.next = add nuw nsw i64 %lsr.iv, 8
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86 %tmp1 = trunc i64 %lsr.iv.next to i32
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87 %tmp19 = icmp eq i32 %tmp1, 4096
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88 br i1 %tmp19, label %bb1, label %bb2
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89 }
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90
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91 ...
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92 ---
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93 name: sdwa_imm_operand
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94 alignment: 1
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95 exposesReturnsTwice: false
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96 legalized: false
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97 regBankSelected: false
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98 selected: false
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99 tracksRegLiveness: true
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100 registers:
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101 - { id: 0, class: sreg_64 }
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102 - { id: 1, class: sreg_64 }
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103 - { id: 2, class: vgpr_32 }
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104 - { id: 3, class: sgpr_128 }
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105 - { id: 4, class: sgpr_64 }
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106 - { id: 5, class: sreg_32_xm0 }
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107 - { id: 6, class: sgpr_32 }
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108 - { id: 7, class: sreg_64 }
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109 - { id: 8, class: sreg_64 }
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110 - { id: 9, class: sreg_64_xexec }
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111 - { id: 10, class: sreg_32_xm0 }
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112 - { id: 11, class: sreg_32_xm0 }
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113 - { id: 12, class: sreg_32_xm0 }
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114 - { id: 13, class: sreg_32_xm0 }
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115 - { id: 14, class: sreg_32_xm0 }
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116 - { id: 15, class: sreg_32_xm0 }
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117 - { id: 16, class: sreg_64 }
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118 - { id: 17, class: vgpr_32 }
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119 - { id: 18, class: vreg_64 }
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120 - { id: 19, class: sreg_32_xm0 }
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121 - { id: 20, class: sreg_32 }
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122 - { id: 21, class: sreg_32_xm0 }
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123 - { id: 22, class: sreg_32_xm0 }
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124 - { id: 23, class: sreg_32_xm0 }
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125 - { id: 24, class: sreg_64 }
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126 - { id: 25, class: sreg_32_xm0 }
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127 - { id: 26, class: sreg_32_xm0 }
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128 - { id: 27, class: sreg_32_xm0 }
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129 - { id: 28, class: sreg_32_xm0 }
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130 - { id: 29, class: sreg_64 }
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131 - { id: 30, class: vgpr_32 }
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132 - { id: 31, class: vreg_64 }
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133 - { id: 32, class: sreg_32_xm0 }
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134 - { id: 33, class: sreg_32_xm0 }
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135 - { id: 34, class: sreg_64 }
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136 - { id: 35, class: sreg_32_xm0 }
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137 - { id: 36, class: sreg_32_xm0 }
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138 - { id: 37, class: sreg_32_xm0 }
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139 - { id: 38, class: sreg_32_xm0 }
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140 - { id: 39, class: vreg_64 }
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141 - { id: 40, class: vgpr_32 }
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142 - { id: 41, class: vreg_64 }
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143 - { id: 42, class: sreg_32_xm0 }
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144 - { id: 43, class: sreg_32 }
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145 - { id: 44, class: sreg_32_xm0 }
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146 - { id: 45, class: sreg_64 }
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147 - { id: 46, class: sreg_32_xm0 }
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148 - { id: 47, class: sreg_32_xm0 }
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149 - { id: 48, class: sreg_32_xm0 }
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150 - { id: 49, class: sreg_32_xm0 }
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151 - { id: 50, class: sreg_64 }
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152 - { id: 51, class: vreg_64 }
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153 - { id: 52, class: sreg_64 }
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154 - { id: 53, class: sreg_32_xm0 }
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155 - { id: 54, class: sreg_32_xm0 }
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156 - { id: 55, class: sreg_32_xm0 }
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157 - { id: 56, class: sreg_32_xm0 }
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158 - { id: 57, class: sreg_64 }
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159 - { id: 58, class: sreg_32_xm0 }
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160 - { id: 59, class: sreg_32_xm0 }
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161 - { id: 60, class: vgpr_32 }
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162 - { id: 61, class: vgpr_32 }
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163 - { id: 62, class: vreg_64 }
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164 - { id: 63, class: vgpr_32 }
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165 - { id: 64, class: vgpr_32 }
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166 - { id: 65, class: vgpr_32 }
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167 - { id: 66, class: vgpr_32 }
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168 - { id: 67, class: vreg_64 }
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169 - { id: 68, class: vgpr_32 }
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170 - { id: 69, class: vgpr_32 }
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171 - { id: 70, class: vgpr_32 }
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172 - { id: 71, class: vgpr_32 }
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173 - { id: 72, class: vgpr_32 }
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174 - { id: 73, class: vgpr_32 }
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175 - { id: 74, class: vgpr_32 }
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176 - { id: 75, class: vreg_64 }
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177 - { id: 76, class: vgpr_32 }
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178 - { id: 77, class: vgpr_32 }
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179 - { id: 78, class: vgpr_32 }
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180 - { id: 79, class: vgpr_32 }
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181 - { id: 80, class: vreg_64 }
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182 - { id: 81, class: vgpr_32 }
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183 - { id: 82, class: vgpr_32 }
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184 - { id: 83, class: vgpr_32 }
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185 liveins:
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186 - { reg: '$sgpr4_sgpr5', virtual-reg: '%4' }
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187 frameInfo:
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188 isFrameAddressTaken: false
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189 isReturnAddressTaken: false
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190 hasStackMap: false
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191 hasPatchPoint: false
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192 stackSize: 0
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193 offsetAdjustment: 0
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194 maxAlignment: 0
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195 adjustsStack: false
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196 hasCalls: false
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197 hasOpaqueSPAdjustment: false
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198 hasVAStart: false
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199 hasMustTailInVarArgFunc: false
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200 body: |
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201 bb.0.bb:
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202 successors: %bb.2.bb2(0x80000000)
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203 liveins: $sgpr4_sgpr5
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204
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205 %4 = COPY $sgpr4_sgpr5
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223
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206 %9 = S_LOAD_DWORDX2_IMM %4, 0, 0 :: (non-temporal dereferenceable invariant load (s64) from `i64 addrspace(4)* undef`)
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150
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207 %8 = S_MOV_B64 0
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208 %7 = COPY %9
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209 %30 = V_MOV_B32_e32 1, implicit $exec
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210 S_BRANCH %bb.2.bb2
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211
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212 bb.1.bb1:
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213 S_ENDPGM 0
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214
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215 bb.2.bb2:
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216 successors: %bb.1.bb1(0x04000000), %bb.2.bb2(0x7c000000)
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217
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218 %0 = PHI %8, %bb.0.bb, %1, %bb.2.bb2
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219 %13 = COPY %7.sub1
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220 %14 = S_ADD_U32 %7.sub0, %0.sub0, implicit-def $scc
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221 %15 = S_ADDC_U32 %7.sub1, %0.sub1, implicit-def dead $scc, implicit $scc
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222 %16 = REG_SEQUENCE %14, %subreg.sub0, %15, %subreg.sub1
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223 %18 = COPY %16
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223
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224 %17 = FLAT_LOAD_DWORD %18, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %ir.uglygep45)
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221
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225 %60 = V_BFE_U32_e64 %17, 8, 8, implicit $exec
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150
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226 %61 = V_LSHLREV_B32_e32 2, killed %60, implicit $exec
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221
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227 %70 = V_ADD_CO_U32_e32 %7.sub0, %61, implicit-def $vcc, implicit $exec
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150
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228 %66 = COPY %13
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229 %65 = V_ADDC_U32_e32 0, %66, implicit-def $vcc, implicit $vcc, implicit $exec
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230 %67 = REG_SEQUENCE %70, %subreg.sub0, killed %65, %subreg.sub1
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223
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231 FLAT_STORE_DWORD %67, %30, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.tmp9)
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150
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232 %37 = S_ADD_U32 %14, 4, implicit-def $scc
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233 %38 = S_ADDC_U32 %15, 0, implicit-def dead $scc, implicit $scc
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234 %71 = COPY killed %37
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235 %72 = COPY killed %38
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236 %41 = REG_SEQUENCE killed %71, %subreg.sub0, killed %72, %subreg.sub1
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223
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237 %40 = FLAT_LOAD_DWORD killed %41, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %ir.scevgep)
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221
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238 %73 = V_BFE_U32_e64 %40, 8, 8, implicit $exec
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150
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239 %74 = V_LSHLREV_B32_e32 2, killed %73, implicit $exec
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221
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240 %83 = V_ADD_CO_U32_e32 %7.sub0, %74, implicit-def $vcc, implicit $exec
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150
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241 %78 = V_ADDC_U32_e32 0, %66, implicit-def $vcc, implicit $vcc, implicit $exec
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242 %80 = REG_SEQUENCE %83, %subreg.sub0, killed %78, %subreg.sub1
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223
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243 FLAT_STORE_DWORD %80, %30, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.tmp17)
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150
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244 %55 = S_ADD_U32 %0.sub0, 8, implicit-def $scc
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245 %56 = S_ADDC_U32 %0.sub1, 0, implicit-def dead $scc, implicit $scc
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246 %57 = REG_SEQUENCE %55, %subreg.sub0, killed %56, %subreg.sub1
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247 %1 = COPY %57
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248 S_CMPK_EQ_I32 %55, 4096, implicit-def $scc
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249 S_CBRANCH_SCC1 %bb.1.bb1, implicit $scc
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250 S_BRANCH %bb.2.bb2
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251
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252 ...
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253 ---
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254 name: sdwa_sgpr_operand
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255 alignment: 1
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256 exposesReturnsTwice: false
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257 legalized: false
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258 regBankSelected: false
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259 selected: false
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260 tracksRegLiveness: true
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261 registers:
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262 - { id: 0, class: sreg_64 }
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263 - { id: 1, class: sreg_64 }
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264 - { id: 2, class: vgpr_32 }
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265 - { id: 3, class: sgpr_128 }
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266 - { id: 4, class: sgpr_64 }
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267 - { id: 5, class: sreg_32_xm0 }
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268 - { id: 6, class: sgpr_32 }
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269 - { id: 7, class: sreg_64 }
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270 - { id: 8, class: sreg_64 }
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271 - { id: 9, class: sreg_64_xexec }
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272 - { id: 10, class: sreg_32_xm0 }
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273 - { id: 11, class: sreg_32_xm0 }
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274 - { id: 12, class: sreg_32_xm0 }
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275 - { id: 13, class: sreg_32_xm0 }
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276 - { id: 14, class: sreg_32_xm0 }
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277 - { id: 15, class: sreg_32_xm0 }
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278 - { id: 16, class: sreg_64 }
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279 - { id: 17, class: vgpr_32 }
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280 - { id: 18, class: vreg_64 }
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281 - { id: 19, class: sreg_32_xm0 }
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282 - { id: 20, class: sreg_32 }
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283 - { id: 21, class: sreg_32_xm0 }
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284 - { id: 22, class: sreg_32_xm0 }
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285 - { id: 23, class: sreg_32_xm0 }
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286 - { id: 24, class: sreg_64 }
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287 - { id: 25, class: sreg_32_xm0 }
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288 - { id: 26, class: sreg_32_xm0 }
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|
|
289 - { id: 27, class: sreg_32_xm0 }
|
|
|
290 - { id: 28, class: sreg_32_xm0 }
|
|
|
291 - { id: 29, class: sreg_64 }
|
|
|
292 - { id: 30, class: vgpr_32 }
|
|
|
293 - { id: 31, class: vreg_64 }
|
|
|
294 - { id: 32, class: sreg_32_xm0 }
|
|
|
295 - { id: 33, class: sreg_32_xm0 }
|
|
|
296 - { id: 34, class: sreg_64 }
|
|
|
297 - { id: 35, class: sreg_32_xm0 }
|
|
|
298 - { id: 36, class: sreg_32_xm0 }
|
|
|
299 - { id: 37, class: sreg_32_xm0 }
|
|
|
300 - { id: 38, class: sreg_32_xm0 }
|
|
|
301 - { id: 39, class: vreg_64 }
|
|
|
302 - { id: 40, class: vgpr_32 }
|
|
|
303 - { id: 41, class: vreg_64 }
|
|
|
304 - { id: 42, class: sreg_32_xm0 }
|
|
|
305 - { id: 43, class: sreg_32 }
|
|
|
306 - { id: 44, class: sreg_32_xm0 }
|
|
|
307 - { id: 45, class: sreg_64 }
|
|
|
308 - { id: 46, class: sreg_32_xm0 }
|
|
|
309 - { id: 47, class: sreg_32_xm0 }
|
|
|
310 - { id: 48, class: sreg_32_xm0 }
|
|
|
311 - { id: 49, class: sreg_32_xm0 }
|
|
|
312 - { id: 50, class: sreg_64 }
|
|
|
313 - { id: 51, class: vreg_64 }
|
|
|
314 - { id: 52, class: sreg_64 }
|
|
|
315 - { id: 53, class: sreg_32_xm0 }
|
|
|
316 - { id: 54, class: sreg_32_xm0 }
|
|
|
317 - { id: 55, class: sreg_32_xm0 }
|
|
|
318 - { id: 56, class: sreg_32_xm0 }
|
|
|
319 - { id: 57, class: sreg_64 }
|
|
|
320 - { id: 58, class: sreg_32_xm0 }
|
|
|
321 - { id: 59, class: sreg_32_xm0 }
|
|
|
322 - { id: 60, class: vgpr_32 }
|
|
|
323 - { id: 61, class: vgpr_32 }
|
|
|
324 - { id: 62, class: vreg_64 }
|
|
|
325 - { id: 63, class: vgpr_32 }
|
|
|
326 - { id: 64, class: vgpr_32 }
|
|
|
327 - { id: 65, class: vgpr_32 }
|
|
|
328 - { id: 66, class: vgpr_32 }
|
|
|
329 - { id: 67, class: vreg_64 }
|
|
|
330 - { id: 68, class: vgpr_32 }
|
|
|
331 - { id: 69, class: vgpr_32 }
|
|
|
332 - { id: 70, class: vgpr_32 }
|
|
|
333 - { id: 71, class: vgpr_32 }
|
|
|
334 - { id: 72, class: vgpr_32 }
|
|
|
335 - { id: 73, class: vgpr_32 }
|
|
|
336 - { id: 74, class: vgpr_32 }
|
|
|
337 - { id: 75, class: vreg_64 }
|
|
|
338 - { id: 76, class: vgpr_32 }
|
|
|
339 - { id: 77, class: vgpr_32 }
|
|
|
340 - { id: 78, class: vgpr_32 }
|
|
|
341 - { id: 79, class: vgpr_32 }
|
|
|
342 - { id: 80, class: vreg_64 }
|
|
|
343 - { id: 81, class: vgpr_32 }
|
|
|
344 - { id: 82, class: vgpr_32 }
|
|
|
345 - { id: 83, class: vgpr_32 }
|
|
|
346 - { id: 84, class: sreg_32_xm0 }
|
|
|
347 liveins:
|
|
|
348 - { reg: '$sgpr4_sgpr5', virtual-reg: '%4' }
|
|
|
349 frameInfo:
|
|
|
350 isFrameAddressTaken: false
|
|
|
351 isReturnAddressTaken: false
|
|
|
352 hasStackMap: false
|
|
|
353 hasPatchPoint: false
|
|
|
354 stackSize: 0
|
|
|
355 offsetAdjustment: 0
|
|
|
356 maxAlignment: 0
|
|
|
357 adjustsStack: false
|
|
|
358 hasCalls: false
|
|
|
359 hasOpaqueSPAdjustment: false
|
|
|
360 hasVAStart: false
|
|
|
361 hasMustTailInVarArgFunc: false
|
|
|
362 body: |
|
|
|
363 bb.0.bb:
|
|
|
364 successors: %bb.2.bb2(0x80000000)
|
|
|
365 liveins: $sgpr4_sgpr5
|
|
|
366
|
|
|
367 %4 = COPY $sgpr4_sgpr5
|
|
223
|
368 %9 = S_LOAD_DWORDX2_IMM %4, 0, 0 :: (non-temporal dereferenceable invariant load (s64) from `i64 addrspace(4)* undef`)
|
|
150
|
369 %8 = S_MOV_B64 0
|
|
|
370 %7 = COPY %9
|
|
|
371 %30 = V_MOV_B32_e32 1, implicit $exec
|
|
|
372 %84 = S_MOV_B32 2
|
|
|
373 S_BRANCH %bb.2.bb2
|
|
|
374
|
|
|
375 bb.1.bb1:
|
|
|
376 S_ENDPGM 0
|
|
|
377
|
|
|
378 bb.2.bb2:
|
|
|
379 successors: %bb.1.bb1(0x04000000), %bb.2.bb2(0x7c000000)
|
|
|
380
|
|
|
381 %0 = PHI %8, %bb.0.bb, %1, %bb.2.bb2
|
|
|
382 %13 = COPY %7.sub1
|
|
|
383 %14 = S_ADD_U32 %7.sub0, %0.sub0, implicit-def $scc
|
|
|
384 %15 = S_ADDC_U32 %7.sub1, %0.sub1, implicit-def dead $scc, implicit $scc
|
|
|
385 %16 = REG_SEQUENCE %14, %subreg.sub0, %15, %subreg.sub1
|
|
|
386 %18 = COPY %16
|
|
223
|
387 %17 = FLAT_LOAD_DWORD %18, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %ir.uglygep45)
|
|
221
|
388 %60 = V_BFE_U32_e64 %17, 8, 8, implicit $exec
|
|
150
|
389 %61 = V_LSHLREV_B32_e32 %84, killed %60, implicit $exec
|
|
221
|
390 %70 = V_ADD_CO_U32_e32 %7.sub0, %61, implicit-def $vcc, implicit $exec
|
|
150
|
391 %66 = COPY %13
|
|
|
392 %65 = V_ADDC_U32_e32 0, %66, implicit-def $vcc, implicit $vcc, implicit $exec
|
|
|
393 %67 = REG_SEQUENCE %70, %subreg.sub0, killed %65, %subreg.sub1
|
|
223
|
394 FLAT_STORE_DWORD %67, %30, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.tmp9)
|
|
150
|
395 %37 = S_ADD_U32 %14, 4, implicit-def $scc
|
|
|
396 %38 = S_ADDC_U32 %15, 0, implicit-def dead $scc, implicit $scc
|
|
|
397 %71 = COPY killed %37
|
|
|
398 %72 = COPY killed %38
|
|
|
399 %41 = REG_SEQUENCE killed %71, %subreg.sub0, killed %72, %subreg.sub1
|
|
223
|
400 %40 = FLAT_LOAD_DWORD killed %41, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %ir.scevgep)
|
|
221
|
401 %73 = V_BFE_U32_e64 %40, 8, 8, implicit $exec
|
|
150
|
402 %74 = V_LSHLREV_B32_e32 %84, killed %73, implicit $exec
|
|
221
|
403 %83 = V_ADD_CO_U32_e32 %7.sub0, %74, implicit-def $vcc, implicit $exec
|
|
150
|
404 %78 = V_ADDC_U32_e32 0, %66, implicit-def $vcc, implicit $vcc, implicit $exec
|
|
|
405 %80 = REG_SEQUENCE %83, %subreg.sub0, killed %78, %subreg.sub1
|
|
223
|
406 FLAT_STORE_DWORD %80, %30, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.tmp17)
|
|
150
|
407 %55 = S_ADD_U32 %0.sub0, 8, implicit-def $scc
|
|
|
408 %56 = S_ADDC_U32 %0.sub1, 0, implicit-def dead $scc, implicit $scc
|
|
|
409 %57 = REG_SEQUENCE %55, %subreg.sub0, killed %56, %subreg.sub1
|
|
|
410 %1 = COPY %57
|
|
|
411 S_CMPK_EQ_I32 %55, 4096, implicit-def $scc
|
|
|
412 S_CBRANCH_SCC1 %bb.1.bb1, implicit $scc
|
|
|
413 S_BRANCH %bb.2.bb2
|
|
|
414
|
|
|
415 ...
|
