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150
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1 ; RUN: llc -march=sparc <%s | FileCheck %s
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2
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3 ; CHECK-LABEL: test_constraint_r
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236
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4 ; CHECK: add %i1, %i0, %i0
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150
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5 define i32 @test_constraint_r(i32 %a, i32 %b) {
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6 entry:
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7 %0 = tail call i32 asm sideeffect "add $2, $1, $0", "=r,r,r"(i32 %a, i32 %b)
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8 ret i32 %0
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9 }
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10
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11 ;; Check tests only that the constraints are accepted without a compiler failure.
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12 ; CHECK-LABEL: test_constraints_nro:
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13 %struct.anon = type { i32, i32 }
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14 @v = external global %struct.anon, align 4
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15 define void @test_constraints_nro() {
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16 entry:
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17 %0 = load i32, i32* getelementptr inbounds (%struct.anon, %struct.anon* @v, i32 0, i32 0);
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18 %1 = load i32, i32* getelementptr inbounds (%struct.anon, %struct.anon* @v, i32 0, i32 1);
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19 tail call void asm sideeffect "", "nro,nro"(i32 %0, i32 %1)
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20 ret void
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21 }
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22
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23 ; CHECK-LABEL: test_constraint_I:
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236
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24 ; CHECK: add %i0, 1023, %i0
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150
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25 define i32 @test_constraint_I(i32 %a) {
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26 entry:
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27 %0 = tail call i32 asm sideeffect "add $1, $2, $0", "=r,r,rI"(i32 %a, i32 1023)
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28 ret i32 %0
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29 }
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30
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31 ; CHECK-LABEL: test_constraint_I_neg:
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236
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32 ; CHECK: add %i0, -4096, %i0
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150
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33 define i32 @test_constraint_I_neg(i32 %a) {
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34 entry:
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35 %0 = tail call i32 asm sideeffect "add $1, $2, $0", "=r,r,rI"(i32 %a, i32 -4096)
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36 ret i32 %0
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37 }
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38
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39 ; CHECK-LABEL: test_constraint_I_largeimm:
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40 ; CHECK: sethi 9, [[R0:%[gilo][0-7]]]
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41 ; CHECK: or [[R0]], 784, [[R1:%[gilo][0-7]]]
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236
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42 ; CHECK: add %i0, [[R1]], %i0
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150
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43 define i32 @test_constraint_I_largeimm(i32 %a) {
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44 entry:
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45 %0 = tail call i32 asm sideeffect "add $1, $2, $0", "=r,r,rI"(i32 %a, i32 10000)
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46 ret i32 %0
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47 }
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48
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49 ; CHECK-LABEL: test_constraint_reg:
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236
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50 ; CHECK: ldda [%i1] 43, %g2
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51 ; CHECK: ldda [%i1] 43, %g4
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150
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52 define void @test_constraint_reg(i32 %s, i32* %ptr) {
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53 entry:
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54 %0 = tail call i64 asm sideeffect "ldda [$1] $2, $0", "={r2},r,n"(i32* %ptr, i32 43)
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55 %1 = tail call i64 asm sideeffect "ldda [$1] $2, $0", "={g4},r,n"(i32* %ptr, i32 43)
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56 ret void
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57 }
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58
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59 ;; Ensure that i64 args to asm are allocated to the IntPair register class.
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236
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60 ;; Also checks that there's no register renaming for leaf proc if it has inline asm.
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150
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61 ; CHECK-LABEL: test_constraint_r_i64:
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236
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62 ; CHECK: mov %i0, %i5
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63 ; CHECK: sra %i5, 31, %i4
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64 ; CHECK: std %i4, [%i1]
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150
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65 define i32 @test_constraint_r_i64(i32 %foo, i64* %out, i32 %o) {
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66 entry:
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67 %conv = sext i32 %foo to i64
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68 tail call void asm sideeffect "std $0, [$1]", "r,r,~{memory}"(i64 %conv, i64* %out)
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69 ret i32 %o
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70 }
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71
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72 ;; Same test without leaf-proc opt
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73 ; CHECK-LABEL: test_constraint_r_i64_noleaf:
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74 ; CHECK: mov %i0, %i5
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75 ; CHECK: sra %i5, 31, %i4
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76 ; CHECK: std %i4, [%i1]
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77 define i32 @test_constraint_r_i64_noleaf(i32 %foo, i64* %out, i32 %o) #0 {
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78 entry:
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79 %conv = sext i32 %foo to i64
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80 tail call void asm sideeffect "std $0, [$1]", "r,r,~{memory}"(i64 %conv, i64* %out)
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81 ret i32 %o
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82 }
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83 attributes #0 = { "frame-pointer"="all" }
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84
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85 ;; Ensures that tied in and out gets allocated properly.
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86 ; CHECK-LABEL: test_i64_inout:
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252
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87 ; CHECK: mov 5, %i3
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236
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88 ; CHECK: mov %g0, %i2
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89 ; CHECK: xor %i2, %g0, %i2
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90 ; CHECK: mov %i2, %i0
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150
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91 ; CHECK: ret
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92 define i64 @test_i64_inout() {
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93 entry:
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94 %0 = call i64 asm sideeffect "xor $1, %g0, $0", "=r,0,~{i1}"(i64 5);
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95 ret i64 %0
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96 }
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97
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98
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99 ;; Ensures that inline-asm accepts and uses 'f' and 'e' register constraints.
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100 ; CHECK-LABEL: fadds:
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101 ; CHECK: fadds %f0, %f1, %f0
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102 define float @fadds(float, float) local_unnamed_addr #2 {
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103 entry:
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104 %2 = tail call float asm sideeffect "fadds $1, $2, $0;", "=f,f,e"(float %0, float %1) #7
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105 ret float %2
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106 }
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107
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108 ; CHECK-LABEL: faddd:
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109 ; CHECK: faddd %f0, %f2, %f0
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110 define double @faddd(double, double) local_unnamed_addr #2 {
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111 entry:
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112 %2 = tail call double asm sideeffect "faddd $1, $2, $0;", "=f,f,e"(double %0, double %1) #7
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113 ret double %2
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114 }
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115
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116 ; CHECK-LABEL: test_addressing_mode_i64:
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236
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117 ; CHECK: std %l0, [%i0]
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150
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118 define void @test_addressing_mode_i64(i64* %out) {
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119 entry:
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236
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120 call void asm "std %l0, $0", "=*m,r"(i64* elementtype(i64) nonnull %out, i64 0)
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150
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121 ret void
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122 }
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123
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124 ; CHECK-LABEL: test_constraint_float_reg:
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125 ; CHECK: fadds %f20, %f20, %f20
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126 ; CHECK: faddd %f20, %f20, %f20
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127 define void @test_constraint_float_reg() {
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128 entry:
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129 tail call void asm sideeffect "fadds $0,$1,$2", "{f20},{f20},{f20}"(float 6.0, float 7.0, float 8.0)
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130 tail call void asm sideeffect "faddd $0,$1,$2", "{f20},{f20},{f20}"(double 9.0, double 10.0, double 11.0)
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131 ret void
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132 }
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133
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134 ; CHECK-LABEL: test_constraint_f_e_i32_i64:
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236
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135 ; CHECK: ld [%i0+%lo(.LCPI13_0)], %f0
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136 ; CHECK: ldd [%i0+%lo(.LCPI13_1)], %f2
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150
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137 ; CHECK: fadds %f0, %f0, %f0
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138 ; CHECK: faddd %f2, %f2, %f0
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139
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140 define void @test_constraint_f_e_i32_i64() {
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141 entry:
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142 %0 = call float asm sideeffect "fadds $1, $2, $0", "=f,f,e"(i32 0, i32 0)
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143 %1 = call double asm sideeffect "faddd $1, $2, $0", "=f,f,e"(i64 0, i64 0)
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144 ret void
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145 }
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