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annotate llvm/test/TableGen/GlobalISelEmitter-zero-reg.td @ 266:00f31e85ec16 default tip

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Added tag current for changeset 31d058e83c98
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Sat, 14 Oct 2023 10:13:55 +0900
parents 2e18cbf3894f
children
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Shinji KONO <kono@ie.u-ryukyu.ac.jp>
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1 // RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s
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2
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3 include "llvm/Target/Target.td"
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4 include "GlobalISelEmitterCommon.td"
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5
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6 def P0 : Register<"p0"> { let Namespace = "MyTarget"; }
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7 def PR32 : RegisterClass<"MyTarget", [i32], 32, (add P0)>;
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8 def PR32Op : RegisterOperand<PR32>;
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9
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10 def pred : PredicateOperand<OtherVT,
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11 (ops PR32:$FR),
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12 (ops (i32 zero_reg))> {}
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13 class PredI<dag OOps, dag IOps, list<dag> Pat>
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14 : Instruction {
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15 let Namespace = "MyTarget";
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16 let OutOperandList = OOps;
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17 let InOperandList = !con(IOps, (ins pred:$pred));
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18 let Pattern = Pat;
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19 }
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20
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21 def INST : PredI<(outs GPR32:$dst), (ins GPR32:$src), []>;
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22
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23 // CHECK: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
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24 // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_LOAD,
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25 // CHECK-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
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26 // CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
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27 // CHECK-NEXT: // MIs[0] dst
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28 // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
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29 // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
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30 // CHECK-NEXT: // MIs[0] src
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31 // CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
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32 // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
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33 // CHECK-NEXT: // (ld:{ *:[i32] } GPR32:{ *:[i32] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (INST:{ *:[i32] } GPR32:{ *:[i32] }:$src)
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34 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::INST,
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35 // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
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36 // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
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37 // CHECK-NEXT: GIR_AddRegister, /*InsnID*/0, MyTarget::NoRegister, /*AddRegisterRegFlags*/0,
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38 // CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
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39 // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
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40 // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
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41 def : Pat<(i32 (load GPR32:$src)),
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42 (INST GPR32:$src)>;