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150
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1 // This test describes how we eventually want to describe instructions in
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2 // the target independent code generators.
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3 // RUN: llvm-tblgen %s
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4 // XFAIL: vg_leak
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5
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6 // Target indep stuff.
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7 class Instruction { // Would have other stuff eventually
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8 bit isTwoAddress = 0;
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9 string AssemblyString;
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10 }
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11 class RegisterClass;
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12
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13 class RTLNode;
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14
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15 def ops; // Marker for operand list.
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16
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17 // Various expressions used in RTL descriptions.
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18 def imm8 : RTLNode;
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19 def imm32 : RTLNode;
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20 def addr : RTLNode;
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21
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22 def set : RTLNode;
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23 def signext : RTLNode;
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24 def zeroext : RTLNode;
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25 def plus : RTLNode;
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26 def and : RTLNode;
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27 def xor : RTLNode;
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28 def shl : RTLNode;
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29 def load : RTLNode;
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30 def store : RTLNode;
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31 def unspec : RTLNode;
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32
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33 // Start of X86 specific stuff.
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34
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35 def R8 : RegisterClass;
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36 def R16 : RegisterClass;
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37 def R32 : RegisterClass;
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38
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39 def CL; // As are currently defined
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40 def AL;
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41 def AX;
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42 def EDX;
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43
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44 class Format<bits<5> val> {
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45 bits<5> Value = val;
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46 }
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47
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48 def Pseudo : Format<0>; def RawFrm : Format<1>;
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49 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
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50 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
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51 def MRMSrcMem : Format<6>;
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52 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
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53 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
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54 def MRM6r : Format<22>; def MRM7r : Format<23>;
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55 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
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56 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
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57 def MRM6m : Format<30>; def MRM7m : Format<31>;
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58
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59
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60 class Inst<dag opnds, string asmstr, bits<8> opcode,
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61 Format f, list<dag> rtl> : Instruction {
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62 dag Operands = opnds;
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63 string AssemblyString = asmstr;
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64 bits<8> Opcode = opcode;
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65 Format Format = f;
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66 list<dag> RTL = rtl;
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67 }
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68
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69
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70 // Start of instruction definitions, the real point of this file.
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71 //
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72 // Note that these patterns show a couple of important things:
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73 // 1. The order and contents of the operands of the MachineInstr are
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74 // described here. Eventually we can do away with this when everything
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75 // is generated from the description.
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76 // 2. The asm string is captured here, which makes it possible to get rid of
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77 // a ton of hacks in the various printers and a bunch of flags.
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78 // 3. Target specific properties (e.g. Format) can still be captured as
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79 // needed.
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80 // 4. We capture the behavior of the instruction with a simplified RTL-like
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81 // expression.
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82 // 5. The use/def properties for each operand are automatically inferred from
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83 // the pattern.
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84 // 6. Address expressions should become first-class entities.
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85
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86 // Simple copy instruction.
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87 def MOV8rr : Inst<(ops R8:$dst, R8:$src),
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88 "mov $dst, $src", 0x88, MRMDestReg,
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89 [(set R8:$dst, R8:$src)]>;
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90
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91 // Simple immediate initialization.
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92 def MOV8ri : Inst<(ops R8:$dst, imm8:$src),
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93 "mov $dst, $src", 0xB0, AddRegFrm,
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94 [(set R8:$dst, imm8:$src)]>;
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95
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96 // Two address instructions are described as three-addr instructions, with
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97 // the special target-independent isTwoAddress flag set. The asm pattern
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98 // should not refer to the $src1, this would be enforced by the
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99 // TargetInstrInfo tablegen backend.
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100 let isTwoAddress = 1 in
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101 def AND8rr : Inst<(ops R8:$dst, R8:$src1, R8:$src2),
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102 "and $dst, $src2", 0x20, MRMDestReg,
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103 [(set R8:$dst, (and R8:$src1, R8:$src2))]>;
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104
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105 // Instructions that have explicit uses/defs make them explicit in the RTL.
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106 // Instructions that need extra stuff emitted in the assembly can, trivially.
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107 let isTwoAddress = 1 in
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108 def SHL32rCL : Inst<(ops R32:$dst, R32:$src),
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109 "shl $dst, CL", 0xD2, MRM4r,
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110 [(set R32:$dst, (shl R32:$src, CL))]>;
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111
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112 // The RTL list is a list, allowing complex instructions to be defined easily.
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113 // Temporary 'internal' registers can be used to break instructions apart.
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114 let isTwoAddress = 1 in
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115 def XOR32mi : Inst<(ops addr:$addr, imm32:$imm),
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116 "xor $dst, $src2", 0x81, MRM6m,
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117 [(set R32:$tmp1, (load addr:$addr)),
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118 (set R32:$tmp2, (xor R32:$tmp1, imm32:$imm)),
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119 (store addr:$addr, R32:$tmp2)]>;
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120
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121 // Alternatively, if each tmporary register is only used once, the instruction
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122 // can just be described in nested form. This would be the canonical
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123 // representation the target generator would convert the above into. Pick your
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124 // favorite indentation scheme.
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125 let isTwoAddress = 1 in
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126 def AND32mr : Inst<(ops addr:$addr, R32:$src),
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127 "xor $dst, $src2", 0x81, MRM6m,
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128 [(store addr:$addr,
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129 (and
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130 (load addr:$addr),
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131 R32:$src)
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132 )
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133 ]>;
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134
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135 // Describing complex instructions is not too hard! Note how implicit uses/defs
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136 // become explicit here.
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137 def CBW : Inst<(ops),
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138 "cbw", 0x98, RawFrm,
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139 [(set AX, (signext AL))]>;
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140
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141 // Noop, does nothing.
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142 def NOOP : Inst<(ops), "nop", 0x90, RawFrm, []>;
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143
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144
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145 // Instructions that don't expect optimization can use unspec.
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146 def IN8rr : Inst<(ops), "in AL, EDX", 0xEC, RawFrm,
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147 [(set AL, (unspec EDX))]>;
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148
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