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annotate llvm/test/TableGen/gisel-physreg-input.td @ 266:00f31e85ec16 default tip

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Added tag current for changeset 31d058e83c98
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Sat, 14 Oct 2023 10:13:55 +0900
parents 1d019706d866
children
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rev   line source
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1 // RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
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2
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3 include "llvm/Target/Target.td"
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4
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5 def TestTargetInstrInfo : InstrInfo;
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6
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7 def TestTarget : Target {
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8 let InstructionSet = TestTargetInstrInfo;
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9 }
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10
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11 def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
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12 def SPECIAL : Register<"special"> { let Namespace = "MyTarget"; }
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13 def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
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14 def Special32 : RegisterClass<"MyTarget", [i32], 32, (add SPECIAL)>;
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15
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16
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17 class I<dag OOps, dag IOps, list<dag> Pat>
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18 : Instruction {
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19 let Namespace = "MyTarget";
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20 let OutOperandList = OOps;
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21 let InOperandList = IOps;
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22 let Pattern = Pat;
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23 }
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24
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25 // Try a normal physical register use.
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26
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27 // GISEL: GIM_Try,
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28 // GISEL-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
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29 // GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD,
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30 // GISEL-NEXT: // MIs[0] dst
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31 // GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
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32 // GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
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33 // GISEL-NEXT: // MIs[0] src0
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34 // GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
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35 // GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
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36 // GISEL-NEXT: // MIs[0] Operand 2
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37 // GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
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38 // GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::Special32RegClassID,
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39 // GISEL-NEXT: // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src0, SPECIAL:{ *:[i32] }) => (ADD_PHYS:{ *:[i32] } GPR32:{ *:[i32] }:$src0)
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40 // GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
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41 // GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, MyTarget::SPECIAL, /*AddRegisterRegFlags*/RegState::Define,
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42 // GISEL-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // SPECIAL
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43 // GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::ADD_PHYS,
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44 // GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
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45 // GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
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46 // GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0,
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47 // GISEL-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
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48 def ADD_PHYS : I<(outs GPR32:$dst), (ins GPR32:$src0),
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49 [(set GPR32:$dst, (add GPR32:$src0, SPECIAL))]> {
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50 let Uses = [SPECIAL];
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51 }
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52
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53 // Try using the name of the physreg in another operand.
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54
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55 // GISEL: GIM_Try,
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56 // GISEL-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
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57 // GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_MUL,
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58 // GISEL-NEXT: // MIs[0] dst
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59 // GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
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60 // GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
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61 // GISEL-NEXT: // MIs[0] SPECIAL
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62 // GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
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63 // GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
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64 // GISEL-NEXT: // MIs[0] Operand 2
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65 // GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
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66 // GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::Special32RegClassID,
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67 // GISEL-NEXT: // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$SPECIAL, SPECIAL:{ *:[i32] }) => (MUL_PHYS:{ *:[i32] } GPR32:{ *:[i32] }:$SPECIAL)
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68 // GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
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69 // GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, MyTarget::SPECIAL, /*AddRegisterRegFlags*/RegState::Define,
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70 // GISEL-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // SPECIAL
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71 // GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MUL_PHYS,
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72 // GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
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73 // GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // SPECIAL
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74 // GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0,
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75 // GISEL-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
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76 def MUL_PHYS : I<(outs GPR32:$dst), (ins GPR32:$SPECIAL),
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77 [(set GPR32:$dst, (mul GPR32:$SPECIAL, SPECIAL))]> {
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78 let Uses = [SPECIAL];
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79 }
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80
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81 // Try giving the physical operand a name
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82 // def ADD_PHYS : I<(outs GPR32:$dst), (ins GPR32:$src0),
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83 // [(set GPR32:$dst, (add GPR32:$src0, SPECIAL:$special))]> {
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84 // let Uses = [SPECIAL];
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85 // }