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annotate llvm/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink.ll @ 266:00f31e85ec16 default tip

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Added tag current for changeset 31d058e83c98
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Sat, 14 Oct 2023 10:13:55 +0900
parents 1f2b6ac9f198
children
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1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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2 ; RUN: opt -S -codegenprepare -mcpu=corei7 %s | FileCheck %s --check-prefixes=CHECK,CHECK-SSE2
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3 ; RUN: opt -S -codegenprepare -mcpu=bdver2 %s | FileCheck %s --check-prefixes=CHECK,CHECK-XOP
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4 ; RUN: opt -S -codegenprepare -mcpu=core-avx2 %s | FileCheck %s --check-prefixes=CHECK,CHECK-AVX,CHECK-AVX2
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5 ; RUN: opt -S -codegenprepare -mcpu=skylake-avx512 %s | FileCheck %s --check-prefixes=CHECK,CHECK-AVX,CHECK-AVX512BW
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6
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7 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
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8 target triple = "x86_64-apple-darwin10.9.0"
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9
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10 define <16 x i8> @test_8bit(<16 x i8> %lhs, <16 x i8> %tmp, i1 %tst) {
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11 ; CHECK-SSE2-LABEL: @test_8bit(
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12 ; CHECK-SSE2-NEXT: [[MASK:%.*]] = shufflevector <16 x i8> [[TMP:%.*]], <16 x i8> undef, <16 x i32> zeroinitializer
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13 ; CHECK-SSE2-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
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14 ; CHECK-SSE2: if_true:
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15 ; CHECK-SSE2-NEXT: ret <16 x i8> [[MASK]]
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16 ; CHECK-SSE2: if_false:
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17 ; CHECK-SSE2-NEXT: [[TMP1:%.*]] = shufflevector <16 x i8> [[TMP]], <16 x i8> undef, <16 x i32> zeroinitializer
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18 ; CHECK-SSE2-NEXT: [[RES:%.*]] = shl <16 x i8> [[LHS:%.*]], [[TMP1]]
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19 ; CHECK-SSE2-NEXT: ret <16 x i8> [[RES]]
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20 ;
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21 ; CHECK-XOP-LABEL: @test_8bit(
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22 ; CHECK-XOP-NEXT: [[MASK:%.*]] = shufflevector <16 x i8> [[TMP:%.*]], <16 x i8> undef, <16 x i32> zeroinitializer
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23 ; CHECK-XOP-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
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24 ; CHECK-XOP: if_true:
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25 ; CHECK-XOP-NEXT: ret <16 x i8> [[MASK]]
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26 ; CHECK-XOP: if_false:
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27 ; CHECK-XOP-NEXT: [[RES:%.*]] = shl <16 x i8> [[LHS:%.*]], [[MASK]]
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28 ; CHECK-XOP-NEXT: ret <16 x i8> [[RES]]
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29 ;
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30 ; CHECK-AVX-LABEL: @test_8bit(
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31 ; CHECK-AVX-NEXT: [[MASK:%.*]] = shufflevector <16 x i8> [[TMP:%.*]], <16 x i8> undef, <16 x i32> zeroinitializer
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32 ; CHECK-AVX-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
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33 ; CHECK-AVX: if_true:
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34 ; CHECK-AVX-NEXT: ret <16 x i8> [[MASK]]
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35 ; CHECK-AVX: if_false:
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36 ; CHECK-AVX-NEXT: [[TMP1:%.*]] = shufflevector <16 x i8> [[TMP]], <16 x i8> undef, <16 x i32> zeroinitializer
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37 ; CHECK-AVX-NEXT: [[RES:%.*]] = shl <16 x i8> [[LHS:%.*]], [[TMP1]]
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38 ; CHECK-AVX-NEXT: ret <16 x i8> [[RES]]
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39 ;
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40 %mask = shufflevector <16 x i8> %tmp, <16 x i8> undef, <16 x i32> zeroinitializer
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41 br i1 %tst, label %if_true, label %if_false
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42
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43 if_true:
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44 ret <16 x i8> %mask
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45
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46 if_false:
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47 %res = shl <16 x i8> %lhs, %mask
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48 ret <16 x i8> %res
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49 }
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50
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51 define <8 x i16> @test_16bit(<8 x i16> %lhs, <8 x i16> %tmp, i1 %tst) {
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52 ; CHECK-SSE2-LABEL: @test_16bit(
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53 ; CHECK-SSE2-NEXT: [[MASK:%.*]] = shufflevector <8 x i16> [[TMP:%.*]], <8 x i16> undef, <8 x i32> zeroinitializer
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54 ; CHECK-SSE2-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
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55 ; CHECK-SSE2: if_true:
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56 ; CHECK-SSE2-NEXT: ret <8 x i16> [[MASK]]
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57 ; CHECK-SSE2: if_false:
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58 ; CHECK-SSE2-NEXT: [[TMP1:%.*]] = shufflevector <8 x i16> [[TMP]], <8 x i16> undef, <8 x i32> zeroinitializer
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59 ; CHECK-SSE2-NEXT: [[RES:%.*]] = shl <8 x i16> [[LHS:%.*]], [[TMP1]]
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60 ; CHECK-SSE2-NEXT: ret <8 x i16> [[RES]]
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61 ;
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62 ; CHECK-XOP-LABEL: @test_16bit(
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63 ; CHECK-XOP-NEXT: [[MASK:%.*]] = shufflevector <8 x i16> [[TMP:%.*]], <8 x i16> undef, <8 x i32> zeroinitializer
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64 ; CHECK-XOP-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
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65 ; CHECK-XOP: if_true:
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66 ; CHECK-XOP-NEXT: ret <8 x i16> [[MASK]]
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67 ; CHECK-XOP: if_false:
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68 ; CHECK-XOP-NEXT: [[RES:%.*]] = shl <8 x i16> [[LHS:%.*]], [[MASK]]
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69 ; CHECK-XOP-NEXT: ret <8 x i16> [[RES]]
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70 ;
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71 ; CHECK-AVX2-LABEL: @test_16bit(
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72 ; CHECK-AVX2-NEXT: [[MASK:%.*]] = shufflevector <8 x i16> [[TMP:%.*]], <8 x i16> undef, <8 x i32> zeroinitializer
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73 ; CHECK-AVX2-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
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74 ; CHECK-AVX2: if_true:
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75 ; CHECK-AVX2-NEXT: ret <8 x i16> [[MASK]]
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76 ; CHECK-AVX2: if_false:
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77 ; CHECK-AVX2-NEXT: [[TMP1:%.*]] = shufflevector <8 x i16> [[TMP]], <8 x i16> undef, <8 x i32> zeroinitializer
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78 ; CHECK-AVX2-NEXT: [[RES:%.*]] = shl <8 x i16> [[LHS:%.*]], [[TMP1]]
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79 ; CHECK-AVX2-NEXT: ret <8 x i16> [[RES]]
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80 ;
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81 ; CHECK-AVX512BW-LABEL: @test_16bit(
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82 ; CHECK-AVX512BW-NEXT: [[MASK:%.*]] = shufflevector <8 x i16> [[TMP:%.*]], <8 x i16> undef, <8 x i32> zeroinitializer
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83 ; CHECK-AVX512BW-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
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84 ; CHECK-AVX512BW: if_true:
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85 ; CHECK-AVX512BW-NEXT: ret <8 x i16> [[MASK]]
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86 ; CHECK-AVX512BW: if_false:
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87 ; CHECK-AVX512BW-NEXT: [[RES:%.*]] = shl <8 x i16> [[LHS:%.*]], [[MASK]]
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88 ; CHECK-AVX512BW-NEXT: ret <8 x i16> [[RES]]
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89 ;
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90 %mask = shufflevector <8 x i16> %tmp, <8 x i16> undef, <8 x i32> zeroinitializer
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91 br i1 %tst, label %if_true, label %if_false
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92
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93 if_true:
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94 ret <8 x i16> %mask
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95
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96 if_false:
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97 %res = shl <8 x i16> %lhs, %mask
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98 ret <8 x i16> %res
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99 }
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100
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101 define <4 x i32> @test_notsplat(<4 x i32> %lhs, <4 x i32> %tmp, i1 %tst) {
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102 ; CHECK-LABEL: @test_notsplat(
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103 ; CHECK-NEXT: [[MASK:%.*]] = shufflevector <4 x i32> [[TMP:%.*]], <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 1, i32 0>
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104 ; CHECK-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
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105 ; CHECK: if_true:
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106 ; CHECK-NEXT: ret <4 x i32> [[MASK]]
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107 ; CHECK: if_false:
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108 ; CHECK-NEXT: [[RES:%.*]] = shl <4 x i32> [[LHS:%.*]], [[MASK]]
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109 ; CHECK-NEXT: ret <4 x i32> [[RES]]
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110 ;
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111 %mask = shufflevector <4 x i32> %tmp, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 1, i32 0>
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112 br i1 %tst, label %if_true, label %if_false
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113
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114 if_true:
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115 ret <4 x i32> %mask
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116
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117 if_false:
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118 %res = shl <4 x i32> %lhs, %mask
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119 ret <4 x i32> %res
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120 }
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121
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122 define <4 x i32> @test_32bit(<4 x i32> %lhs, <4 x i32> %tmp, i1 %tst) {
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123 ; CHECK-SSE2-LABEL: @test_32bit(
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124 ; CHECK-SSE2-NEXT: [[MASK:%.*]] = shufflevector <4 x i32> [[TMP:%.*]], <4 x i32> undef, <4 x i32> <i32 0, i32 poison, i32 0, i32 0>
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125 ; CHECK-SSE2-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
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126 ; CHECK-SSE2: if_true:
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127 ; CHECK-SSE2-NEXT: ret <4 x i32> [[MASK]]
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128 ; CHECK-SSE2: if_false:
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129 ; CHECK-SSE2-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[TMP]], <4 x i32> undef, <4 x i32> <i32 0, i32 poison, i32 0, i32 0>
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130 ; CHECK-SSE2-NEXT: [[RES:%.*]] = ashr <4 x i32> [[LHS:%.*]], [[TMP1]]
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131 ; CHECK-SSE2-NEXT: ret <4 x i32> [[RES]]
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132 ;
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133 ; CHECK-XOP-LABEL: @test_32bit(
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134 ; CHECK-XOP-NEXT: [[MASK:%.*]] = shufflevector <4 x i32> [[TMP:%.*]], <4 x i32> undef, <4 x i32> <i32 0, i32 poison, i32 0, i32 0>
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135 ; CHECK-XOP-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
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136 ; CHECK-XOP: if_true:
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137 ; CHECK-XOP-NEXT: ret <4 x i32> [[MASK]]
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138 ; CHECK-XOP: if_false:
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139 ; CHECK-XOP-NEXT: [[RES:%.*]] = ashr <4 x i32> [[LHS:%.*]], [[MASK]]
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140 ; CHECK-XOP-NEXT: ret <4 x i32> [[RES]]
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141 ;
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142 ; CHECK-AVX-LABEL: @test_32bit(
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143 ; CHECK-AVX-NEXT: [[MASK:%.*]] = shufflevector <4 x i32> [[TMP:%.*]], <4 x i32> undef, <4 x i32> <i32 0, i32 poison, i32 0, i32 0>
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144 ; CHECK-AVX-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
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145 ; CHECK-AVX: if_true:
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146 ; CHECK-AVX-NEXT: ret <4 x i32> [[MASK]]
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147 ; CHECK-AVX: if_false:
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148 ; CHECK-AVX-NEXT: [[RES:%.*]] = ashr <4 x i32> [[LHS:%.*]], [[MASK]]
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149 ; CHECK-AVX-NEXT: ret <4 x i32> [[RES]]
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150 ;
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151 %mask = shufflevector <4 x i32> %tmp, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 0, i32 0>
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152 br i1 %tst, label %if_true, label %if_false
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153
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154 if_true:
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155 ret <4 x i32> %mask
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156
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157 if_false:
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158 %res = ashr <4 x i32> %lhs, %mask
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159 ret <4 x i32> %res
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160 }
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161
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162 define <2 x i64> @test_64bit(<2 x i64> %lhs, <2 x i64> %tmp, i1 %tst) {
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163 ; CHECK-SSE2-LABEL: @test_64bit(
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164 ; CHECK-SSE2-NEXT: [[MASK:%.*]] = shufflevector <2 x i64> [[TMP:%.*]], <2 x i64> undef, <2 x i32> zeroinitializer
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165 ; CHECK-SSE2-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
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166 ; CHECK-SSE2: if_true:
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167 ; CHECK-SSE2-NEXT: ret <2 x i64> [[MASK]]
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168 ; CHECK-SSE2: if_false:
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169 ; CHECK-SSE2-NEXT: [[TMP1:%.*]] = shufflevector <2 x i64> [[TMP]], <2 x i64> undef, <2 x i32> zeroinitializer
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170 ; CHECK-SSE2-NEXT: [[RES:%.*]] = lshr <2 x i64> [[LHS:%.*]], [[TMP1]]
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171 ; CHECK-SSE2-NEXT: ret <2 x i64> [[RES]]
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172 ;
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173 ; CHECK-XOP-LABEL: @test_64bit(
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174 ; CHECK-XOP-NEXT: [[MASK:%.*]] = shufflevector <2 x i64> [[TMP:%.*]], <2 x i64> undef, <2 x i32> zeroinitializer
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175 ; CHECK-XOP-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
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176 ; CHECK-XOP: if_true:
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177 ; CHECK-XOP-NEXT: ret <2 x i64> [[MASK]]
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178 ; CHECK-XOP: if_false:
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179 ; CHECK-XOP-NEXT: [[RES:%.*]] = lshr <2 x i64> [[LHS:%.*]], [[MASK]]
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180 ; CHECK-XOP-NEXT: ret <2 x i64> [[RES]]
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181 ;
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182 ; CHECK-AVX-LABEL: @test_64bit(
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183 ; CHECK-AVX-NEXT: [[MASK:%.*]] = shufflevector <2 x i64> [[TMP:%.*]], <2 x i64> undef, <2 x i32> zeroinitializer
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184 ; CHECK-AVX-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
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185 ; CHECK-AVX: if_true:
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186 ; CHECK-AVX-NEXT: ret <2 x i64> [[MASK]]
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187 ; CHECK-AVX: if_false:
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188 ; CHECK-AVX-NEXT: [[RES:%.*]] = lshr <2 x i64> [[LHS:%.*]], [[MASK]]
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189 ; CHECK-AVX-NEXT: ret <2 x i64> [[RES]]
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190 ;
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191 %mask = shufflevector <2 x i64> %tmp, <2 x i64> undef, <2 x i32> zeroinitializer
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192 br i1 %tst, label %if_true, label %if_false
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193
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194 if_true:
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195 ret <2 x i64> %mask
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196
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197 if_false:
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198 %res = lshr <2 x i64> %lhs, %mask
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199 ret <2 x i64> %res
anatofuz
parents:
diff changeset
200 }
173
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Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
201
252
1f2b6ac9f198 LLVM16-1
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 236
diff changeset
202 define void @funnel_splatvar(ptr nocapture %arr, i32 %rot) {
173
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parents: 150
diff changeset
203 ; CHECK-SSE2-LABEL: @funnel_splatvar(
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parents: 150
diff changeset
204 ; CHECK-SSE2-NEXT: entry:
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Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
205 ; CHECK-SSE2-NEXT: [[BROADCAST_SPLATINSERT15:%.*]] = insertelement <8 x i32> undef, i32 [[ROT:%.*]], i32 0
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parents: 150
diff changeset
206 ; CHECK-SSE2-NEXT: br label [[VECTOR_BODY:%.*]]
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Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
207 ; CHECK-SSE2: vector.body:
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Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
208 ; CHECK-SSE2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
252
1f2b6ac9f198 LLVM16-1
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parents: 236
diff changeset
209 ; CHECK-SSE2-NEXT: [[T0:%.*]] = getelementptr inbounds i32, ptr [[ARR:%.*]], i64 [[INDEX]]
1f2b6ac9f198 LLVM16-1
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 236
diff changeset
210 ; CHECK-SSE2-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i32>, ptr [[T0]], align 4
173
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parents: 150
diff changeset
211 ; CHECK-SSE2-NEXT: [[TMP0:%.*]] = shufflevector <8 x i32> [[BROADCAST_SPLATINSERT15]], <8 x i32> undef, <8 x i32> zeroinitializer
0572611fdcc8 reorgnization done
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parents: 150
diff changeset
212 ; CHECK-SSE2-NEXT: [[T2:%.*]] = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> [[WIDE_LOAD]], <8 x i32> [[WIDE_LOAD]], <8 x i32> [[TMP0]])
252
1f2b6ac9f198 LLVM16-1
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parents: 236
diff changeset
213 ; CHECK-SSE2-NEXT: store <8 x i32> [[T2]], ptr [[T0]], align 4
173
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parents: 150
diff changeset
214 ; CHECK-SSE2-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 8
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parents: 150
diff changeset
215 ; CHECK-SSE2-NEXT: [[T3:%.*]] = icmp eq i64 [[INDEX_NEXT]], 65536
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parents: 150
diff changeset
216 ; CHECK-SSE2-NEXT: br i1 [[T3]], label [[FOR_COND_CLEANUP:%.*]], label [[VECTOR_BODY]]
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parents: 150
diff changeset
217 ; CHECK-SSE2: for.cond.cleanup:
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parents: 150
diff changeset
218 ; CHECK-SSE2-NEXT: ret void
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parents: 150
diff changeset
219 ;
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parents: 150
diff changeset
220 ; CHECK-XOP-LABEL: @funnel_splatvar(
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parents: 150
diff changeset
221 ; CHECK-XOP-NEXT: entry:
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parents: 150
diff changeset
222 ; CHECK-XOP-NEXT: [[BROADCAST_SPLATINSERT15:%.*]] = insertelement <8 x i32> undef, i32 [[ROT:%.*]], i32 0
0572611fdcc8 reorgnization done
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
223 ; CHECK-XOP-NEXT: [[BROADCAST_SPLAT16:%.*]] = shufflevector <8 x i32> [[BROADCAST_SPLATINSERT15]], <8 x i32> undef, <8 x i32> zeroinitializer
0572611fdcc8 reorgnization done
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parents: 150
diff changeset
224 ; CHECK-XOP-NEXT: br label [[VECTOR_BODY:%.*]]
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Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
225 ; CHECK-XOP: vector.body:
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Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
226 ; CHECK-XOP-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
252
1f2b6ac9f198 LLVM16-1
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 236
diff changeset
227 ; CHECK-XOP-NEXT: [[T0:%.*]] = getelementptr inbounds i32, ptr [[ARR:%.*]], i64 [[INDEX]]
1f2b6ac9f198 LLVM16-1
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 236
diff changeset
228 ; CHECK-XOP-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i32>, ptr [[T0]], align 4
173
0572611fdcc8 reorgnization done
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parents: 150
diff changeset
229 ; CHECK-XOP-NEXT: [[T2:%.*]] = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> [[WIDE_LOAD]], <8 x i32> [[WIDE_LOAD]], <8 x i32> [[BROADCAST_SPLAT16]])
252
1f2b6ac9f198 LLVM16-1
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 236
diff changeset
230 ; CHECK-XOP-NEXT: store <8 x i32> [[T2]], ptr [[T0]], align 4
173
0572611fdcc8 reorgnization done
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parents: 150
diff changeset
231 ; CHECK-XOP-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 8
0572611fdcc8 reorgnization done
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
232 ; CHECK-XOP-NEXT: [[T3:%.*]] = icmp eq i64 [[INDEX_NEXT]], 65536
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Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
233 ; CHECK-XOP-NEXT: br i1 [[T3]], label [[FOR_COND_CLEANUP:%.*]], label [[VECTOR_BODY]]
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parents: 150
diff changeset
234 ; CHECK-XOP: for.cond.cleanup:
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parents: 150
diff changeset
235 ; CHECK-XOP-NEXT: ret void
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parents: 150
diff changeset
236 ;
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parents: 150
diff changeset
237 ; CHECK-AVX-LABEL: @funnel_splatvar(
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parents: 150
diff changeset
238 ; CHECK-AVX-NEXT: entry:
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parents: 150
diff changeset
239 ; CHECK-AVX-NEXT: [[BROADCAST_SPLATINSERT15:%.*]] = insertelement <8 x i32> undef, i32 [[ROT:%.*]], i32 0
0572611fdcc8 reorgnization done
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
240 ; CHECK-AVX-NEXT: [[BROADCAST_SPLAT16:%.*]] = shufflevector <8 x i32> [[BROADCAST_SPLATINSERT15]], <8 x i32> undef, <8 x i32> zeroinitializer
0572611fdcc8 reorgnization done
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parents: 150
diff changeset
241 ; CHECK-AVX-NEXT: br label [[VECTOR_BODY:%.*]]
0572611fdcc8 reorgnization done
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
242 ; CHECK-AVX: vector.body:
0572611fdcc8 reorgnization done
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
243 ; CHECK-AVX-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
252
1f2b6ac9f198 LLVM16-1
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 236
diff changeset
244 ; CHECK-AVX-NEXT: [[T0:%.*]] = getelementptr inbounds i32, ptr [[ARR:%.*]], i64 [[INDEX]]
1f2b6ac9f198 LLVM16-1
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 236
diff changeset
245 ; CHECK-AVX-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i32>, ptr [[T0]], align 4
173
0572611fdcc8 reorgnization done
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
246 ; CHECK-AVX-NEXT: [[T2:%.*]] = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> [[WIDE_LOAD]], <8 x i32> [[WIDE_LOAD]], <8 x i32> [[BROADCAST_SPLAT16]])
252
1f2b6ac9f198 LLVM16-1
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 236
diff changeset
247 ; CHECK-AVX-NEXT: store <8 x i32> [[T2]], ptr [[T0]], align 4
173
0572611fdcc8 reorgnization done
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
248 ; CHECK-AVX-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 8
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Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
249 ; CHECK-AVX-NEXT: [[T3:%.*]] = icmp eq i64 [[INDEX_NEXT]], 65536
0572611fdcc8 reorgnization done
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
250 ; CHECK-AVX-NEXT: br i1 [[T3]], label [[FOR_COND_CLEANUP:%.*]], label [[VECTOR_BODY]]
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parents: 150
diff changeset
251 ; CHECK-AVX: for.cond.cleanup:
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Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
252 ; CHECK-AVX-NEXT: ret void
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Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
253 ;
0572611fdcc8 reorgnization done
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parents: 150
diff changeset
254 entry:
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parents: 150
diff changeset
255 %broadcast.splatinsert15 = insertelement <8 x i32> undef, i32 %rot, i32 0
0572611fdcc8 reorgnization done
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
256 %broadcast.splat16 = shufflevector <8 x i32> %broadcast.splatinsert15, <8 x i32> undef, <8 x i32> zeroinitializer
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parents: 150
diff changeset
257 br label %vector.body
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parents: 150
diff changeset
258
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Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
259 vector.body:
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Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
260 %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
252
1f2b6ac9f198 LLVM16-1
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 236
diff changeset
261 %t0 = getelementptr inbounds i32, ptr %arr, i64 %index
1f2b6ac9f198 LLVM16-1
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 236
diff changeset
262 %wide.load = load <8 x i32>, ptr %t0, align 4
173
0572611fdcc8 reorgnization done
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
263 %t2 = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> %wide.load, <8 x i32> %wide.load, <8 x i32> %broadcast.splat16)
252
1f2b6ac9f198 LLVM16-1
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 236
diff changeset
264 store <8 x i32> %t2, ptr %t0, align 4
173
0572611fdcc8 reorgnization done
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
265 %index.next = add i64 %index, 8
0572611fdcc8 reorgnization done
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
266 %t3 = icmp eq i64 %index.next, 65536
0572611fdcc8 reorgnization done
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
267 br i1 %t3, label %for.cond.cleanup, label %vector.body
0572611fdcc8 reorgnization done
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
268
0572611fdcc8 reorgnization done
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
269 for.cond.cleanup:
0572611fdcc8 reorgnization done
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
270 ret void
0572611fdcc8 reorgnization done
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
271 }
0572611fdcc8 reorgnization done
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
272
0572611fdcc8 reorgnization done
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
273 declare <8 x i32> @llvm.fshl.v8i32(<8 x i32>, <8 x i32>, <8 x i32>)