Mercurial > hg > CbC > CbC_llvm

comparison llvm/test/CodeGen/AMDGPU/sgpr-copy.ll @ 173:0572611fdcc8 llvm10 llvm12

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
reorgnization done
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Mon, 25 May 2020 11:55:54 +0900
parents 1d019706d866
children c4bab56944e8
comparison
equal deleted inserted replaced
172:9fbae9c8bf63 173:0572611fdcc8
209 ; This checks for a bug in the FixSGPRCopies pass where VReg96 209 ; This checks for a bug in the FixSGPRCopies pass where VReg96
210 ; registers were being identified as an SGPR regclass which was causing 210 ; registers were being identified as an SGPR regclass which was causing
211 ; an assertion failure. 211 ; an assertion failure.
212 212
213 ; CHECK-LABEL: {{^}}sample_v3: 213 ; CHECK-LABEL: {{^}}sample_v3:
214 ; CHECK: v_mov_b32_e32 v[[SAMPLE_LO:[0-9]+]], 11 214 ; CHECK: v_mov_b32_e32 v[[SAMPLE_LO:[0-9]+]], 5
215 ; CHECK: v_mov_b32_e32 v[[SAMPLE_HI:[0-9]+]], 13 215 ; CHECK: v_mov_b32_e32 v[[SAMPLE_HI:[0-9]+]], 7
216 ; CHECK: s_branch 216 ; CHECK: s_branch
217 217
218 ; CHECK-DAG: v_mov_b32_e32 v[[SAMPLE_LO:[0-9]+]], 5
219 ; CHECK-DAG: v_mov_b32_e32 v[[SAMPLE_HI:[0-9]+]], 7
220
221 ; CHECK: BB{{[0-9]+_[0-9]+}}: 218 ; CHECK: BB{{[0-9]+_[0-9]+}}:
219 ; CHECK-DAG: v_mov_b32_e32 v[[SAMPLE_LO:[0-9]+]], 11
220 ; CHECK-DAG: v_mov_b32_e32 v[[SAMPLE_HI:[0-9]+]], 13
221
222 ; CHECK: image_sample v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[SAMPLE_LO]]:[[SAMPLE_HI]]{{\]}} 222 ; CHECK: image_sample v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[SAMPLE_LO]]:[[SAMPLE_HI]]{{\]}}
223 ; CHECK: exp 223 ; CHECK: exp
224 ; CHECK: s_endpgm 224 ; CHECK: s_endpgm
225 define amdgpu_ps void @sample_v3([17 x <4 x i32>] addrspace(4)* inreg %arg, [32 x <4 x i32>] addrspace(4)* inreg %arg1, [16 x <8 x i32>] addrspace(4)* inreg %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 { 225 define amdgpu_ps void @sample_v3([17 x <4 x i32>] addrspace(4)* inreg %arg, [32 x <4 x i32>] addrspace(4)* inreg %arg1, [16 x <8 x i32>] addrspace(4)* inreg %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 {
226 entry: 226 entry: