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comparison llvm/test/TableGen/AsmPredicateCombining.td @ 173:0572611fdcc8 llvm10 llvm12

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reorgnization done
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Mon, 25 May 2020 11:55:54 +0900
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children c4bab56944e8
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172:9fbae9c8bf63 173:0572611fdcc8
1 // RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | \
2 // RUN: FileCheck --check-prefix=DISASS %s
3 // RUN: llvm-tblgen -gen-asm-matcher -I %p/../../include %s | \
4 // RUN: FileCheck --check-prefix=MATCHER %s
5 // RUN: llvm-tblgen -gen-asm-writer -I %p/../../include %s | \
6 // RUN: FileCheck --check-prefix=WRITER %s
7
8 // Check that combining conditions in AssemblerPredicate generates the correct
9 // output when using both the (all_of) AND operator, and the (any_of) OR
10 // operator.
11
12 include "llvm/Target/Target.td"
13
14 def archInstrInfo : InstrInfo { }
15 def archAsmWriter : AsmWriter {
16 int PassSubtarget = 1;
17 }
18
19 def arch : Target {
20 let InstructionSet = archInstrInfo;
21 let AssemblyWriters = [archAsmWriter];
22 }
23
24 let Namespace = "arch" in {
25 def R0 : Register<"r0">;
26 def R1 : Register<"r1">;
27 def R2 : Register<"r2">;
28 def R3 : Register<"r3">;
29 def R4 : Register<"r4">;
30 }
31 def Regs : RegisterClass<"Regs", [i32], 32, (add R0, R1, R2, R3, R4)>;
32
33 class TestInsn<int Opc, list<Predicate> Preds> : Instruction {
34 let Size = 2;
35 let OutOperandList = (outs);
36 let InOperandList = (ins Regs:$r);
37 field bits<16> Inst;
38 let Inst = Opc;
39 let AsmString = NAME # " $r";
40 field bits<16> SoftFail = 0;
41 let Predicates = Preds;
42 }
43
44
45 def AsmCond1 : SubtargetFeature<"cond1", "cond1", "true", "">;
46 def AsmCond2a: SubtargetFeature<"cond2a", "cond2a", "true", "">;
47 def AsmCond2b: SubtargetFeature<"cond2b", "cond2b", "true", "">;
48 def AsmCond3a: SubtargetFeature<"cond3a", "cond3a", "true", "">;
49 def AsmCond3b: SubtargetFeature<"cond3b", "cond3b", "true", "">;
50
51 def AsmPred1 : Predicate<"Pred1">, AssemblerPredicate<(all_of AsmCond1)>;
52 def AsmPred2 : Predicate<"Pred2">, AssemblerPredicate<(all_of AsmCond2a, AsmCond2b)>;
53 def AsmPred3 : Predicate<"Pred3">, AssemblerPredicate<(any_of AsmCond3a, AsmCond3b)>;
54 // MATCHER: if (FB[arch::AsmCond1])
55 // MATCHER-NEXT: Features.set(Feature_AsmPred1Bit);
56 // MATCHER-NEXT: if (FB[arch::AsmCond2a] && FB[arch::AsmCond2b])
57 // MATCHER-NEXT: Features.set(Feature_AsmPred2Bit);
58 // MATCHER-NEXT: if ((FB[arch::AsmCond3a] || FB[arch::AsmCond3b]))
59 // MATCHER-NEXT: Features.set(Feature_AsmPred3Bit);
60
61 def insn1 : TestInsn<1, [AsmPred1]>;
62 // DISASS: return (Bits[arch::AsmCond1]);
63
64 def insn2 : TestInsn<2, [AsmPred2]>;
65 // DISASS: return (Bits[arch::AsmCond2a] && Bits[arch::AsmCond2b])
66
67 def insn3 : TestInsn<3, [AsmPred3]>;
68 // DISASS: return ((Bits[arch::AsmCond3a] || Bits[arch::AsmCond3b]))
69
70 def insn4 : TestInsn<4, [AsmPred1, AsmPred2]>;
71 // DISASS: return (Bits[arch::AsmCond1] && Bits[arch::AsmCond2a] && Bits[arch::AsmCond2b])
72
73 def insn5 : TestInsn<5, [AsmPred1, AsmPred3]>;
74 // DISASS: return (Bits[arch::AsmCond1] && (Bits[arch::AsmCond3a] || Bits[arch::AsmCond3b]))
75
76 def insn6 : TestInsn<6, []>;
77 def : InstAlias<"alias1", (insn6 R0)> { let Predicates = [AsmPred1]; }
78 // WRITER: // (insn6 R0)
79 // WRITER-NEXT: {AliasPatternCond::K_Reg, arch::R0},
80 // WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond1},
81 def : InstAlias<"alias2", (insn6 R1)> { let Predicates = [AsmPred2]; }
82 // WRITER: // (insn6 R1)
83 // WRITER-NEXT: {AliasPatternCond::K_Reg, arch::R1},
84 // WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond2a},
85 // WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond2b},
86 def : InstAlias<"alias3", (insn6 R2)> { let Predicates = [AsmPred3]; }
87 // WRITER: // (insn6 R2)
88 // WRITER-NEXT: {AliasPatternCond::K_Reg, arch::R2},
89 // WRITER-NEXT: {AliasPatternCond::K_OrFeature, arch::AsmCond3a},
90 // WRITER-NEXT: {AliasPatternCond::K_OrFeature, arch::AsmCond3b},
91 // WRITER-NEXT: {AliasPatternCond::K_EndOrFeatures, 0},
92 def : InstAlias<"alias4", (insn6 R3)> { let Predicates = [AsmPred1, AsmPred2]; }
93 // WRITER: // (insn6 R3)
94 // WRITER-NEXT: {AliasPatternCond::K_Reg, arch::R3},
95 // WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond1},
96 // WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond2a},
97 // WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond2b},
98 def : InstAlias<"alias5", (insn6 R4)> { let Predicates = [AsmPred1, AsmPred3]; }
99 // WRITER: // (insn6 R4)
100 // WRITER-NEXT: {AliasPatternCond::K_Reg, arch::R4},
101 // WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond1},
102 // WRITER-NEXT: {AliasPatternCond::K_OrFeature, arch::AsmCond3a},
103 // WRITER-NEXT: {AliasPatternCond::K_OrFeature, arch::AsmCond3b},
104 // WRITER-NEXT: {AliasPatternCond::K_EndOrFeatures, 0},