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comparison llvm/test/TableGen/AsmPredicateCombiningRISCV.td @ 173:0572611fdcc8 llvm10 llvm12

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reorgnization done
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Mon, 25 May 2020 11:55:54 +0900
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children 2e18cbf3894f
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172:9fbae9c8bf63 173:0572611fdcc8
1 // RUN: llvm-tblgen -gen-compress-inst-emitter -I %p/../../include %s | \
2 // RUN: FileCheck --check-prefix=COMPRESS %s
3
4 // Check that combining conditions in AssemblerPredicate generates the correct
5 // output when using both the (all_of) AND operator, and the (any_of) OR
6 // operator in the RISC-V specific instruction compressor.
7
8 include "llvm/Target/Target.td"
9
10 def archInstrInfo : InstrInfo { }
11 def archAsmWriter : AsmWriter {
12 int PassSubtarget = 1;
13 }
14
15 def arch : Target {
16 let InstructionSet = archInstrInfo;
17 let AssemblyWriters = [archAsmWriter];
18 }
19
20 let Namespace = "arch" in {
21 def R0 : Register<"r0">;
22 }
23 def Regs : RegisterClass<"Regs", [i32], 32, (add R0)>;
24
25 class RVInst<int Opc, list<Predicate> Preds> : Instruction {
26 let Size = 4;
27 let OutOperandList = (outs);
28 let InOperandList = (ins Regs:$r);
29 field bits<32> Inst;
30 let Inst = Opc;
31 let AsmString = NAME # " $r";
32 field bits<32> SoftFail = 0;
33 let Predicates = Preds;
34 }
35 class RVInst16<int Opc, list<Predicate> Preds> : Instruction {
36 let Size = 2;
37 let OutOperandList = (outs);
38 let InOperandList = (ins Regs:$r);
39 field bits<16> Inst;
40 let Inst = Opc;
41 let AsmString = NAME # " $r";
42 field bits<16> SoftFail = 0;
43 let Predicates = Preds;
44 }
45
46 def AsmCond1 : SubtargetFeature<"cond1", "cond1", "true", "">;
47 def AsmCond2a: SubtargetFeature<"cond2a", "cond2a", "true", "">;
48 def AsmCond2b: SubtargetFeature<"cond2b", "cond2b", "true", "">;
49 def AsmCond3a: SubtargetFeature<"cond3a", "cond3a", "true", "">;
50 def AsmCond3b: SubtargetFeature<"cond3b", "cond3b", "true", "">;
51
52 def AsmPred1 : Predicate<"Pred1">, AssemblerPredicate<(all_of AsmCond1)>;
53 def AsmPred2 : Predicate<"Pred2">, AssemblerPredicate<(all_of AsmCond2a, AsmCond2b)>;
54 def AsmPred3 : Predicate<"Pred3">, AssemblerPredicate<(any_of AsmCond3a, AsmCond3b)>;
55
56 def BigInst : RVInst<1, [AsmPred1]>;
57
58 class CompressPat<dag input, dag output, list<Predicate> predicates> {
59 dag Input = input;
60 dag Output = output;
61 list<Predicate> Predicates = predicates;
62 }
63
64 // COMPRESS-LABEL: static bool compressInst
65 // COMPRESS: case arch::BigInst
66 def SmallInst1 : RVInst16<1, []>;
67 def : CompressPat<(BigInst Regs:$r), (SmallInst1 Regs:$r), [AsmPred1]>;
68 // COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] &&
69 // COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
70 // COMPRESS-NEXT: // SmallInst1 $r
71
72 def SmallInst2 : RVInst16<2, []>;
73 def : CompressPat<(BigInst Regs:$r), (SmallInst2 Regs:$r), [AsmPred2]>;
74 // COMPRESS: if (STI.getFeatureBits()[arch::AsmCond2a] &&
75 // COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2b] &&
76 // COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
77 // COMPRESS-NEXT: // SmallInst2 $r
78
79 def SmallInst3 : RVInst16<2, []>;
80 def : CompressPat<(BigInst Regs:$r), (SmallInst3 Regs:$r), [AsmPred3]>;
81 // COMPRESS: if ((STI.getFeatureBits()[arch::AsmCond3a] || STI.getFeatureBits()[arch::AsmCond3b]) &&
82 // COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
83 // COMPRESS-NEXT: // SmallInst3 $r
84
85 def SmallInst4 : RVInst16<2, []>;
86 def : CompressPat<(BigInst Regs:$r), (SmallInst4 Regs:$r), [AsmPred1, AsmPred2]>;
87 // COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] &&
88 // COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2a] &&
89 // COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2b] &&
90 // COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
91 // COMPRESS-NEXT: // SmallInst4 $r
92
93 def SmallInst5 : RVInst16<2, []>;
94 def : CompressPat<(BigInst Regs:$r), (SmallInst5 Regs:$r), [AsmPred1, AsmPred3]>;
95 // COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] &&
96 // COMPRESS-NEXT: (STI.getFeatureBits()[arch::AsmCond3a] || STI.getFeatureBits()[arch::AsmCond3b]) &&
97 // COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
98 // COMPRESS-NEXT: // SmallInst5 $r
99
100 // COMPRESS-LABEL: static bool uncompressInst