CbC/CbC_llvm: lib/CodeGen/CriticalAntiDepBreaker.cpp comparison

comparison lib/CodeGen/CriticalAntiDepBreaker.cpp @ 120:1172e4bd9c6f

update 4.0.0

author	mir3636
date	Fri, 25 Nov 2016 19:14:25 +0900
parents	afa8332a0e37
children	803732b1fca8

comparison

equal deleted inserted replaced

-:34baf5011add
+:1172e4bd9c6f
 }
 // Mark live-out callee-saved registers. In a return block this is
 // all callee-saved registers. In non-return this is any
 // callee-saved register that is not saved in the prolog.
-const MachineFrameInfo *MFI = MF.getFrameInfo();
+const MachineFrameInfo &MFI = MF.getFrameInfo();
-BitVector Pristine = MFI->getPristineRegs(MF);
+BitVector Pristine = MFI.getPristineRegs(MF);
 for (const MCPhysReg *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) {
 if (!IsReturnBlock && !Pristine.test(*I)) continue;
 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) {
 unsigned Reg = *AI;
 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
 void CriticalAntiDepBreaker::FinishBlock() {
 RegRefs.clear();
 KeepRegs.reset();
 }
-void CriticalAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count,
+void CriticalAntiDepBreaker::Observe(MachineInstr &MI, unsigned Count,
 unsigned InsertPosIndex) {
 // Kill instructions can define registers but are really nops, and there might
 // be a real definition earlier that needs to be paired with uses dominated by
 // this kill.
 // FIXME: It may be possible to remove the isKill() restriction once PR18663
 // has been properly fixed. There can be value in processing kills as seen in
 // the AggressiveAntiDepBreaker class.
-if (MI->isDebugValue() || MI->isKill())
+if (MI.isDebugValue() || MI.isKill())
 return;
 assert(Count < InsertPosIndex && "Instruction index out of expected range!");
 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
 if (KillIndices[Reg] != ~0u) {
 }
 }
 return Next;
 }
-void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr *MI) {
+void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr &MI) {
 // It's not safe to change register allocation for source operands of
 // instructions that have special allocation requirements. Also assume all
 // registers used in a call must not be changed (ABI).
 // FIXME: The issue with predicated instruction is more complex. We are being
 // conservative here because the kill markers cannot be trusted after
 //
 // The first R6 kill is not really a kill since it's killed by a predicated
 // instruction which may not be executed. The second R6 def may or may not
 // re-define R6 so it's not safe to change it since the last R6 use cannot be
 // changed.
-bool Special = MI->isCall() ||
+bool Special =
-MI->hasExtraSrcRegAllocReq() ||
+MI.isCall() || MI.hasExtraSrcRegAllocReq() || TII->isPredicated(MI);
-TII->isPredicated(MI);
 // Scan the register operands for this instruction and update
 // Classes and RegRefs.
-for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
-MachineOperand &MO = MI->getOperand(i);
+MachineOperand &MO = MI.getOperand(i);
 if (!MO.isReg()) continue;
 unsigned Reg = MO.getReg();
 if (Reg == 0) continue;
 const TargetRegisterClass *NewRC = nullptr;
-if (i < MI->getDesc().getNumOperands())
+if (i < MI.getDesc().getNumOperands())
-NewRC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
+NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF);
 // For now, only allow the register to be changed if its register
 // class is consistent across all uses.
 if (!Classes[Reg] && NewRC)
 Classes[Reg] = NewRC;
 // def register but not the second (see PR20020 for details).
 // FIXME: can this check be relaxed to account for undef uses
 // of a register? In the above 'xor' example, the uses of %eax are undef, so
 // earlier instructions could still replace %eax even though the 'xor'
 // itself can't be changed.
-if (MI->isRegTiedToUseOperand(i) &&
+if (MI.isRegTiedToUseOperand(i) &&
 Classes[Reg] == reinterpret_cast<TargetRegisterClass *>(-1)) {
 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
 SubRegs.isValid(); ++SubRegs) {
 KeepRegs.set(*SubRegs);
 }
 }
 }
 }
 }
-void CriticalAntiDepBreaker::ScanInstruction(MachineInstr *MI,
+void CriticalAntiDepBreaker::ScanInstruction(MachineInstr &MI, unsigned Count) {
-unsigned Count) {
 // Update liveness.
 // Proceeding upwards, registers that are defed but not used in this
 // instruction are now dead.
-assert(!MI->isKill() && "Attempting to scan a kill instruction");
+assert(!MI.isKill() && "Attempting to scan a kill instruction");
 if (!TII->isPredicated(MI)) {
 // Predicated defs are modeled as read + write, i.e. similar to two
 // address updates.
-for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
-MachineOperand &MO = MI->getOperand(i);
+MachineOperand &MO = MI.getOperand(i);
 if (MO.isRegMask())
 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
 if (MO.clobbersPhysReg(i)) {
 DefIndices[i] = Count;
 if (!MO.isReg()) continue;
 unsigned Reg = MO.getReg();
 if (Reg == 0) continue;
 if (!MO.isDef()) continue;
-// If we've already marked this reg as unchangeable, carry on.
-if (KeepRegs.test(Reg)) continue;
 // Ignore two-addr defs.
-if (MI->isRegTiedToUseOperand(i)) continue;
+if (MI.isRegTiedToUseOperand(i))
+continue;
+// If we've already marked this reg as unchangeable, don't remove
+// it or any of its subregs from KeepRegs.
+bool Keep = KeepRegs.test(Reg);
 // For the reg itself and all subregs: update the def to current;
 // reset the kill state, any restrictions, and references.
 for (MCSubRegIterator SRI(Reg, TRI, true); SRI.isValid(); ++SRI) {
 unsigned SubregReg = *SRI;
 DefIndices[SubregReg] = Count;
 KillIndices[SubregReg] = ~0u;
-KeepRegs.reset(SubregReg);
 Classes[SubregReg] = nullptr;
 RegRefs.erase(SubregReg);
+if (!Keep)
+KeepRegs.reset(SubregReg);
 }
 // Conservatively mark super-registers as unusable.
 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR)
 Classes[*SR] = reinterpret_cast<TargetRegisterClass *>(-1);
 }
 }
-for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
-MachineOperand &MO = MI->getOperand(i);
+MachineOperand &MO = MI.getOperand(i);
 if (!MO.isReg()) continue;
 unsigned Reg = MO.getReg();
 if (Reg == 0) continue;
 if (!MO.isUse()) continue;
 const TargetRegisterClass *NewRC = nullptr;
-if (i < MI->getDesc().getNumOperands())
+if (i < MI.getDesc().getNumOperands())
-NewRC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
+NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF);
 // For now, only allow the register to be changed if its register
 // class is consistent across all uses.
 if (!Classes[Reg] && NewRC)
 Classes[Reg] = NewRC;
 // instructions from the bottom up, tracking information about liveness
 // as we go to help determine which registers are available.
 unsigned Broken = 0;
 unsigned Count = InsertPosIndex - 1;
 for (MachineBasicBlock::iterator I = End, E = Begin; I != E; --Count) {
-MachineInstr *MI = --I;
+MachineInstr &MI = *--I;
 // Kill instructions can define registers but are really nops, and there
 // might be a real definition earlier that needs to be paired with uses
 // dominated by this kill.
 // FIXME: It may be possible to remove the isKill() restriction once PR18663
 // has been properly fixed. There can be value in processing kills as seen
 // in the AggressiveAntiDepBreaker class.
-if (MI->isDebugValue() || MI->isKill())
+if (MI.isDebugValue() || MI.isKill())
 continue;
 // Check if this instruction has a dependence on the critical path that
 // is an anti-dependence that we may be able to break. If it is, set
 // AntiDepReg to the non-zero register associated with the anti-dependence.
 // TODO: Instructions with multiple defs could have multiple
 // anti-dependencies. The current code here only knows how to break one
 // edge per instruction. Note that we'd have to be able to break all of
 // the anti-dependencies in an instruction in order to be effective.
 unsigned AntiDepReg = 0;
-if (MI == CriticalPathMI) {
+if (&MI == CriticalPathMI) {
 if (const SDep *Edge = CriticalPathStep(CriticalPathSU)) {
 const SUnit *NextSU = Edge->getSUnit();
 // Only consider anti-dependence edges.
 if (Edge->getKind() == SDep::Anti) {
 SmallVector<unsigned, 2> ForbidRegs;
 // If MI's defs have a special allocation requirement, don't allow
 // any def registers to be changed. Also assume all registers
 // defined in a call must not be changed (ABI).
-if (MI->isCall() || MI->hasExtraDefRegAllocReq() || TII->isPredicated(MI))
+if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI))
 // If this instruction's defs have special allocation requirement, don't
 // break this anti-dependency.
 AntiDepReg = 0;
 else if (AntiDepReg) {
 // If this instruction has a use of AntiDepReg, breaking it
 // is invalid.  If the instruction defines other registers,
 // save a list of them so that we don't pick a new register
 // that overlaps any of them.
-for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
-MachineOperand &MO = MI->getOperand(i);
+MachineOperand &MO = MI.getOperand(i);
 if (!MO.isReg()) continue;
 unsigned Reg = MO.getReg();
 if (Reg == 0) continue;
 if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) {
 AntiDepReg = 0;
 const SUnit *SU = MISUnitMap[Q->second->getParent()];
 if (!SU) continue;
 for (DbgValueVector::iterator DVI = DbgValues.begin(),
 DVE = DbgValues.end(); DVI != DVE; ++DVI)
 if (DVI->second == Q->second->getParent())
-UpdateDbgValue(DVI->first, AntiDepReg, NewReg);
+UpdateDbgValue(*DVI->first, AntiDepReg, NewReg);
 }
 // We just went back in time and modified history; the
 // liveness information for the anti-dependence reg is now
 // inconsistent. Set the state as if it were dead.

Mercurial > hg > CbC > CbC_llvm

comparison lib/CodeGen/CriticalAntiDepBreaker.cpp @ 120:1172e4bd9c6f