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comparison lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents 7d135dc70f03
children 803732b1fca8
comparison
equal deleted inserted replaced
101:34baf5011add 120:1172e4bd9c6f
334 assert(Interferences.empty() && LRegsMap.empty() && "stale Interferences"); 334 assert(Interferences.empty() && LRegsMap.empty() && "stale Interferences");
335 335
336 // Build the scheduling graph. 336 // Build the scheduling graph.
337 BuildSchedGraph(nullptr); 337 BuildSchedGraph(nullptr);
338 338
339 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su) 339 DEBUG(for (SUnit &SU : SUnits)
340 SUnits[su].dumpAll(this)); 340 SU.dumpAll(this));
341 Topo.InitDAGTopologicalSorting(); 341 Topo.InitDAGTopologicalSorting();
342 342
343 AvailableQueue->initNodes(SUnits); 343 AvailableQueue->initNodes(SUnits);
344 344
345 HazardRec->Reset(); 345 HazardRec->Reset();
1025 SmallVector<SDep, 4> ChainPreds; 1025 SmallVector<SDep, 4> ChainPreds;
1026 SmallVector<SDep, 4> ChainSuccs; 1026 SmallVector<SDep, 4> ChainSuccs;
1027 SmallVector<SDep, 4> LoadPreds; 1027 SmallVector<SDep, 4> LoadPreds;
1028 SmallVector<SDep, 4> NodePreds; 1028 SmallVector<SDep, 4> NodePreds;
1029 SmallVector<SDep, 4> NodeSuccs; 1029 SmallVector<SDep, 4> NodeSuccs;
1030 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 1030 for (SDep &Pred : SU->Preds) {
1031 I != E; ++I) { 1031 if (Pred.isCtrl())
1032 if (I->isCtrl()) 1032 ChainPreds.push_back(Pred);
1033 ChainPreds.push_back(*I); 1033 else if (isOperandOf(Pred.getSUnit(), LoadNode))
1034 else if (isOperandOf(I->getSUnit(), LoadNode)) 1034 LoadPreds.push_back(Pred);
1035 LoadPreds.push_back(*I);
1036 else 1035 else
1037 NodePreds.push_back(*I); 1036 NodePreds.push_back(Pred);
1038 } 1037 }
1039 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 1038 for (SDep &Succ : SU->Succs) {
1040 I != E; ++I) { 1039 if (Succ.isCtrl())
1041 if (I->isCtrl()) 1040 ChainSuccs.push_back(Succ);
1042 ChainSuccs.push_back(*I);
1043 else 1041 else
1044 NodeSuccs.push_back(*I); 1042 NodeSuccs.push_back(Succ);
1045 } 1043 }
1046 1044
1047 // Now assign edges to the newly-created nodes. 1045 // Now assign edges to the newly-created nodes.
1048 for (unsigned i = 0, e = ChainPreds.size(); i != e; ++i) { 1046 for (const SDep &Pred : ChainPreds) {
1049 const SDep &Pred = ChainPreds[i];
1050 RemovePred(SU, Pred); 1047 RemovePred(SU, Pred);
1051 if (isNewLoad) 1048 if (isNewLoad)
1052 AddPred(LoadSU, Pred); 1049 AddPred(LoadSU, Pred);
1053 } 1050 }
1054 for (unsigned i = 0, e = LoadPreds.size(); i != e; ++i) { 1051 for (const SDep &Pred : LoadPreds) {
1055 const SDep &Pred = LoadPreds[i];
1056 RemovePred(SU, Pred); 1052 RemovePred(SU, Pred);
1057 if (isNewLoad) 1053 if (isNewLoad)
1058 AddPred(LoadSU, Pred); 1054 AddPred(LoadSU, Pred);
1059 } 1055 }
1060 for (unsigned i = 0, e = NodePreds.size(); i != e; ++i) { 1056 for (const SDep &Pred : NodePreds) {
1061 const SDep &Pred = NodePreds[i];
1062 RemovePred(SU, Pred); 1057 RemovePred(SU, Pred);
1063 AddPred(NewSU, Pred); 1058 AddPred(NewSU, Pred);
1064 } 1059 }
1065 for (unsigned i = 0, e = NodeSuccs.size(); i != e; ++i) { 1060 for (SDep D : NodeSuccs) {
1066 SDep D = NodeSuccs[i];
1067 SUnit *SuccDep = D.getSUnit(); 1061 SUnit *SuccDep = D.getSUnit();
1068 D.setSUnit(SU); 1062 D.setSUnit(SU);
1069 RemovePred(SuccDep, D); 1063 RemovePred(SuccDep, D);
1070 D.setSUnit(NewSU); 1064 D.setSUnit(NewSU);
1071 AddPred(SuccDep, D); 1065 AddPred(SuccDep, D);
1072 // Balance register pressure. 1066 // Balance register pressure.
1073 if (AvailableQueue->tracksRegPressure() && SuccDep->isScheduled 1067 if (AvailableQueue->tracksRegPressure() && SuccDep->isScheduled
1074 && !D.isCtrl() && NewSU->NumRegDefsLeft > 0) 1068 && !D.isCtrl() && NewSU->NumRegDefsLeft > 0)
1075 --NewSU->NumRegDefsLeft; 1069 --NewSU->NumRegDefsLeft;
1076 } 1070 }
1077 for (unsigned i = 0, e = ChainSuccs.size(); i != e; ++i) { 1071 for (SDep D : ChainSuccs) {
1078 SDep D = ChainSuccs[i];
1079 SUnit *SuccDep = D.getSUnit(); 1072 SUnit *SuccDep = D.getSUnit();
1080 D.setSUnit(SU); 1073 D.setSUnit(SU);
1081 RemovePred(SuccDep, D); 1074 RemovePred(SuccDep, D);
1082 if (isNewLoad) { 1075 if (isNewLoad) {
1083 D.setSUnit(LoadSU); 1076 D.setSUnit(LoadSU);
1106 1099
1107 DEBUG(dbgs() << " Duplicating SU #" << SU->NodeNum << "\n"); 1100 DEBUG(dbgs() << " Duplicating SU #" << SU->NodeNum << "\n");
1108 NewSU = CreateClone(SU); 1101 NewSU = CreateClone(SU);
1109 1102
1110 // New SUnit has the exact same predecessors. 1103 // New SUnit has the exact same predecessors.
1111 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 1104 for (SDep &Pred : SU->Preds)
1112 I != E; ++I) 1105 if (!Pred.isArtificial())
1113 if (!I->isArtificial()) 1106 AddPred(NewSU, Pred);
1114 AddPred(NewSU, *I);
1115 1107
1116 // Only copy scheduled successors. Cut them from old node's successor 1108 // Only copy scheduled successors. Cut them from old node's successor
1117 // list and move them over. 1109 // list and move them over.
1118 SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps; 1110 SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps;
1119 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 1111 for (SDep &Succ : SU->Succs) {
1120 I != E; ++I) { 1112 if (Succ.isArtificial())
1121 if (I->isArtificial())
1122 continue; 1113 continue;
1123 SUnit *SuccSU = I->getSUnit(); 1114 SUnit *SuccSU = Succ.getSUnit();
1124 if (SuccSU->isScheduled) { 1115 if (SuccSU->isScheduled) {
1125 SDep D = *I; 1116 SDep D = Succ;
1126 D.setSUnit(NewSU); 1117 D.setSUnit(NewSU);
1127 AddPred(SuccSU, D); 1118 AddPred(SuccSU, D);
1128 D.setSUnit(SU); 1119 D.setSUnit(SU);
1129 DelDeps.push_back(std::make_pair(SuccSU, D)); 1120 DelDeps.push_back(std::make_pair(SuccSU, D));
1130 } 1121 }
1131 } 1122 }
1132 for (unsigned i = 0, e = DelDeps.size(); i != e; ++i) 1123 for (auto &DelDep : DelDeps)
1133 RemovePred(DelDeps[i].first, DelDeps[i].second); 1124 RemovePred(DelDep.first, DelDep.second);
1134 1125
1135 AvailableQueue->updateNode(SU); 1126 AvailableQueue->updateNode(SU);
1136 AvailableQueue->addNode(NewSU); 1127 AvailableQueue->addNode(NewSU);
1137 1128
1138 ++NumDups; 1129 ++NumDups;
1154 CopyToSU->CopyDstRC = SrcRC; 1145 CopyToSU->CopyDstRC = SrcRC;
1155 1146
1156 // Only copy scheduled successors. Cut them from old node's successor 1147 // Only copy scheduled successors. Cut them from old node's successor
1157 // list and move them over. 1148 // list and move them over.
1158 SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps; 1149 SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps;
1159 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 1150 for (SDep &Succ : SU->Succs) {
1160 I != E; ++I) { 1151 if (Succ.isArtificial())
1161 if (I->isArtificial())
1162 continue; 1152 continue;
1163 SUnit *SuccSU = I->getSUnit(); 1153 SUnit *SuccSU = Succ.getSUnit();
1164 if (SuccSU->isScheduled) { 1154 if (SuccSU->isScheduled) {
1165 SDep D = *I; 1155 SDep D = Succ;
1166 D.setSUnit(CopyToSU); 1156 D.setSUnit(CopyToSU);
1167 AddPred(SuccSU, D); 1157 AddPred(SuccSU, D);
1168 DelDeps.push_back(std::make_pair(SuccSU, *I)); 1158 DelDeps.push_back(std::make_pair(SuccSU, Succ));
1169 } 1159 }
1170 else { 1160 else {
1171 // Avoid scheduling the def-side copy before other successors. Otherwise 1161 // Avoid scheduling the def-side copy before other successors. Otherwise
1172 // we could introduce another physreg interference on the copy and 1162 // we could introduce another physreg interference on the copy and
1173 // continue inserting copies indefinitely. 1163 // continue inserting copies indefinitely.
1174 AddPred(SuccSU, SDep(CopyFromSU, SDep::Artificial)); 1164 AddPred(SuccSU, SDep(CopyFromSU, SDep::Artificial));
1175 } 1165 }
1176 } 1166 }
1177 for (unsigned i = 0, e = DelDeps.size(); i != e; ++i) 1167 for (auto &DelDep : DelDeps)
1178 RemovePred(DelDeps[i].first, DelDeps[i].second); 1168 RemovePred(DelDep.first, DelDep.second);
1179 1169
1180 SDep FromDep(SU, SDep::Data, Reg); 1170 SDep FromDep(SU, SDep::Data, Reg);
1181 FromDep.setLatency(SU->Latency); 1171 FromDep.setLatency(SU->Latency);
1182 AddPred(CopyFromSU, FromDep); 1172 AddPred(CopyFromSU, FromDep);
1183 SDep ToDep(CopyFromSU, SDep::Data, 0); 1173 SDep ToDep(CopyFromSU, SDep::Data, 0);
1347 for (unsigned i = Interferences.size(); i > 0; --i) { 1337 for (unsigned i = Interferences.size(); i > 0; --i) {
1348 SUnit *SU = Interferences[i-1]; 1338 SUnit *SU = Interferences[i-1];
1349 LRegsMapT::iterator LRegsPos = LRegsMap.find(SU); 1339 LRegsMapT::iterator LRegsPos = LRegsMap.find(SU);
1350 if (Reg) { 1340 if (Reg) {
1351 SmallVectorImpl<unsigned> &LRegs = LRegsPos->second; 1341 SmallVectorImpl<unsigned> &LRegs = LRegsPos->second;
1352 if (std::find(LRegs.begin(), LRegs.end(), Reg) == LRegs.end()) 1342 if (!is_contained(LRegs, Reg))
1353 continue; 1343 continue;
1354 } 1344 }
1355 SU->isPending = false; 1345 SU->isPending = false;
1356 // The interfering node may no longer be available due to backtracking. 1346 // The interfering node may no longer be available due to backtracking.
1357 // Furthermore, it may have been made available again, in which case it is 1347 // Furthermore, it may have been made available again, in which case it is
1398 return CurSU; 1388 return CurSU;
1399 1389
1400 // All candidates are delayed due to live physical reg dependencies. 1390 // All candidates are delayed due to live physical reg dependencies.
1401 // Try backtracking, code duplication, or inserting cross class copies 1391 // Try backtracking, code duplication, or inserting cross class copies
1402 // to resolve it. 1392 // to resolve it.
1403 for (unsigned i = 0, e = Interferences.size(); i != e; ++i) { 1393 for (SUnit *TrySU : Interferences) {
1404 SUnit *TrySU = Interferences[i];
1405 SmallVectorImpl<unsigned> &LRegs = LRegsMap[TrySU]; 1394 SmallVectorImpl<unsigned> &LRegs = LRegsMap[TrySU];
1406 1395
1407 // Try unscheduling up to the point where it's safe to schedule 1396 // Try unscheduling up to the point where it's safe to schedule
1408 // this node. 1397 // this node.
1409 SUnit *BtSU = nullptr; 1398 SUnit *BtSU = nullptr;
1410 unsigned LiveCycle = UINT_MAX; 1399 unsigned LiveCycle = UINT_MAX;
1411 for (unsigned j = 0, ee = LRegs.size(); j != ee; ++j) { 1400 for (unsigned Reg : LRegs) {
1412 unsigned Reg = LRegs[j];
1413 if (LiveRegGens[Reg]->getHeight() < LiveCycle) { 1401 if (LiveRegGens[Reg]->getHeight() < LiveCycle) {
1414 BtSU = LiveRegGens[Reg]; 1402 BtSU = LiveRegGens[Reg];
1415 LiveCycle = BtSU->getHeight(); 1403 LiveCycle = BtSU->getHeight();
1416 } 1404 }
1417 } 1405 }
1714 } 1702 }
1715 1703
1716 void remove(SUnit *SU) override { 1704 void remove(SUnit *SU) override {
1717 assert(!Queue.empty() && "Queue is empty!"); 1705 assert(!Queue.empty() && "Queue is empty!");
1718 assert(SU->NodeQueueId != 0 && "Not in queue!"); 1706 assert(SU->NodeQueueId != 0 && "Not in queue!");
1719 std::vector<SUnit *>::iterator I = std::find(Queue.begin(), Queue.end(), 1707 std::vector<SUnit *>::iterator I = find(Queue, SU);
1720 SU);
1721 if (I != std::prev(Queue.end())) 1708 if (I != std::prev(Queue.end()))
1722 std::swap(*I, Queue.back()); 1709 std::swap(*I, Queue.back());
1723 Queue.pop_back(); 1710 Queue.pop_back();
1724 SU->NodeQueueId = 0; 1711 SU->NodeQueueId = 0;
1725 } 1712 }
1852 unsigned &SethiUllmanNumber = SUNumbers[SU->NodeNum]; 1839 unsigned &SethiUllmanNumber = SUNumbers[SU->NodeNum];
1853 if (SethiUllmanNumber != 0) 1840 if (SethiUllmanNumber != 0)
1854 return SethiUllmanNumber; 1841 return SethiUllmanNumber;
1855 1842
1856 unsigned Extra = 0; 1843 unsigned Extra = 0;
1857 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 1844 for (const SDep &Pred : SU->Preds) {
1858 I != E; ++I) { 1845 if (Pred.isCtrl()) continue; // ignore chain preds
1859 if (I->isCtrl()) continue; // ignore chain preds 1846 SUnit *PredSU = Pred.getSUnit();
1860 SUnit *PredSU = I->getSUnit();
1861 unsigned PredSethiUllman = CalcNodeSethiUllmanNumber(PredSU, SUNumbers); 1847 unsigned PredSethiUllman = CalcNodeSethiUllmanNumber(PredSU, SUNumbers);
1862 if (PredSethiUllman > SethiUllmanNumber) { 1848 if (PredSethiUllman > SethiUllmanNumber) {
1863 SethiUllmanNumber = PredSethiUllman; 1849 SethiUllmanNumber = PredSethiUllman;
1864 Extra = 0; 1850 Extra = 0;
1865 } else if (PredSethiUllman == SethiUllmanNumber) 1851 } else if (PredSethiUllman == SethiUllmanNumber)
1877 /// CalculateSethiUllmanNumbers - Calculate Sethi-Ullman numbers of all 1863 /// CalculateSethiUllmanNumbers - Calculate Sethi-Ullman numbers of all
1878 /// scheduling units. 1864 /// scheduling units.
1879 void RegReductionPQBase::CalculateSethiUllmanNumbers() { 1865 void RegReductionPQBase::CalculateSethiUllmanNumbers() {
1880 SethiUllmanNumbers.assign(SUnits->size(), 0); 1866 SethiUllmanNumbers.assign(SUnits->size(), 0);
1881 1867
1882 for (unsigned i = 0, e = SUnits->size(); i != e; ++i) 1868 for (const SUnit &SU : *SUnits)
1883 CalcNodeSethiUllmanNumber(&(*SUnits)[i], SethiUllmanNumbers); 1869 CalcNodeSethiUllmanNumber(&SU, SethiUllmanNumbers);
1884 } 1870 }
1885 1871
1886 void RegReductionPQBase::addNode(const SUnit *SU) { 1872 void RegReductionPQBase::addNode(const SUnit *SU) {
1887 unsigned SUSize = SethiUllmanNumbers.size(); 1873 unsigned SUSize = SethiUllmanNumbers.size();
1888 if (SUnits->size() > SUSize) 1874 if (SUnits->size() > SUSize)
1954 1940
1955 bool RegReductionPQBase::HighRegPressure(const SUnit *SU) const { 1941 bool RegReductionPQBase::HighRegPressure(const SUnit *SU) const {
1956 if (!TLI) 1942 if (!TLI)
1957 return false; 1943 return false;
1958 1944
1959 for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end(); 1945 for (const SDep &Pred : SU->Preds) {
1960 I != E; ++I) { 1946 if (Pred.isCtrl())
1961 if (I->isCtrl())
1962 continue; 1947 continue;
1963 SUnit *PredSU = I->getSUnit(); 1948 SUnit *PredSU = Pred.getSUnit();
1964 // NumRegDefsLeft is zero when enough uses of this node have been scheduled 1949 // NumRegDefsLeft is zero when enough uses of this node have been scheduled
1965 // to cover the number of registers defined (they are all live). 1950 // to cover the number of registers defined (they are all live).
1966 if (PredSU->NumRegDefsLeft == 0) { 1951 if (PredSU->NumRegDefsLeft == 0) {
1967 continue; 1952 continue;
1968 } 1953 }
2004 // FIXME: This encompasses the logic in HighRegPressure and MayReduceRegPressure 1989 // FIXME: This encompasses the logic in HighRegPressure and MayReduceRegPressure
2005 // so could probably be factored. 1990 // so could probably be factored.
2006 int RegReductionPQBase::RegPressureDiff(SUnit *SU, unsigned &LiveUses) const { 1991 int RegReductionPQBase::RegPressureDiff(SUnit *SU, unsigned &LiveUses) const {
2007 LiveUses = 0; 1992 LiveUses = 0;
2008 int PDiff = 0; 1993 int PDiff = 0;
2009 for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end(); 1994 for (const SDep &Pred : SU->Preds) {
2010 I != E; ++I) { 1995 if (Pred.isCtrl())
2011 if (I->isCtrl())
2012 continue; 1996 continue;
2013 SUnit *PredSU = I->getSUnit(); 1997 SUnit *PredSU = Pred.getSUnit();
2014 // NumRegDefsLeft is zero when enough uses of this node have been scheduled 1998 // NumRegDefsLeft is zero when enough uses of this node have been scheduled
2015 // to cover the number of registers defined (they are all live). 1999 // to cover the number of registers defined (they are all live).
2016 if (PredSU->NumRegDefsLeft == 0) { 2000 if (PredSU->NumRegDefsLeft == 0) {
2017 if (PredSU->getNode()->isMachineOpcode()) 2001 if (PredSU->getNode()->isMachineOpcode())
2018 ++LiveUses; 2002 ++LiveUses;
2048 return; 2032 return;
2049 2033
2050 if (!SU->getNode()) 2034 if (!SU->getNode())
2051 return; 2035 return;
2052 2036
2053 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 2037 for (const SDep &Pred : SU->Preds) {
2054 I != E; ++I) { 2038 if (Pred.isCtrl())
2055 if (I->isCtrl())
2056 continue; 2039 continue;
2057 SUnit *PredSU = I->getSUnit(); 2040 SUnit *PredSU = Pred.getSUnit();
2058 // NumRegDefsLeft is zero when enough uses of this node have been scheduled 2041 // NumRegDefsLeft is zero when enough uses of this node have been scheduled
2059 // to cover the number of registers defined (they are all live). 2042 // to cover the number of registers defined (they are all live).
2060 if (PredSU->NumRegDefsLeft == 0) { 2043 if (PredSU->NumRegDefsLeft == 0) {
2061 continue; 2044 continue;
2062 } 2045 }
2130 Opc == TargetOpcode::REG_SEQUENCE || 2113 Opc == TargetOpcode::REG_SEQUENCE ||
2131 Opc == TargetOpcode::IMPLICIT_DEF) 2114 Opc == TargetOpcode::IMPLICIT_DEF)
2132 return; 2115 return;
2133 } 2116 }
2134 2117
2135 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 2118 for (const SDep &Pred : SU->Preds) {
2136 I != E; ++I) { 2119 if (Pred.isCtrl())
2137 if (I->isCtrl())
2138 continue; 2120 continue;
2139 SUnit *PredSU = I->getSUnit(); 2121 SUnit *PredSU = Pred.getSUnit();
2140 // NumSuccsLeft counts all deps. Don't compare it with NumSuccs which only 2122 // NumSuccsLeft counts all deps. Don't compare it with NumSuccs which only
2141 // counts data deps. 2123 // counts data deps.
2142 if (PredSU->NumSuccsLeft != PredSU->Succs.size()) 2124 if (PredSU->NumSuccsLeft != PredSU->Succs.size())
2143 continue; 2125 continue;
2144 const SDNode *PN = PredSU->getNode(); 2126 const SDNode *PN = PredSU->getNode();
2199 2181
2200 /// closestSucc - Returns the scheduled cycle of the successor which is 2182 /// closestSucc - Returns the scheduled cycle of the successor which is
2201 /// closest to the current cycle. 2183 /// closest to the current cycle.
2202 static unsigned closestSucc(const SUnit *SU) { 2184 static unsigned closestSucc(const SUnit *SU) {
2203 unsigned MaxHeight = 0; 2185 unsigned MaxHeight = 0;
2204 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 2186 for (const SDep &Succ : SU->Succs) {
2205 I != E; ++I) { 2187 if (Succ.isCtrl()) continue; // ignore chain succs
2206 if (I->isCtrl()) continue; // ignore chain succs 2188 unsigned Height = Succ.getSUnit()->getHeight();
2207 unsigned Height = I->getSUnit()->getHeight();
2208 // If there are bunch of CopyToRegs stacked up, they should be considered 2189 // If there are bunch of CopyToRegs stacked up, they should be considered
2209 // to be at the same position. 2190 // to be at the same position.
2210 if (I->getSUnit()->getNode() && 2191 if (Succ.getSUnit()->getNode() &&
2211 I->getSUnit()->getNode()->getOpcode() == ISD::CopyToReg) 2192 Succ.getSUnit()->getNode()->getOpcode() == ISD::CopyToReg)
2212 Height = closestSucc(I->getSUnit())+1; 2193 Height = closestSucc(Succ.getSUnit())+1;
2213 if (Height > MaxHeight) 2194 if (Height > MaxHeight)
2214 MaxHeight = Height; 2195 MaxHeight = Height;
2215 } 2196 }
2216 return MaxHeight; 2197 return MaxHeight;
2217 } 2198 }
2218 2199
2219 /// calcMaxScratches - Returns an cost estimate of the worse case requirement 2200 /// calcMaxScratches - Returns an cost estimate of the worse case requirement
2220 /// for scratch registers, i.e. number of data dependencies. 2201 /// for scratch registers, i.e. number of data dependencies.
2221 static unsigned calcMaxScratches(const SUnit *SU) { 2202 static unsigned calcMaxScratches(const SUnit *SU) {
2222 unsigned Scratches = 0; 2203 unsigned Scratches = 0;
2223 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 2204 for (const SDep &Pred : SU->Preds) {
2224 I != E; ++I) { 2205 if (Pred.isCtrl()) continue; // ignore chain preds
2225 if (I->isCtrl()) continue; // ignore chain preds
2226 Scratches++; 2206 Scratches++;
2227 } 2207 }
2228 return Scratches; 2208 return Scratches;
2229 } 2209 }
2230 2210
2231 /// hasOnlyLiveInOpers - Return true if SU has only value predecessors that are 2211 /// hasOnlyLiveInOpers - Return true if SU has only value predecessors that are
2232 /// CopyFromReg from a virtual register. 2212 /// CopyFromReg from a virtual register.
2233 static bool hasOnlyLiveInOpers(const SUnit *SU) { 2213 static bool hasOnlyLiveInOpers(const SUnit *SU) {
2234 bool RetVal = false; 2214 bool RetVal = false;
2235 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 2215 for (const SDep &Pred : SU->Preds) {
2236 I != E; ++I) { 2216 if (Pred.isCtrl()) continue;
2237 if (I->isCtrl()) continue; 2217 const SUnit *PredSU = Pred.getSUnit();
2238 const SUnit *PredSU = I->getSUnit();
2239 if (PredSU->getNode() && 2218 if (PredSU->getNode() &&
2240 PredSU->getNode()->getOpcode() == ISD::CopyFromReg) { 2219 PredSU->getNode()->getOpcode() == ISD::CopyFromReg) {
2241 unsigned Reg = 2220 unsigned Reg =
2242 cast<RegisterSDNode>(PredSU->getNode()->getOperand(1))->getReg(); 2221 cast<RegisterSDNode>(PredSU->getNode()->getOperand(1))->getReg();
2243 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 2222 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
2253 /// hasOnlyLiveOutUses - Return true if SU has only value successors that are 2232 /// hasOnlyLiveOutUses - Return true if SU has only value successors that are
2254 /// CopyToReg to a virtual register. This SU def is probably a liveout and 2233 /// CopyToReg to a virtual register. This SU def is probably a liveout and
2255 /// it has no other use. It should be scheduled closer to the terminator. 2234 /// it has no other use. It should be scheduled closer to the terminator.
2256 static bool hasOnlyLiveOutUses(const SUnit *SU) { 2235 static bool hasOnlyLiveOutUses(const SUnit *SU) {
2257 bool RetVal = false; 2236 bool RetVal = false;
2258 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 2237 for (const SDep &Succ : SU->Succs) {
2259 I != E; ++I) { 2238 if (Succ.isCtrl()) continue;
2260 if (I->isCtrl()) continue; 2239 const SUnit *SuccSU = Succ.getSUnit();
2261 const SUnit *SuccSU = I->getSUnit();
2262 if (SuccSU->getNode() && SuccSU->getNode()->getOpcode() == ISD::CopyToReg) { 2240 if (SuccSU->getNode() && SuccSU->getNode()->getOpcode() == ISD::CopyToReg) {
2263 unsigned Reg = 2241 unsigned Reg =
2264 cast<RegisterSDNode>(SuccSU->getNode()->getOperand(1))->getReg(); 2242 cast<RegisterSDNode>(SuccSU->getNode()->getOperand(1))->getReg();
2265 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 2243 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
2266 RetVal = true; 2244 RetVal = true;
2291 2269
2292 DEBUG(dbgs() << "VRegCycle: SU(" << SU->NodeNum << ")\n"); 2270 DEBUG(dbgs() << "VRegCycle: SU(" << SU->NodeNum << ")\n");
2293 2271
2294 SU->isVRegCycle = true; 2272 SU->isVRegCycle = true;
2295 2273
2296 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 2274 for (const SDep &Pred : SU->Preds) {
2297 I != E; ++I) { 2275 if (Pred.isCtrl()) continue;
2298 if (I->isCtrl()) continue; 2276 Pred.getSUnit()->isVRegCycle = true;
2299 I->getSUnit()->isVRegCycle = true;
2300 } 2277 }
2301 } 2278 }
2302 2279
2303 // After scheduling the definition of a VRegCycle, clear the isVRegCycle flag of 2280 // After scheduling the definition of a VRegCycle, clear the isVRegCycle flag of
2304 // CopyFromReg operands. We should no longer penalize other uses of this VReg. 2281 // CopyFromReg operands. We should no longer penalize other uses of this VReg.
2305 static void resetVRegCycle(SUnit *SU) { 2282 static void resetVRegCycle(SUnit *SU) {
2306 if (!SU->isVRegCycle) 2283 if (!SU->isVRegCycle)
2307 return; 2284 return;
2308 2285
2309 for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end(); 2286 for (const SDep &Pred : SU->Preds) {
2310 I != E; ++I) { 2287 if (Pred.isCtrl()) continue; // ignore chain preds
2311 if (I->isCtrl()) continue; // ignore chain preds 2288 SUnit *PredSU = Pred.getSUnit();
2312 SUnit *PredSU = I->getSUnit();
2313 if (PredSU->isVRegCycle) { 2289 if (PredSU->isVRegCycle) {
2314 assert(PredSU->getNode()->getOpcode() == ISD::CopyFromReg && 2290 assert(PredSU->getNode()->getOpcode() == ISD::CopyFromReg &&
2315 "VRegCycle def must be CopyFromReg"); 2291 "VRegCycle def must be CopyFromReg");
2316 I->getSUnit()->isVRegCycle = 0; 2292 Pred.getSUnit()->isVRegCycle = false;
2317 } 2293 }
2318 } 2294 }
2319 } 2295 }
2320 2296
2321 // Return true if this SUnit uses a CopyFromReg node marked as a VRegCycle. This 2297 // Return true if this SUnit uses a CopyFromReg node marked as a VRegCycle. This
2323 static bool hasVRegCycleUse(const SUnit *SU) { 2299 static bool hasVRegCycleUse(const SUnit *SU) {
2324 // If this SU also defines the VReg, don't hoist it as a "use". 2300 // If this SU also defines the VReg, don't hoist it as a "use".
2325 if (SU->isVRegCycle) 2301 if (SU->isVRegCycle)
2326 return false; 2302 return false;
2327 2303
2328 for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end(); 2304 for (const SDep &Pred : SU->Preds) {
2329 I != E; ++I) { 2305 if (Pred.isCtrl()) continue; // ignore chain preds
2330 if (I->isCtrl()) continue; // ignore chain preds 2306 if (Pred.getSUnit()->isVRegCycle &&
2331 if (I->getSUnit()->isVRegCycle && 2307 Pred.getSUnit()->getNode()->getOpcode() == ISD::CopyFromReg) {
2332 I->getSUnit()->getNode()->getOpcode() == ISD::CopyFromReg) {
2333 DEBUG(dbgs() << " VReg cycle use: SU (" << SU->NodeNum << ")\n"); 2308 DEBUG(dbgs() << " VReg cycle use: SU (" << SU->NodeNum << ")\n");
2334 return true; 2309 return true;
2335 } 2310 }
2336 } 2311 }
2337 return false; 2312 return false;
2682 PrescheduleNodesWithMultipleUses(); 2657 PrescheduleNodesWithMultipleUses();
2683 // Calculate node priorities. 2658 // Calculate node priorities.
2684 CalculateSethiUllmanNumbers(); 2659 CalculateSethiUllmanNumbers();
2685 2660
2686 // For single block loops, mark nodes that look like canonical IV increments. 2661 // For single block loops, mark nodes that look like canonical IV increments.
2687 if (scheduleDAG->BB->isSuccessor(scheduleDAG->BB)) { 2662 if (scheduleDAG->BB->isSuccessor(scheduleDAG->BB))
2688 for (unsigned i = 0, e = sunits.size(); i != e; ++i) { 2663 for (SUnit &SU : sunits)
2689 initVRegCycle(&sunits[i]); 2664 initVRegCycle(&SU);
2690 }
2691 }
2692 } 2665 }
2693 2666
2694 //===----------------------------------------------------------------------===// 2667 //===----------------------------------------------------------------------===//
2695 // Preschedule for Register Pressure 2668 // Preschedule for Register Pressure
2696 //===----------------------------------------------------------------------===// 2669 //===----------------------------------------------------------------------===//
2724 = TII->get(SU->getNode()->getMachineOpcode()).getImplicitDefs(); 2697 = TII->get(SU->getNode()->getMachineOpcode()).getImplicitDefs();
2725 const uint32_t *RegMask = getNodeRegMask(SU->getNode()); 2698 const uint32_t *RegMask = getNodeRegMask(SU->getNode());
2726 if(!ImpDefs && !RegMask) 2699 if(!ImpDefs && !RegMask)
2727 return false; 2700 return false;
2728 2701
2729 for (SUnit::const_succ_iterator SI = SU->Succs.begin(), SE = SU->Succs.end(); 2702 for (const SDep &Succ : SU->Succs) {
2730 SI != SE; ++SI) { 2703 SUnit *SuccSU = Succ.getSUnit();
2731 SUnit *SuccSU = SI->getSUnit(); 2704 for (const SDep &SuccPred : SuccSU->Preds) {
2732 for (SUnit::const_pred_iterator PI = SuccSU->Preds.begin(), 2705 if (!SuccPred.isAssignedRegDep())
2733 PE = SuccSU->Preds.end(); PI != PE; ++PI) {
2734 if (!PI->isAssignedRegDep())
2735 continue; 2706 continue;
2736 2707
2737 if (RegMask && MachineOperand::clobbersPhysReg(RegMask, PI->getReg()) && 2708 if (RegMask &&
2738 scheduleDAG->IsReachable(DepSU, PI->getSUnit())) 2709 MachineOperand::clobbersPhysReg(RegMask, SuccPred.getReg()) &&
2710 scheduleDAG->IsReachable(DepSU, SuccPred.getSUnit()))
2739 return true; 2711 return true;
2740 2712
2741 if (ImpDefs) 2713 if (ImpDefs)
2742 for (const MCPhysReg *ImpDef = ImpDefs; *ImpDef; ++ImpDef) 2714 for (const MCPhysReg *ImpDef = ImpDefs; *ImpDef; ++ImpDef)
2743 // Return true if SU clobbers this physical register use and the 2715 // Return true if SU clobbers this physical register use and the
2744 // definition of the register reaches from DepSU. IsReachable queries 2716 // definition of the register reaches from DepSU. IsReachable queries
2745 // a topological forward sort of the DAG (following the successors). 2717 // a topological forward sort of the DAG (following the successors).
2746 if (TRI->regsOverlap(*ImpDef, PI->getReg()) && 2718 if (TRI->regsOverlap(*ImpDef, SuccPred.getReg()) &&
2747 scheduleDAG->IsReachable(DepSU, PI->getSUnit())) 2719 scheduleDAG->IsReachable(DepSU, SuccPred.getSUnit()))
2748 return true; 2720 return true;
2749 } 2721 }
2750 } 2722 }
2751 return false; 2723 return false;
2752 } 2724 }
2821 /// after N, which shortens the U->N live range, reducing 2793 /// after N, which shortens the U->N live range, reducing
2822 /// register pressure. 2794 /// register pressure.
2823 /// 2795 ///
2824 void RegReductionPQBase::PrescheduleNodesWithMultipleUses() { 2796 void RegReductionPQBase::PrescheduleNodesWithMultipleUses() {
2825 // Visit all the nodes in topological order, working top-down. 2797 // Visit all the nodes in topological order, working top-down.
2826 for (unsigned i = 0, e = SUnits->size(); i != e; ++i) { 2798 for (SUnit &SU : *SUnits) {
2827 SUnit *SU = &(*SUnits)[i];
2828 // For now, only look at nodes with no data successors, such as stores. 2799 // For now, only look at nodes with no data successors, such as stores.
2829 // These are especially important, due to the heuristics in 2800 // These are especially important, due to the heuristics in
2830 // getNodePriority for nodes with no data successors. 2801 // getNodePriority for nodes with no data successors.
2831 if (SU->NumSuccs != 0) 2802 if (SU.NumSuccs != 0)
2832 continue; 2803 continue;
2833 // For now, only look at nodes with exactly one data predecessor. 2804 // For now, only look at nodes with exactly one data predecessor.
2834 if (SU->NumPreds != 1) 2805 if (SU.NumPreds != 1)
2835 continue; 2806 continue;
2836 // Avoid prescheduling copies to virtual registers, which don't behave 2807 // Avoid prescheduling copies to virtual registers, which don't behave
2837 // like other nodes from the perspective of scheduling heuristics. 2808 // like other nodes from the perspective of scheduling heuristics.
2838 if (SDNode *N = SU->getNode()) 2809 if (SDNode *N = SU.getNode())
2839 if (N->getOpcode() == ISD::CopyToReg && 2810 if (N->getOpcode() == ISD::CopyToReg &&
2840 TargetRegisterInfo::isVirtualRegister 2811 TargetRegisterInfo::isVirtualRegister
2841 (cast<RegisterSDNode>(N->getOperand(1))->getReg())) 2812 (cast<RegisterSDNode>(N->getOperand(1))->getReg()))
2842 continue; 2813 continue;
2843 2814
2844 // Locate the single data predecessor. 2815 // Locate the single data predecessor.
2845 SUnit *PredSU = nullptr; 2816 SUnit *PredSU = nullptr;
2846 for (SUnit::const_pred_iterator II = SU->Preds.begin(), 2817 for (const SDep &Pred : SU.Preds)
2847 EE = SU->Preds.end(); II != EE; ++II) 2818 if (!Pred.isCtrl()) {
2848 if (!II->isCtrl()) { 2819 PredSU = Pred.getSUnit();
2849 PredSU = II->getSUnit();
2850 break; 2820 break;
2851 } 2821 }
2852 assert(PredSU); 2822 assert(PredSU);
2853 2823
2854 // Don't rewrite edges that carry physregs, because that requires additional 2824 // Don't rewrite edges that carry physregs, because that requires additional
2858 // Short-circuit the case where SU is PredSU's only data successor. 2828 // Short-circuit the case where SU is PredSU's only data successor.
2859 if (PredSU->NumSuccs == 1) 2829 if (PredSU->NumSuccs == 1)
2860 continue; 2830 continue;
2861 // Avoid prescheduling to copies from virtual registers, which don't behave 2831 // Avoid prescheduling to copies from virtual registers, which don't behave
2862 // like other nodes from the perspective of scheduling heuristics. 2832 // like other nodes from the perspective of scheduling heuristics.
2863 if (SDNode *N = SU->getNode()) 2833 if (SDNode *N = SU.getNode())
2864 if (N->getOpcode() == ISD::CopyFromReg && 2834 if (N->getOpcode() == ISD::CopyFromReg &&
2865 TargetRegisterInfo::isVirtualRegister 2835 TargetRegisterInfo::isVirtualRegister
2866 (cast<RegisterSDNode>(N->getOperand(1))->getReg())) 2836 (cast<RegisterSDNode>(N->getOperand(1))->getReg()))
2867 continue; 2837 continue;
2868 2838
2869 // Perform checks on the successors of PredSU. 2839 // Perform checks on the successors of PredSU.
2870 for (SUnit::const_succ_iterator II = PredSU->Succs.begin(), 2840 for (const SDep &PredSucc : PredSU->Succs) {
2871 EE = PredSU->Succs.end(); II != EE; ++II) { 2841 SUnit *PredSuccSU = PredSucc.getSUnit();
2872 SUnit *PredSuccSU = II->getSUnit(); 2842 if (PredSuccSU == &SU) continue;
2873 if (PredSuccSU == SU) continue;
2874 // If PredSU has another successor with no data successors, for 2843 // If PredSU has another successor with no data successors, for
2875 // now don't attempt to choose either over the other. 2844 // now don't attempt to choose either over the other.
2876 if (PredSuccSU->NumSuccs == 0) 2845 if (PredSuccSU->NumSuccs == 0)
2877 goto outer_loop_continue; 2846 goto outer_loop_continue;
2878 // Don't break physical register dependencies. 2847 // Don't break physical register dependencies.
2879 if (SU->hasPhysRegClobbers && PredSuccSU->hasPhysRegDefs) 2848 if (SU.hasPhysRegClobbers && PredSuccSU->hasPhysRegDefs)
2880 if (canClobberPhysRegDefs(PredSuccSU, SU, TII, TRI)) 2849 if (canClobberPhysRegDefs(PredSuccSU, &SU, TII, TRI))
2881 goto outer_loop_continue; 2850 goto outer_loop_continue;
2882 // Don't introduce graph cycles. 2851 // Don't introduce graph cycles.
2883 if (scheduleDAG->IsReachable(SU, PredSuccSU)) 2852 if (scheduleDAG->IsReachable(&SU, PredSuccSU))
2884 goto outer_loop_continue; 2853 goto outer_loop_continue;
2885 } 2854 }
2886 2855
2887 // Ok, the transformation is safe and the heuristics suggest it is 2856 // Ok, the transformation is safe and the heuristics suggest it is
2888 // profitable. Update the graph. 2857 // profitable. Update the graph.
2889 DEBUG(dbgs() << " Prescheduling SU #" << SU->NodeNum 2858 DEBUG(dbgs() << " Prescheduling SU #" << SU.NodeNum
2890 << " next to PredSU #" << PredSU->NodeNum 2859 << " next to PredSU #" << PredSU->NodeNum
2891 << " to guide scheduling in the presence of multiple uses\n"); 2860 << " to guide scheduling in the presence of multiple uses\n");
2892 for (unsigned i = 0; i != PredSU->Succs.size(); ++i) { 2861 for (unsigned i = 0; i != PredSU->Succs.size(); ++i) {
2893 SDep Edge = PredSU->Succs[i]; 2862 SDep Edge = PredSU->Succs[i];
2894 assert(!Edge.isAssignedRegDep()); 2863 assert(!Edge.isAssignedRegDep());
2895 SUnit *SuccSU = Edge.getSUnit(); 2864 SUnit *SuccSU = Edge.getSUnit();
2896 if (SuccSU != SU) { 2865 if (SuccSU != &SU) {
2897 Edge.setSUnit(PredSU); 2866 Edge.setSUnit(PredSU);
2898 scheduleDAG->RemovePred(SuccSU, Edge); 2867 scheduleDAG->RemovePred(SuccSU, Edge);
2899 scheduleDAG->AddPred(SU, Edge); 2868 scheduleDAG->AddPred(&SU, Edge);
2900 Edge.setSUnit(SU); 2869 Edge.setSUnit(&SU);
2901 scheduleDAG->AddPred(SuccSU, Edge); 2870 scheduleDAG->AddPred(SuccSU, Edge);
2902 --i; 2871 --i;
2903 } 2872 }
2904 } 2873 }
2905 outer_loop_continue:; 2874 outer_loop_continue:;
2912 /// first (lower in the schedule). If both nodes are two-address, favor the 2881 /// first (lower in the schedule). If both nodes are two-address, favor the
2913 /// one that has a CopyToReg use (more likely to be a loop induction update). 2882 /// one that has a CopyToReg use (more likely to be a loop induction update).
2914 /// If both are two-address, but one is commutable while the other is not 2883 /// If both are two-address, but one is commutable while the other is not
2915 /// commutable, favor the one that's not commutable. 2884 /// commutable, favor the one that's not commutable.
2916 void RegReductionPQBase::AddPseudoTwoAddrDeps() { 2885 void RegReductionPQBase::AddPseudoTwoAddrDeps() {
2917 for (unsigned i = 0, e = SUnits->size(); i != e; ++i) { 2886 for (SUnit &SU : *SUnits) {
2918 SUnit *SU = &(*SUnits)[i]; 2887 if (!SU.isTwoAddress)
2919 if (!SU->isTwoAddress)
2920 continue; 2888 continue;
2921 2889
2922 SDNode *Node = SU->getNode(); 2890 SDNode *Node = SU.getNode();
2923 if (!Node || !Node->isMachineOpcode() || SU->getNode()->getGluedNode()) 2891 if (!Node || !Node->isMachineOpcode() || SU.getNode()->getGluedNode())
2924 continue; 2892 continue;
2925 2893
2926 bool isLiveOut = hasOnlyLiveOutUses(SU); 2894 bool isLiveOut = hasOnlyLiveOutUses(&SU);
2927 unsigned Opc = Node->getMachineOpcode(); 2895 unsigned Opc = Node->getMachineOpcode();
2928 const MCInstrDesc &MCID = TII->get(Opc); 2896 const MCInstrDesc &MCID = TII->get(Opc);
2929 unsigned NumRes = MCID.getNumDefs(); 2897 unsigned NumRes = MCID.getNumDefs();
2930 unsigned NumOps = MCID.getNumOperands() - NumRes; 2898 unsigned NumOps = MCID.getNumOperands() - NumRes;
2931 for (unsigned j = 0; j != NumOps; ++j) { 2899 for (unsigned j = 0; j != NumOps; ++j) {
2932 if (MCID.getOperandConstraint(j+NumRes, MCOI::TIED_TO) == -1) 2900 if (MCID.getOperandConstraint(j+NumRes, MCOI::TIED_TO) == -1)
2933 continue; 2901 continue;
2934 SDNode *DU = SU->getNode()->getOperand(j).getNode(); 2902 SDNode *DU = SU.getNode()->getOperand(j).getNode();
2935 if (DU->getNodeId() == -1) 2903 if (DU->getNodeId() == -1)
2936 continue; 2904 continue;
2937 const SUnit *DUSU = &(*SUnits)[DU->getNodeId()]; 2905 const SUnit *DUSU = &(*SUnits)[DU->getNodeId()];
2938 if (!DUSU) continue; 2906 if (!DUSU)
2939 for (SUnit::const_succ_iterator I = DUSU->Succs.begin(), 2907 continue;
2940 E = DUSU->Succs.end(); I != E; ++I) { 2908 for (const SDep &Succ : DUSU->Succs) {
2941 if (I->isCtrl()) continue; 2909 if (Succ.isCtrl())
2942 SUnit *SuccSU = I->getSUnit(); 2910 continue;
2943 if (SuccSU == SU) 2911 SUnit *SuccSU = Succ.getSUnit();
2912 if (SuccSU == &SU)
2944 continue; 2913 continue;
2945 // Be conservative. Ignore if nodes aren't at roughly the same 2914 // Be conservative. Ignore if nodes aren't at roughly the same
2946 // depth and height. 2915 // depth and height.
2947 if (SuccSU->getHeight() < SU->getHeight() && 2916 if (SuccSU->getHeight() < SU.getHeight() &&
2948 (SU->getHeight() - SuccSU->getHeight()) > 1) 2917 (SU.getHeight() - SuccSU->getHeight()) > 1)
2949 continue; 2918 continue;
2950 // Skip past COPY_TO_REGCLASS nodes, so that the pseudo edge 2919 // Skip past COPY_TO_REGCLASS nodes, so that the pseudo edge
2951 // constrains whatever is using the copy, instead of the copy 2920 // constrains whatever is using the copy, instead of the copy
2952 // itself. In the case that the copy is coalesced, this 2921 // itself. In the case that the copy is coalesced, this
2953 // preserves the intent of the pseudo two-address heurietics. 2922 // preserves the intent of the pseudo two-address heurietics.
2959 // Don't constrain non-instruction nodes. 2928 // Don't constrain non-instruction nodes.
2960 if (!SuccSU->getNode() || !SuccSU->getNode()->isMachineOpcode()) 2929 if (!SuccSU->getNode() || !SuccSU->getNode()->isMachineOpcode())
2961 continue; 2930 continue;
2962 // Don't constrain nodes with physical register defs if the 2931 // Don't constrain nodes with physical register defs if the
2963 // predecessor can clobber them. 2932 // predecessor can clobber them.
2964 if (SuccSU->hasPhysRegDefs && SU->hasPhysRegClobbers) { 2933 if (SuccSU->hasPhysRegDefs && SU.hasPhysRegClobbers) {
2965 if (canClobberPhysRegDefs(SuccSU, SU, TII, TRI)) 2934 if (canClobberPhysRegDefs(SuccSU, &SU, TII, TRI))
2966 continue; 2935 continue;
2967 } 2936 }
2968 // Don't constrain EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG; 2937 // Don't constrain EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG;
2969 // these may be coalesced away. We want them close to their uses. 2938 // these may be coalesced away. We want them close to their uses.
2970 unsigned SuccOpc = SuccSU->getNode()->getMachineOpcode(); 2939 unsigned SuccOpc = SuccSU->getNode()->getMachineOpcode();
2971 if (SuccOpc == TargetOpcode::EXTRACT_SUBREG || 2940 if (SuccOpc == TargetOpcode::EXTRACT_SUBREG ||
2972 SuccOpc == TargetOpcode::INSERT_SUBREG || 2941 SuccOpc == TargetOpcode::INSERT_SUBREG ||
2973 SuccOpc == TargetOpcode::SUBREG_TO_REG) 2942 SuccOpc == TargetOpcode::SUBREG_TO_REG)
2974 continue; 2943 continue;
2975 if (!canClobberReachingPhysRegUse(SuccSU, SU, scheduleDAG, TII, TRI) && 2944 if (!canClobberReachingPhysRegUse(SuccSU, &SU, scheduleDAG, TII, TRI) &&
2976 (!canClobber(SuccSU, DUSU) || 2945 (!canClobber(SuccSU, DUSU) ||
2977 (isLiveOut && !hasOnlyLiveOutUses(SuccSU)) || 2946 (isLiveOut && !hasOnlyLiveOutUses(SuccSU)) ||
2978 (!SU->isCommutable && SuccSU->isCommutable)) && 2947 (!SU.isCommutable && SuccSU->isCommutable)) &&
2979 !scheduleDAG->IsReachable(SuccSU, SU)) { 2948 !scheduleDAG->IsReachable(SuccSU, &SU)) {
2980 DEBUG(dbgs() << " Adding a pseudo-two-addr edge from SU #" 2949 DEBUG(dbgs() << " Adding a pseudo-two-addr edge from SU #"
2981 << SU->NodeNum << " to SU #" << SuccSU->NodeNum << "\n"); 2950 << SU.NodeNum << " to SU #" << SuccSU->NodeNum << "\n");
2982 scheduleDAG->AddPred(SU, SDep(SuccSU, SDep::Artificial)); 2951 scheduleDAG->AddPred(&SU, SDep(SuccSU, SDep::Artificial));
2983 } 2952 }
2984 } 2953 }
2985 } 2954 }
2986 } 2955 }
2987 } 2956 }