Mercurial > hg > CbC > CbC_llvm

comparison lib/CodeGen/VirtRegMap.cpp @ 120:1172e4bd9c6f

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents 7d135dc70f03
children 803732b1fca8
comparison
equal deleted inserted replaced
101:34baf5011add 120:1172e4bd9c6f
17 //===----------------------------------------------------------------------===// 17 //===----------------------------------------------------------------------===//
18 18
19 #include "llvm/CodeGen/VirtRegMap.h" 19 #include "llvm/CodeGen/VirtRegMap.h"
20 #include "LiveDebugVariables.h" 20 #include "LiveDebugVariables.h"
21 #include "llvm/ADT/STLExtras.h" 21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/SparseSet.h"
23 #include "llvm/ADT/Statistic.h" 22 #include "llvm/ADT/Statistic.h"
24 #include "llvm/CodeGen/LiveIntervalAnalysis.h" 23 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
25 #include "llvm/CodeGen/LiveStackAnalysis.h" 24 #include "llvm/CodeGen/LiveStackAnalysis.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h" 26 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h" 27 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h" 28 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/Passes.h" 29 #include "llvm/CodeGen/Passes.h"
31 #include "llvm/IR/Function.h" 30 #include "llvm/IR/Function.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Compiler.h" 31 #include "llvm/Support/Compiler.h"
34 #include "llvm/Support/Debug.h" 32 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/raw_ostream.h" 33 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetInstrInfo.h" 34 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Target/TargetMachine.h" 35 #include "llvm/Target/TargetMachine.h"
73 Virt2StackSlotMap.resize(NumRegs); 71 Virt2StackSlotMap.resize(NumRegs);
74 Virt2SplitMap.resize(NumRegs); 72 Virt2SplitMap.resize(NumRegs);
75 } 73 }
76 74
77 unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) { 75 unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) {
78 int SS = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(), 76 int SS = MF->getFrameInfo().CreateSpillStackObject(RC->getSize(),
79 RC->getAlignment()); 77 RC->getAlignment());
80 ++NumSpillSlots; 78 ++NumSpillSlots;
81 return SS; 79 return SS;
82 } 80 }
83 81
84 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) { 82 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) {
85 unsigned Hint = MRI->getSimpleHint(VirtReg); 83 unsigned Hint = MRI->getSimpleHint(VirtReg);
86 if (!Hint) 84 if (!Hint)
87 return 0; 85 return false;
88 if (TargetRegisterInfo::isVirtualRegister(Hint)) 86 if (TargetRegisterInfo::isVirtualRegister(Hint))
89 Hint = getPhys(Hint); 87 Hint = getPhys(Hint);
90 return getPhys(VirtReg) == Hint; 88 return getPhys(VirtReg) == Hint;
91 } 89 }
92 90
110 void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) { 108 void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) {
111 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); 109 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
112 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && 110 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
113 "attempt to assign stack slot to already spilled register"); 111 "attempt to assign stack slot to already spilled register");
114 assert((SS >= 0 || 112 assert((SS >= 0 ||
115 (SS >= MF->getFrameInfo()->getObjectIndexBegin())) && 113 (SS >= MF->getFrameInfo().getObjectIndexBegin())) &&
116 "illegal fixed frame index"); 114 "illegal fixed frame index");
117 Virt2StackSlotMap[virtReg] = SS; 115 Virt2StackSlotMap[virtReg] = SS;
118 } 116 }
119 117
120 void VirtRegMap::print(raw_ostream &OS, const Module*) const { 118 void VirtRegMap::print(raw_ostream &OS, const Module*) const {
137 } 135 }
138 OS << '\n'; 136 OS << '\n';
139 } 137 }
140 138
141 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 139 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
142 void VirtRegMap::dump() const { 140 LLVM_DUMP_METHOD void VirtRegMap::dump() const {
143 print(dbgs()); 141 print(dbgs());
144 } 142 }
145 #endif 143 #endif
146 144
147 //===----------------------------------------------------------------------===// 145 //===----------------------------------------------------------------------===//
166 164
167 void rewrite(); 165 void rewrite();
168 void addMBBLiveIns(); 166 void addMBBLiveIns();
169 bool readsUndefSubreg(const MachineOperand &MO) const; 167 bool readsUndefSubreg(const MachineOperand &MO) const;
170 void addLiveInsForSubRanges(const LiveInterval &LI, unsigned PhysReg) const; 168 void addLiveInsForSubRanges(const LiveInterval &LI, unsigned PhysReg) const;
169 void handleIdentityCopy(MachineInstr &MI) const;
171 170
172 public: 171 public:
173 static char ID; 172 static char ID;
174 VirtRegRewriter() : MachineFunctionPass(ID) {} 173 VirtRegRewriter() : MachineFunctionPass(ID) {}
175 174
176 void getAnalysisUsage(AnalysisUsage &AU) const override; 175 void getAnalysisUsage(AnalysisUsage &AU) const override;
177 176
178 bool runOnMachineFunction(MachineFunction&) override; 177 bool runOnMachineFunction(MachineFunction&) override;
178 MachineFunctionProperties getSetProperties() const override {
179 return MachineFunctionProperties().set(
180 MachineFunctionProperties::Property::NoVRegs);
181 }
179 }; 182 };
180 } // end anonymous namespace 183 } // end anonymous namespace
181 184
182 char &llvm::VirtRegRewriterID = VirtRegRewriter::ID; 185 char &llvm::VirtRegRewriterID = VirtRegRewriter::ID;
183 186
327 return true; 330 return true;
328 331
329 unsigned Reg = MO.getReg(); 332 unsigned Reg = MO.getReg();
330 const LiveInterval &LI = LIS->getInterval(Reg); 333 const LiveInterval &LI = LIS->getInterval(Reg);
331 const MachineInstr &MI = *MO.getParent(); 334 const MachineInstr &MI = *MO.getParent();
332 SlotIndex BaseIndex = LIS->getInstructionIndex(&MI); 335 SlotIndex BaseIndex = LIS->getInstructionIndex(MI);
333 // This code is only meant to handle reading undefined subregisters which 336 // This code is only meant to handle reading undefined subregisters which
334 // we couldn't properly detect before. 337 // we couldn't properly detect before.
335 assert(LI.liveAt(BaseIndex) && 338 assert(LI.liveAt(BaseIndex) &&
336 "Reads of completely dead register should be marked undef already"); 339 "Reads of completely dead register should be marked undef already");
337 unsigned SubRegIdx = MO.getSubReg(); 340 unsigned SubRegIdx = MO.getSubReg();
341 assert(SubRegIdx != 0 && LI.hasSubRanges());
338 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx); 342 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx);
339 // See if any of the relevant subregister liveranges is defined at this point. 343 // See if any of the relevant subregister liveranges is defined at this point.
340 for (const LiveInterval::SubRange &SR : LI.subranges()) { 344 for (const LiveInterval::SubRange &SR : LI.subranges()) {
341 if ((SR.LaneMask & UseMask) != 0 && SR.liveAt(BaseIndex)) 345 if ((SR.LaneMask & UseMask) != 0 && SR.liveAt(BaseIndex))
342 return false; 346 return false;
343 } 347 }
344 return true; 348 return true;
349 }
350
351 void VirtRegRewriter::handleIdentityCopy(MachineInstr &MI) const {
352 if (!MI.isIdentityCopy())
353 return;
354 DEBUG(dbgs() << "Identity copy: " << MI);
355 ++NumIdCopies;
356
357 // Copies like:
358 // %R0 = COPY %R0<undef>
359 // %AL = COPY %AL, %EAX<imp-def>
360 // give us additional liveness information: The target (super-)register
361 // must not be valid before this point. Replace the COPY with a KILL
362 // instruction to maintain this information.
363 if (MI.getOperand(0).isUndef() || MI.getNumOperands() > 2) {
364 MI.setDesc(TII->get(TargetOpcode::KILL));
365 DEBUG(dbgs() << " replace by: " << MI);
366 return;
367 }
368
369 if (Indexes)
370 Indexes->removeMachineInstrFromMaps(MI);
371 MI.eraseFromParent();
372 DEBUG(dbgs() << " deleted.\n");
345 } 373 }
346 374
347 void VirtRegRewriter::rewrite() { 375 void VirtRegRewriter::rewrite() {
348 bool NoSubRegLiveness = !MRI->subRegLivenessEnabled(); 376 bool NoSubRegLiveness = !MRI->subRegLivenessEnabled();
349 SmallVector<unsigned, 8> SuperDeads; 377 SmallVector<unsigned, 8> SuperDeads;
431 while (!SuperDefs.empty()) 459 while (!SuperDefs.empty())
432 MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI); 460 MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI);
433 461
434 DEBUG(dbgs() << "> " << *MI); 462 DEBUG(dbgs() << "> " << *MI);
435 463
436 // Finally, remove any identity copies. 464 // We can remove identity copies right now.
437 if (MI->isIdentityCopy()) { 465 handleIdentityCopy(*MI);
438 ++NumIdCopies;
439 DEBUG(dbgs() << "Deleting identity copy.\n");
440 if (Indexes)
441 Indexes->removeMachineInstrFromMaps(MI);
442 // It's safe to erase MI because MII has already been incremented.
443 MI->eraseFromParent();
444 }
445 } 466 }
446 } 467 }
447 } 468 }
448