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comparison lib/Target/AVR/AVRISelLowering.h @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
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101:34baf5011add 120:1172e4bd9c6f
1 //===-- AVRISelLowering.h - AVR DAG Lowering Interface ----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that AVR uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #ifndef LLVM_AVR_ISEL_LOWERING_H
16 #define LLVM_AVR_ISEL_LOWERING_H
17
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/Target/TargetLowering.h"
20
21 namespace llvm {
22
23 namespace AVRISD {
24
25 /// AVR Specific DAG Nodes
26 enum NodeType {
27 /// Start the numbering where the builtin ops leave off.
28 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 /// Return from subroutine.
30 RET_FLAG,
31 /// Return from ISR.
32 RETI_FLAG,
33 /// Represents an abstract call instruction,
34 /// which includes a bunch of information.
35 CALL,
36 /// A wrapper node for TargetConstantPool,
37 /// TargetExternalSymbol, and TargetGlobalAddress.
38 WRAPPER,
39 LSL, ///< Logical shift left.
40 LSR, ///< Logical shift right.
41 ASR, ///< Arithmetic shift right.
42 ROR, ///< Bit rotate right.
43 ROL, ///< Bit rotate left.
44 LSLLOOP, ///< A loop of single logical shift left instructions.
45 LSRLOOP, ///< A loop of single logical shift right instructions.
46 ASRLOOP, ///< A loop of single arithmetic shift right instructions.
47 /// AVR conditional branches. Operand 0 is the chain operand, operand 1
48 /// is the block to branch if condition is true, operand 2 is the
49 /// condition code, and operand 3 is the flag operand produced by a CMP
50 /// or TEST instruction.
51 BRCOND,
52 /// Compare instruction.
53 CMP,
54 /// Compare with carry instruction.
55 CMPC,
56 /// Test for zero or minus instruction.
57 TST,
58 /// Operand 0 and operand 1 are selection variable, operand 2
59 /// is condition code and operand 3 is flag operand.
60 SELECT_CC
61 };
62
63 } // end of namespace AVRISD
64
65 class AVRTargetMachine;
66
67 /// Performs target lowering for the AVR.
68 class AVRTargetLowering : public TargetLowering {
69 public:
70 explicit AVRTargetLowering(AVRTargetMachine &TM);
71
72 public:
73 MVT getScalarShiftAmountTy(const DataLayout &, EVT LHSTy) const override {
74 return MVT::i8;
75 }
76 const char *getTargetNodeName(unsigned Opcode) const override;
77
78 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
79
80 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
81 SelectionDAG &DAG) const override;
82
83 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
84 unsigned AS) const override;
85
86 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
87 ISD::MemIndexedMode &AM,
88 SelectionDAG &DAG) const override;
89
90 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
91 SDValue &Offset, ISD::MemIndexedMode &AM,
92 SelectionDAG &DAG) const override;
93
94 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
95
96 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
97 EVT VT) const override;
98
99 MachineBasicBlock *
100 EmitInstrWithCustomInserter(MachineInstr &MI,
101 MachineBasicBlock *MBB) const override;
102
103 ConstraintType getConstraintType(StringRef Constraint) const override;
104
105 ConstraintWeight
106 getSingleConstraintMatchWeight(AsmOperandInfo &info,
107 const char *constraint) const override;
108
109 std::pair<unsigned, const TargetRegisterClass *>
110 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
111 StringRef Constraint, MVT VT) const override;
112
113 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
114
115 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
116 std::vector<SDValue> &Ops,
117 SelectionDAG &DAG) const override;
118
119 private:
120 SDValue getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AVRcc,
121 SelectionDAG &DAG, SDLoc dl) const;
122 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
123 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
124 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
125 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
126 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
127 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
128 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
129 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
130 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
131
132 CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC) const;
133
134 bool CanLowerReturn(CallingConv::ID CallConv,
135 MachineFunction &MF, bool isVarArg,
136 const SmallVectorImpl<ISD::OutputArg> &Outs,
137 LLVMContext &Context) const override;
138
139 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
140 const SmallVectorImpl<ISD::OutputArg> &Outs,
141 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
142 SelectionDAG &DAG) const override;
143 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
144 bool isVarArg,
145 const SmallVectorImpl<ISD::InputArg> &Ins,
146 const SDLoc &dl, SelectionDAG &DAG,
147 SmallVectorImpl<SDValue> &InVals) const override;
148 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
149 SmallVectorImpl<SDValue> &InVals) const override;
150 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
151 CallingConv::ID CallConv, bool isVarArg,
152 const SmallVectorImpl<ISD::InputArg> &Ins,
153 const SDLoc &dl, SelectionDAG &DAG,
154 SmallVectorImpl<SDValue> &InVals) const;
155
156 private:
157 MachineBasicBlock *insertShift(MachineInstr &MI, MachineBasicBlock *BB) const;
158 MachineBasicBlock *insertMul(MachineInstr &MI, MachineBasicBlock *BB) const;
159 };
160
161 } // end namespace llvm
162
163 #endif // LLVM_AVR_ISEL_LOWERING_H