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comparison lib/Target/Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
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101:34baf5011add 120:1172e4bd9c6f
1 //===-- LanaiMCCodeEmitter.cpp - Convert Lanai code to machine code -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the LanaiMCCodeEmitter class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "Lanai.h"
15 #include "MCTargetDesc/LanaiBaseInfo.h"
16 #include "MCTargetDesc/LanaiFixupKinds.h"
17 #include "MCTargetDesc/LanaiMCExpr.h"
18 #include "MCTargetDesc/LanaiMCTargetDesc.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/MC/MCCodeEmitter.h"
21 #include "llvm/MC/MCFixup.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/MC/MCSymbol.h"
27 #include "llvm/Support/raw_ostream.h"
28
29 #define DEBUG_TYPE "mccodeemitter"
30
31 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
32
33 namespace llvm {
34 namespace {
35 class LanaiMCCodeEmitter : public MCCodeEmitter {
36 LanaiMCCodeEmitter(const LanaiMCCodeEmitter &); // DO NOT IMPLEMENT
37 void operator=(const LanaiMCCodeEmitter &); // DO NOT IMPLEMENT
38 const MCInstrInfo &InstrInfo;
39 MCContext &Context;
40
41 public:
42 LanaiMCCodeEmitter(const MCInstrInfo &MCII, MCContext &C)
43 : InstrInfo(MCII), Context(C) {}
44
45 ~LanaiMCCodeEmitter() override {}
46
47 // The functions below are called by TableGen generated functions for getting
48 // the binary encoding of instructions/opereands.
49
50 // getBinaryCodeForInstr - TableGen'erated function for getting the
51 // binary encoding for an instruction.
52 uint64_t getBinaryCodeForInstr(const MCInst &Inst,
53 SmallVectorImpl<MCFixup> &Fixups,
54 const MCSubtargetInfo &SubtargetInfo) const;
55
56 // getMachineOpValue - Return binary encoding of operand. If the machine
57 // operand requires relocation, record the relocation and return zero.
58 unsigned getMachineOpValue(const MCInst &Inst, const MCOperand &MCOp,
59 SmallVectorImpl<MCFixup> &Fixups,
60 const MCSubtargetInfo &SubtargetInfo) const;
61
62 unsigned getRiMemoryOpValue(const MCInst &Inst, unsigned OpNo,
63 SmallVectorImpl<MCFixup> &Fixups,
64 const MCSubtargetInfo &SubtargetInfo) const;
65
66 unsigned getRrMemoryOpValue(const MCInst &Inst, unsigned OpNo,
67 SmallVectorImpl<MCFixup> &Fixups,
68 const MCSubtargetInfo &SubtargetInfo) const;
69
70 unsigned getSplsOpValue(const MCInst &Inst, unsigned OpNo,
71 SmallVectorImpl<MCFixup> &Fixups,
72 const MCSubtargetInfo &SubtargetInfo) const;
73
74 unsigned getBranchTargetOpValue(const MCInst &Inst, unsigned OpNo,
75 SmallVectorImpl<MCFixup> &Fixups,
76 const MCSubtargetInfo &SubtargetInfo) const;
77
78 void encodeInstruction(const MCInst &Inst, raw_ostream &Ostream,
79 SmallVectorImpl<MCFixup> &Fixups,
80 const MCSubtargetInfo &SubtargetInfo) const override;
81
82 unsigned adjustPqBitsRmAndRrm(const MCInst &Inst, unsigned Value,
83 const MCSubtargetInfo &STI) const;
84
85 unsigned adjustPqBitsSpls(const MCInst &Inst, unsigned Value,
86 const MCSubtargetInfo &STI) const;
87 };
88
89 Lanai::Fixups FixupKind(const MCExpr *Expr) {
90 if (isa<MCSymbolRefExpr>(Expr))
91 return Lanai::FIXUP_LANAI_21;
92 if (const LanaiMCExpr *McExpr = dyn_cast<LanaiMCExpr>(Expr)) {
93 LanaiMCExpr::VariantKind ExprKind = McExpr->getKind();
94 switch (ExprKind) {
95 case LanaiMCExpr::VK_Lanai_None:
96 return Lanai::FIXUP_LANAI_21;
97 case LanaiMCExpr::VK_Lanai_ABS_HI:
98 return Lanai::FIXUP_LANAI_HI16;
99 case LanaiMCExpr::VK_Lanai_ABS_LO:
100 return Lanai::FIXUP_LANAI_LO16;
101 }
102 }
103 return Lanai::Fixups(0);
104 }
105
106 // getMachineOpValue - Return binary encoding of operand. If the machine
107 // operand requires relocation, record the relocation and return zero.
108 unsigned LanaiMCCodeEmitter::getMachineOpValue(
109 const MCInst &Inst, const MCOperand &MCOp, SmallVectorImpl<MCFixup> &Fixups,
110 const MCSubtargetInfo &SubtargetInfo) const {
111 if (MCOp.isReg())
112 return getLanaiRegisterNumbering(MCOp.getReg());
113 if (MCOp.isImm())
114 return static_cast<unsigned>(MCOp.getImm());
115
116 // MCOp must be an expression
117 assert(MCOp.isExpr());
118 const MCExpr *Expr = MCOp.getExpr();
119
120 // Extract the symbolic reference side of a binary expression.
121 if (Expr->getKind() == MCExpr::Binary) {
122 const MCBinaryExpr *BinaryExpr = static_cast<const MCBinaryExpr *>(Expr);
123 Expr = BinaryExpr->getLHS();
124 }
125
126 assert(isa<LanaiMCExpr>(Expr) || Expr->getKind() == MCExpr::SymbolRef);
127 // Push fixup (all info is contained within)
128 Fixups.push_back(
129 MCFixup::create(0, MCOp.getExpr(), MCFixupKind(FixupKind(Expr))));
130 return 0;
131 }
132
133 // Helper function to adjust P and Q bits on load and store instructions.
134 unsigned adjustPqBits(const MCInst &Inst, unsigned Value, unsigned PBitShift,
135 unsigned QBitShift) {
136 const MCOperand AluOp = Inst.getOperand(3);
137 unsigned AluCode = AluOp.getImm();
138
139 // Set the P bit to one iff the immediate is nonzero and not a post-op
140 // instruction.
141 const MCOperand Op2 = Inst.getOperand(2);
142 Value &= ~(1 << PBitShift);
143 if (!LPAC::isPostOp(AluCode) &&
144 ((Op2.isImm() && Op2.getImm() != 0) ||
145 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr())))
146 Value |= (1 << PBitShift);
147
148 // Set the Q bit to one iff it is a post- or pre-op instruction.
149 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() &&
150 "Expected register operand.");
151 Value &= ~(1 << QBitShift);
152 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) ||
153 (Op2.isReg() && Op2.getReg() != Lanai::R0)))
154 Value |= (1 << QBitShift);
155
156 return Value;
157 }
158
159 unsigned
160 LanaiMCCodeEmitter::adjustPqBitsRmAndRrm(const MCInst &Inst, unsigned Value,
161 const MCSubtargetInfo &STI) const {
162 return adjustPqBits(Inst, Value, 17, 16);
163 }
164
165 unsigned
166 LanaiMCCodeEmitter::adjustPqBitsSpls(const MCInst &Inst, unsigned Value,
167 const MCSubtargetInfo &STI) const {
168 return adjustPqBits(Inst, Value, 11, 10);
169 }
170
171 void LanaiMCCodeEmitter::encodeInstruction(
172 const MCInst &Inst, raw_ostream &Ostream, SmallVectorImpl<MCFixup> &Fixups,
173 const MCSubtargetInfo &SubtargetInfo) const {
174 // Get instruction encoding and emit it
175 unsigned Value = getBinaryCodeForInstr(Inst, Fixups, SubtargetInfo);
176 ++MCNumEmitted; // Keep track of the number of emitted insns.
177
178 // Emit bytes in big-endian
179 for (int i = (4 - 1) * 8; i >= 0; i -= 8)
180 Ostream << static_cast<char>((Value >> i) & 0xff);
181 }
182
183 // Encode Lanai Memory Operand
184 unsigned LanaiMCCodeEmitter::getRiMemoryOpValue(
185 const MCInst &Inst, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
186 const MCSubtargetInfo &SubtargetInfo) const {
187 unsigned Encoding;
188 const MCOperand Op1 = Inst.getOperand(OpNo + 0);
189 const MCOperand Op2 = Inst.getOperand(OpNo + 1);
190 const MCOperand AluOp = Inst.getOperand(OpNo + 2);
191
192 assert(Op1.isReg() && "First operand is not register.");
193 assert((Op2.isImm() || Op2.isExpr()) &&
194 "Second operand is neither an immediate nor an expression.");
195 assert((LPAC::getAluOp(AluOp.getImm()) == LPAC::ADD) &&
196 "Register immediate only supports addition operator");
197
198 Encoding = (getLanaiRegisterNumbering(Op1.getReg()) << 18);
199 if (Op2.isImm()) {
200 assert(isInt<16>(Op2.getImm()) &&
201 "Constant value truncated (limited to 16-bit)");
202
203 Encoding |= (Op2.getImm() & 0xffff);
204 if (Op2.getImm() != 0) {
205 if (LPAC::isPreOp(AluOp.getImm()))
206 Encoding |= (0x3 << 16);
207 if (LPAC::isPostOp(AluOp.getImm()))
208 Encoding |= (0x1 << 16);
209 }
210 } else
211 getMachineOpValue(Inst, Op2, Fixups, SubtargetInfo);
212
213 return Encoding;
214 }
215
216 unsigned LanaiMCCodeEmitter::getRrMemoryOpValue(
217 const MCInst &Inst, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
218 const MCSubtargetInfo &SubtargetInfo) const {
219 unsigned Encoding;
220 const MCOperand Op1 = Inst.getOperand(OpNo + 0);
221 const MCOperand Op2 = Inst.getOperand(OpNo + 1);
222 const MCOperand AluMCOp = Inst.getOperand(OpNo + 2);
223
224 assert(Op1.isReg() && "First operand is not register.");
225 Encoding = (getLanaiRegisterNumbering(Op1.getReg()) << 15);
226 assert(Op2.isReg() && "Second operand is not register.");
227 Encoding |= (getLanaiRegisterNumbering(Op2.getReg()) << 10);
228
229 assert(AluMCOp.isImm() && "Third operator is not immediate.");
230 // Set BBB
231 unsigned AluOp = AluMCOp.getImm();
232 Encoding |= LPAC::encodeLanaiAluCode(AluOp) << 5;
233 // Set P and Q
234 if (LPAC::isPreOp(AluOp))
235 Encoding |= (0x3 << 8);
236 if (LPAC::isPostOp(AluOp))
237 Encoding |= (0x1 << 8);
238 // Set JJJJ
239 switch (LPAC::getAluOp(AluOp)) {
240 case LPAC::SHL:
241 case LPAC::SRL:
242 Encoding |= 0x10;
243 break;
244 case LPAC::SRA:
245 Encoding |= 0x18;
246 break;
247 default:
248 break;
249 }
250
251 return Encoding;
252 }
253
254 unsigned
255 LanaiMCCodeEmitter::getSplsOpValue(const MCInst &Inst, unsigned OpNo,
256 SmallVectorImpl<MCFixup> &Fixups,
257 const MCSubtargetInfo &SubtargetInfo) const {
258 unsigned Encoding;
259 const MCOperand Op1 = Inst.getOperand(OpNo + 0);
260 const MCOperand Op2 = Inst.getOperand(OpNo + 1);
261 const MCOperand AluOp = Inst.getOperand(OpNo + 2);
262
263 assert(Op1.isReg() && "First operand is not register.");
264 assert((Op2.isImm() || Op2.isExpr()) &&
265 "Second operand is neither an immediate nor an expression.");
266 assert((LPAC::getAluOp(AluOp.getImm()) == LPAC::ADD) &&
267 "Register immediate only supports addition operator");
268
269 Encoding = (getLanaiRegisterNumbering(Op1.getReg()) << 12);
270 if (Op2.isImm()) {
271 assert(isInt<10>(Op2.getImm()) &&
272 "Constant value truncated (limited to 10-bit)");
273
274 Encoding |= (Op2.getImm() & 0x3ff);
275 if (Op2.getImm() != 0) {
276 if (LPAC::isPreOp(AluOp.getImm()))
277 Encoding |= (0x3 << 10);
278 if (LPAC::isPostOp(AluOp.getImm()))
279 Encoding |= (0x1 << 10);
280 }
281 } else
282 getMachineOpValue(Inst, Op2, Fixups, SubtargetInfo);
283
284 return Encoding;
285 }
286
287 unsigned LanaiMCCodeEmitter::getBranchTargetOpValue(
288 const MCInst &Inst, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
289 const MCSubtargetInfo &SubtargetInfo) const {
290 const MCOperand &MCOp = Inst.getOperand(OpNo);
291 if (MCOp.isReg() || MCOp.isImm())
292 return getMachineOpValue(Inst, MCOp, Fixups, SubtargetInfo);
293
294 Fixups.push_back(MCFixup::create(
295 0, MCOp.getExpr(), static_cast<MCFixupKind>(Lanai::FIXUP_LANAI_25)));
296
297 return 0;
298 }
299
300 #include "LanaiGenMCCodeEmitter.inc"
301 } // namespace
302 } // namespace llvm
303
304 llvm::MCCodeEmitter *
305 llvm::createLanaiMCCodeEmitter(const MCInstrInfo &InstrInfo,
306 const MCRegisterInfo & /*MRI*/,
307 MCContext &context) {
308 return new LanaiMCCodeEmitter(InstrInfo, context);
309 }