Mercurial > hg > CbC > CbC_llvm

comparison lib/Target/MSP430/MSP430InstrInfo.h @ 120:1172e4bd9c6f

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents afa8332a0e37
children 803732b1fca8
comparison
equal deleted inserted replaced
101:34baf5011add 120:1172e4bd9c6f
50 /// such, whenever a client has an instance of instruction info, it should 50 /// such, whenever a client has an instance of instruction info, it should
51 /// always be able to get register info as well (through this method). 51 /// always be able to get register info as well (through this method).
52 /// 52 ///
53 const TargetRegisterInfo &getRegisterInfo() const { return RI; } 53 const TargetRegisterInfo &getRegisterInfo() const { return RI; }
54 54
55 void copyPhysReg(MachineBasicBlock &MBB, 55 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
56 MachineBasicBlock::iterator I, DebugLoc DL, 56 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
57 unsigned DestReg, unsigned SrcReg,
58 bool KillSrc) const override; 57 bool KillSrc) const override;
59 58
60 void storeRegToStackSlot(MachineBasicBlock &MBB, 59 void storeRegToStackSlot(MachineBasicBlock &MBB,
61 MachineBasicBlock::iterator MI, 60 MachineBasicBlock::iterator MI,
62 unsigned SrcReg, bool isKill, 61 unsigned SrcReg, bool isKill,
67 MachineBasicBlock::iterator MI, 66 MachineBasicBlock::iterator MI,
68 unsigned DestReg, int FrameIdx, 67 unsigned DestReg, int FrameIdx,
69 const TargetRegisterClass *RC, 68 const TargetRegisterClass *RC,
70 const TargetRegisterInfo *TRI) const override; 69 const TargetRegisterInfo *TRI) const override;
71 70
72 unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 71 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
73 72
74 // Branch folding goodness 73 // Branch folding goodness
75 bool 74 bool
76 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 75 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
77 bool isUnpredicatedTerminator(const MachineInstr *MI) const override; 76 bool isUnpredicatedTerminator(const MachineInstr &MI) const override;
78 bool AnalyzeBranch(MachineBasicBlock &MBB, 77 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
79 MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, 78 MachineBasicBlock *&FBB,
80 SmallVectorImpl<MachineOperand> &Cond, 79 SmallVectorImpl<MachineOperand> &Cond,
81 bool AllowModify) const override; 80 bool AllowModify) const override;
82 81
83 unsigned RemoveBranch(MachineBasicBlock &MBB) const override; 82 unsigned removeBranch(MachineBasicBlock &MBB,
84 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 83 int *BytesRemoved = nullptr) const override;
84 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
85 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 85 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
86 DebugLoc DL) const override; 86 const DebugLoc &DL,
87 87 int *BytesAdded = nullptr) const override;
88 }; 88 };
89 89
90 } 90 }
91 91
92 #endif 92 #endif