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comparison lib/Target/Mips/MicroMips32r6InstrFormats.td @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents 7d135dc70f03
children 3a76565eade5
comparison
equal deleted inserted replaced
101:34baf5011add 120:1172e4bd9c6f
12 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===//
13 13
14 class MMR6Arch<string opstr> { 14 class MMR6Arch<string opstr> {
15 string Arch = "micromipsr6"; 15 string Arch = "micromipsr6";
16 string BaseOpcode = opstr; 16 string BaseOpcode = opstr;
17 string DecoderNamespace = "MicroMipsR6";
17 } 18 }
18 19
19 // Class used for microMIPS32r6 and microMIPS64r6 instructions. 20 // Class used for microMIPS32r6 and microMIPS64r6 instructions.
20 class MicroMipsR6Inst16 : PredicateControl { 21 class MicroMipsR6Inst16 : PredicateControl {
21 string DecoderNamespace = "MicroMipsR6"; 22 string DecoderNamespace = "MicroMipsR6";
22 let InsnPredicates = [HasMicroMips32r6]; 23 let InsnPredicates = [HasMicroMips32r6];
23 } 24 }
24 25
26 //===----------------------------------------------------------------------===//
27 //
28 // Disambiguators
29 //
30 //===----------------------------------------------------------------------===//
31 //
32 // Some encodings are ambiguous except by comparing field values.
33
34 class MMDecodeDisambiguatedBy<string Name> : DecodeDisambiguates<Name> {
35 string DecoderNamespace = "MicroMipsR6_Ambiguous";
36 }
37
38 //===----------------------------------------------------------------------===//
39 //
40 // Encoding Formats
41 //
42 //===----------------------------------------------------------------------===//
43
25 class BC16_FM_MM16R6 { 44 class BC16_FM_MM16R6 {
26 bits<10> offset; 45 bits<10> offset;
27 46
28 bits<16> Inst; 47 bits<16> Inst;
29 48
48 bits<16> Inst; 67 bits<16> Inst;
49 68
50 let Inst{15-10} = 0x11; 69 let Inst{15-10} = 0x11;
51 let Inst{9-5} = rs; 70 let Inst{9-5} = rs;
52 let Inst{4-0} = op; 71 let Inst{4-0} = op;
72 }
73
74 class POP35_BOVC_FM_MMR6<string instr_asm> : MipsR6Inst, MMR6Arch<instr_asm> {
75 bits<5> rt;
76 bits<5> rs;
77 bits<16> offset;
78
79 bits<32> Inst;
80
81 let Inst{31-26} = 0b011101;
82 let Inst{25-21} = rt;
83 let Inst{20-16} = rs;
84 let Inst{15-0} = offset;
85 }
86
87 class POP37_BNVC_FM_MMR6<string instr_asm> : MipsR6Inst, MMR6Arch<instr_asm> {
88 bits<5> rt;
89 bits<5> rs;
90 bits<16> offset;
91
92 bits<32> Inst;
93
94 let Inst{31-26} = 0b011111;
95 let Inst{25-21} = rt;
96 let Inst{20-16} = rs;
97 let Inst{15-0} = offset;
53 } 98 }
54 99
55 class POOL16C_JRCADDIUSP_FM_MM16R6<bits<5> op> { 100 class POOL16C_JRCADDIUSP_FM_MM16R6<bits<5> op> {
56 bits<5> imm; 101 bits<5> imm;
57 102
447 let Inst{25-21} = rt; 492 let Inst{25-21} = rt;
448 let Inst{20-16} = 0; 493 let Inst{20-16} = 0;
449 let Inst{15-0} = imm16; 494 let Inst{15-0} = imm16;
450 } 495 }
451 496
452 class CMP_BRANCH_1R_RT_OFF16_FM_MMR6<bits<6> funct> : MipsR6Inst { 497 class CMP_BRANCH_1R_RT_OFF16_FM_MMR6<string instr_asm, bits<6> funct>
498 : MMR6Arch<instr_asm>, MipsR6Inst {
453 bits<5> rt; 499 bits<5> rt;
454 bits<16> offset; 500 bits<16> offset;
455 501
456 bits<32> Inst; 502 bits<32> Inst;
457 503
459 let Inst{25-21} = rt; 505 let Inst{25-21} = rt;
460 let Inst{20-16} = 0b00000; 506 let Inst{20-16} = 0b00000;
461 let Inst{15-0} = offset; 507 let Inst{15-0} = offset;
462 } 508 }
463 509
464 class CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<bits<6> funct> : MipsR6Inst { 510 class CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<string instr_asm, bits<6> funct>
511 : MMR6Arch<instr_asm>, MipsR6Inst {
465 bits<5> rt; 512 bits<5> rt;
466 bits<16> offset; 513 bits<16> offset;
467 514
468 bits<32> Inst; 515 bits<32> Inst;
469 516
470 let Inst{31-26} = funct; 517 let Inst{31-26} = funct;
471 let Inst{25-21} = rt; 518 let Inst{25-21} = rt;
472 let Inst{20-16} = rt; 519 let Inst{20-16} = rt;
473 let Inst{15-0} = offset; 520 let Inst{15-0} = offset;
521 }
522
523 class POOL32A_JALRC_FM_MMR6<string instr_asm, bits<10> funct>
524 : MipsR6Inst, MMR6Arch<instr_asm> {
525 bits<5> rt;
526 bits<5> rs;
527
528 bits<32> Inst;
529
530 let Inst{31-26} = 0;
531 let Inst{25-21} = rt;
532 let Inst{20-16} = rs;
533 let Inst{15-6} = funct;
534 let Inst{5-0} = 0b111100;
535 }
536
537 class POOL32A_EXT_INS_FM_MMR6<string instr_asm, bits<6> funct>
538 : MMR6Arch<instr_asm>, MipsR6Inst {
539 bits<5> rt;
540 bits<5> rs;
541 bits<5> size;
542 bits<5> pos;
543
544 bits<32> Inst;
545
546 let Inst{31-26} = 0;
547 let Inst{25-21} = rt;
548 let Inst{20-16} = rs;
549 let Inst{15-11} = size;
550 let Inst{10-6} = pos;
551 let Inst{5-0} = funct;
474 } 552 }
475 553
476 class POOL32A_ERET_FM_MMR6<string instr_asm, bits<10> funct> 554 class POOL32A_ERET_FM_MMR6<string instr_asm, bits<10> funct>
477 : MMR6Arch<instr_asm> { 555 : MMR6Arch<instr_asm> {
478 bits<32> Inst; 556 bits<32> Inst;
749 let Inst{9-7} = rt; 827 let Inst{9-7} = rt;
750 let Inst{6-4} = rs; 828 let Inst{6-4} = rs;
751 let Inst{3-0} = 0b0000; 829 let Inst{3-0} = 0b0000;
752 } 830 }
753 831
754 class POOL16C_OR16_XOR16_FM_MMR6<bits<4> op> { 832 class POOL16C_OR16_XOR16_FM_MMR6<bits<4> op> : MicroMipsR6Inst16 {
755 bits<3> rt; 833 bits<3> rt;
756 bits<3> rs; 834 bits<3> rs;
757 835
758 bits<16> Inst; 836 bits<16> Inst;
759 837
858 let Inst{20-16} = fd; 936 let Inst{20-16} = fd;
859 let Inst{15-11} = 0b00000; 937 let Inst{15-11} = 0b00000;
860 let Inst{10-9} = fmt; 938 let Inst{10-9} = fmt;
861 let Inst{8-0} = funct; 939 let Inst{8-0} = funct;
862 } 940 }
941
942 class POOL32A_TLBINV_FM_MMR6<string instr_asm, bits<10> funct>
943 : MMR6Arch<instr_asm>, MipsR6Inst {
944 bits<32> Inst;
945
946 let Inst{31-26} = 0x0;
947 let Inst{25-16} = 0x0;
948 let Inst{15-6} = funct;
949 let Inst{5-0} = 0b111100;
950 }
951
952 class POOL32A_MFTC0_FM_MMR6<string instr_asm, bits<5> funct, bits<6> opcode>
953 : MMR6Arch<instr_asm>, MipsR6Inst {
954 bits<5> rt;
955 bits<5> rs;
956 bits<3> sel;
957
958 bits<32> Inst;
959
960 let Inst{31-26} = 0b000000;
961 let Inst{25-21} = rt;
962 let Inst{20-16} = rs;
963 let Inst{15-14} = 0;
964 let Inst{13-11} = sel;
965 let Inst{10-6} = funct;
966 let Inst{5-0} = opcode;
967 }
968
969 class POOL32F_MFTC1_FM_MMR6<string instr_asm, bits<8> funct>
970 : MMR6Arch<instr_asm> {
971 bits<5> rt;
972 bits<5> fs;
973
974 bits<32> Inst;
975
976 let Inst{31-26} = 0b010101;
977 let Inst{25-21} = rt;
978 let Inst{20-16} = fs;
979 let Inst{15-14} = 0;
980 let Inst{13-6} = funct;
981 let Inst{5-0} = 0b111011;
982 }
983
984 class POOL32A_MFTC2_FM_MMR6<string instr_asm, bits<10> funct>
985 : MMR6Arch<instr_asm>, MipsR6Inst {
986 bits<5> rt;
987 bits<5> impl;
988
989 bits<32> Inst;
990
991 let Inst{31-26} = 0b000000;
992 let Inst{25-21} = rt;
993 let Inst{20-16} = impl;
994 let Inst{15-6} = funct;
995 let Inst{5-0} = 0b111100;
996 }
997
998 class CMP_BRANCH_2R_OFF16_FM_MMR6<string opstr, bits<6> funct>
999 : MipsR6Inst, MMR6Arch<opstr> {
1000 bits<5> rt;
1001 bits<5> rs;
1002 bits<16> offset;
1003
1004 bits<32> Inst;
1005
1006 let Inst{31-26} = funct;
1007 let Inst{25-21} = rt;
1008 let Inst{20-16} = rs;
1009 let Inst{15-0} = offset;
1010 }
1011
1012 class POOL32A_DVPEVP_FM_MMR6<string instr_asm, bits<10> funct>
1013 : MMR6Arch<instr_asm>, MipsR6Inst {
1014 bits<5> rs;
1015
1016 bits<32> Inst;
1017
1018 let Inst{31-26} = 0b000000;
1019 let Inst{25-21} = 0b00000;
1020 let Inst{20-16} = rs;
1021 let Inst{15-6} = funct;
1022 let Inst{5-0} = 0b111100;
1023 }
1024
1025 class POOL32B_LWP_SWP_FM_MMR6<bits<4> funct> : MipsR6Inst {
1026 bits<5> rd;
1027 bits<21> addr;
1028 bits<5> base = addr{20-16};
1029 bits<12> offset = addr{11-0};
1030
1031 bits<32> Inst;
1032
1033 let Inst{31-26} = 0x8;
1034 let Inst{25-21} = rd;
1035 let Inst{20-16} = base;
1036 let Inst{15-12} = funct;
1037 let Inst{11-0} = offset;
1038 }
1039
1040 class CMP_BRANCH_OFF21_FM_MMR6<string opstr, bits<6> funct> : MipsR6Inst {
1041 bits<5> rs;
1042 bits<21> offset;
1043
1044 bits<32> Inst;
1045
1046 let Inst{31-26} = funct;
1047 let Inst{25-21} = rs;
1048 let Inst{20-0} = offset;
1049 }
1050
1051 class POOL32I_BRANCH_COP_1_2_FM_MMR6<string instr_asm, bits<5> funct>
1052 : MMR6Arch<instr_asm> {
1053 bits<5> rt;
1054 bits<16> offset;
1055
1056 bits<32> Inst;
1057
1058 let Inst{31-26} = 0b010000;
1059 let Inst{25-21} = funct;
1060 let Inst{20-16} = rt;
1061 let Inst{15-0} = offset;
1062 }
1063
1064 class LDWC1_SDWC1_FM_MMR6<string instr_asm, bits<6> funct>
1065 : MMR6Arch<instr_asm> {
1066 bits<5> ft;
1067 bits<21> addr;
1068 bits<5> base = addr{20-16};
1069 bits<16> offset = addr{15-0};
1070
1071 bits<32> Inst;
1072
1073 let Inst{31-26} = funct;
1074 let Inst{25-21} = ft;
1075 let Inst{20-16} = base;
1076 let Inst{15-0} = offset;
1077 }
1078
1079 class POOL32B_LDWC2_SDWC2_FM_MMR6<string instr_asm, bits<4> funct>
1080 : MMR6Arch<instr_asm>, MipsR6Inst {
1081 bits<5> rt;
1082 bits<21> addr;
1083 bits<5> base = addr{20-16};
1084 bits<11> offset = addr{10-0};
1085
1086 bits<32> Inst;
1087
1088 let Inst{31-26} = 0b001000;
1089 let Inst{25-21} = rt;
1090 let Inst{20-16} = base;
1091 let Inst{15-12} = funct;
1092 let Inst{11} = 0;
1093 let Inst{10-0} = offset;
1094 }