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comparison lib/Target/Mips/Mips16ISelLowering.cpp @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents 7d135dc70f03
children 3a76565eade5
comparison
equal deleted inserted replaced
101:34baf5011add 120:1172e4bd9c6f
14 #include "MCTargetDesc/MipsBaseInfo.h" 14 #include "MCTargetDesc/MipsBaseInfo.h"
15 #include "Mips16HardFloatInfo.h" 15 #include "Mips16HardFloatInfo.h"
16 #include "MipsMachineFunction.h" 16 #include "MipsMachineFunction.h"
17 #include "MipsRegisterInfo.h" 17 #include "MipsRegisterInfo.h"
18 #include "MipsTargetMachine.h" 18 #include "MipsTargetMachine.h"
19 #include "llvm/ADT/StringRef.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h" 19 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/Support/CommandLine.h" 20 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Target/TargetInstrInfo.h" 21 #include "llvm/Target/TargetInstrInfo.h"
23 #include <string>
24 22
25 using namespace llvm; 23 using namespace llvm;
26 24
27 #define DEBUG_TYPE "mips-lower" 25 #define DEBUG_TYPE "mips-lower"
28 26
165 bool *Fast) const { 163 bool *Fast) const {
166 return false; 164 return false;
167 } 165 }
168 166
169 MachineBasicBlock * 167 MachineBasicBlock *
170 Mips16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 168 Mips16TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
171 MachineBasicBlock *BB) const { 169 MachineBasicBlock *BB) const {
172 switch (MI->getOpcode()) { 170 switch (MI.getOpcode()) {
173 default: 171 default:
174 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB); 172 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
175 case Mips::SelBeqZ: 173 case Mips::SelBeqZ:
176 return emitSel16(Mips::BeqzRxImm16, MI, BB); 174 return emitSel16(Mips::BeqzRxImm16, MI, BB);
177 case Mips::SelBneZ: 175 case Mips::SelBneZ:
517 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, 515 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
518 InternalLinkage, IsCallReloc, CLI, Callee, 516 InternalLinkage, IsCallReloc, CLI, Callee,
519 Chain); 517 Chain);
520 } 518 }
521 519
522 MachineBasicBlock *Mips16TargetLowering:: 520 MachineBasicBlock *
523 emitSel16(unsigned Opc, MachineInstr *MI, MachineBasicBlock *BB) const { 521 Mips16TargetLowering::emitSel16(unsigned Opc, MachineInstr &MI,
522 MachineBasicBlock *BB) const {
524 if (DontExpandCondPseudos16) 523 if (DontExpandCondPseudos16)
525 return BB; 524 return BB;
526 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 525 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
527 DebugLoc DL = MI->getDebugLoc(); 526 DebugLoc DL = MI.getDebugLoc();
528 // To "insert" a SELECT_CC instruction, we actually have to insert the 527 // To "insert" a SELECT_CC instruction, we actually have to insert the
529 // diamond control-flow pattern. The incoming instruction knows the 528 // diamond control-flow pattern. The incoming instruction knows the
530 // destination vreg to set, the condition code register to branch on, the 529 // destination vreg to set, the condition code register to branch on, the
531 // true/false values to select between, and a branch opcode to use. 530 // true/false values to select between, and a branch opcode to use.
532 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 531 const BasicBlock *LLVM_BB = BB->getBasicBlock();
552 551
553 // Next, add the true and fallthrough blocks as its successors. 552 // Next, add the true and fallthrough blocks as its successors.
554 BB->addSuccessor(copy0MBB); 553 BB->addSuccessor(copy0MBB);
555 BB->addSuccessor(sinkMBB); 554 BB->addSuccessor(sinkMBB);
556 555
557 BuildMI(BB, DL, TII->get(Opc)).addReg(MI->getOperand(3).getReg()) 556 BuildMI(BB, DL, TII->get(Opc))
558 .addMBB(sinkMBB); 557 .addReg(MI.getOperand(3).getReg())
558 .addMBB(sinkMBB);
559 559
560 // copy0MBB: 560 // copy0MBB:
561 // %FalseValue = ... 561 // %FalseValue = ...
562 // # fallthrough to sinkMBB 562 // # fallthrough to sinkMBB
563 BB = copy0MBB; 563 BB = copy0MBB;
568 // sinkMBB: 568 // sinkMBB:
569 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 569 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
570 // ... 570 // ...
571 BB = sinkMBB; 571 BB = sinkMBB;
572 572
573 BuildMI(*BB, BB->begin(), DL, 573 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
574 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 574 .addReg(MI.getOperand(1).getReg())
575 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB) 575 .addMBB(thisMBB)
576 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB); 576 .addReg(MI.getOperand(2).getReg())
577 577 .addMBB(copy0MBB);
578 MI->eraseFromParent(); // The pseudo instruction is gone now. 578
579 MI.eraseFromParent(); // The pseudo instruction is gone now.
579 return BB; 580 return BB;
580 } 581 }
581 582
582 MachineBasicBlock * 583 MachineBasicBlock *
583 Mips16TargetLowering::emitSelT16(unsigned Opc1, unsigned Opc2, MachineInstr *MI, 584 Mips16TargetLowering::emitSelT16(unsigned Opc1, unsigned Opc2, MachineInstr &MI,
584 MachineBasicBlock *BB) const { 585 MachineBasicBlock *BB) const {
585 if (DontExpandCondPseudos16) 586 if (DontExpandCondPseudos16)
586 return BB; 587 return BB;
587 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 588 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
588 DebugLoc DL = MI->getDebugLoc(); 589 DebugLoc DL = MI.getDebugLoc();
589 // To "insert" a SELECT_CC instruction, we actually have to insert the 590 // To "insert" a SELECT_CC instruction, we actually have to insert the
590 // diamond control-flow pattern. The incoming instruction knows the 591 // diamond control-flow pattern. The incoming instruction knows the
591 // destination vreg to set, the condition code register to branch on, the 592 // destination vreg to set, the condition code register to branch on, the
592 // true/false values to select between, and a branch opcode to use. 593 // true/false values to select between, and a branch opcode to use.
593 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 594 const BasicBlock *LLVM_BB = BB->getBasicBlock();
613 614
614 // Next, add the true and fallthrough blocks as its successors. 615 // Next, add the true and fallthrough blocks as its successors.
615 BB->addSuccessor(copy0MBB); 616 BB->addSuccessor(copy0MBB);
616 BB->addSuccessor(sinkMBB); 617 BB->addSuccessor(sinkMBB);
617 618
618 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg()) 619 BuildMI(BB, DL, TII->get(Opc2))
619 .addReg(MI->getOperand(4).getReg()); 620 .addReg(MI.getOperand(3).getReg())
621 .addReg(MI.getOperand(4).getReg());
620 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB); 622 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
621 623
622 // copy0MBB: 624 // copy0MBB:
623 // %FalseValue = ... 625 // %FalseValue = ...
624 // # fallthrough to sinkMBB 626 // # fallthrough to sinkMBB
630 // sinkMBB: 632 // sinkMBB:
631 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 633 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
632 // ... 634 // ...
633 BB = sinkMBB; 635 BB = sinkMBB;
634 636
635 BuildMI(*BB, BB->begin(), DL, 637 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
636 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 638 .addReg(MI.getOperand(1).getReg())
637 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB) 639 .addMBB(thisMBB)
638 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB); 640 .addReg(MI.getOperand(2).getReg())
639 641 .addMBB(copy0MBB);
640 MI->eraseFromParent(); // The pseudo instruction is gone now. 642
643 MI.eraseFromParent(); // The pseudo instruction is gone now.
641 return BB; 644 return BB;
642 645
643 } 646 }
644 647
645 MachineBasicBlock * 648 MachineBasicBlock *
646 Mips16TargetLowering::emitSeliT16(unsigned Opc1, unsigned Opc2, 649 Mips16TargetLowering::emitSeliT16(unsigned Opc1, unsigned Opc2,
647 MachineInstr *MI, 650 MachineInstr &MI,
648 MachineBasicBlock *BB) const { 651 MachineBasicBlock *BB) const {
649 if (DontExpandCondPseudos16) 652 if (DontExpandCondPseudos16)
650 return BB; 653 return BB;
651 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 654 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
652 DebugLoc DL = MI->getDebugLoc(); 655 DebugLoc DL = MI.getDebugLoc();
653 // To "insert" a SELECT_CC instruction, we actually have to insert the 656 // To "insert" a SELECT_CC instruction, we actually have to insert the
654 // diamond control-flow pattern. The incoming instruction knows the 657 // diamond control-flow pattern. The incoming instruction knows the
655 // destination vreg to set, the condition code register to branch on, the 658 // destination vreg to set, the condition code register to branch on, the
656 // true/false values to select between, and a branch opcode to use. 659 // true/false values to select between, and a branch opcode to use.
657 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 660 const BasicBlock *LLVM_BB = BB->getBasicBlock();
677 680
678 // Next, add the true and fallthrough blocks as its successors. 681 // Next, add the true and fallthrough blocks as its successors.
679 BB->addSuccessor(copy0MBB); 682 BB->addSuccessor(copy0MBB);
680 BB->addSuccessor(sinkMBB); 683 BB->addSuccessor(sinkMBB);
681 684
682 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg()) 685 BuildMI(BB, DL, TII->get(Opc2))
683 .addImm(MI->getOperand(4).getImm()); 686 .addReg(MI.getOperand(3).getReg())
687 .addImm(MI.getOperand(4).getImm());
684 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB); 688 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
685 689
686 // copy0MBB: 690 // copy0MBB:
687 // %FalseValue = ... 691 // %FalseValue = ...
688 // # fallthrough to sinkMBB 692 // # fallthrough to sinkMBB
694 // sinkMBB: 698 // sinkMBB:
695 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 699 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
696 // ... 700 // ...
697 BB = sinkMBB; 701 BB = sinkMBB;
698 702
699 BuildMI(*BB, BB->begin(), DL, 703 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
700 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 704 .addReg(MI.getOperand(1).getReg())
701 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB) 705 .addMBB(thisMBB)
702 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB); 706 .addReg(MI.getOperand(2).getReg())
703 707 .addMBB(copy0MBB);
704 MI->eraseFromParent(); // The pseudo instruction is gone now. 708
709 MI.eraseFromParent(); // The pseudo instruction is gone now.
705 return BB; 710 return BB;
706 711
707 } 712 }
708 713
709 MachineBasicBlock * 714 MachineBasicBlock *
710 Mips16TargetLowering::emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc, 715 Mips16TargetLowering::emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc,
711 MachineInstr *MI, 716 MachineInstr &MI,
712 MachineBasicBlock *BB) const { 717 MachineBasicBlock *BB) const {
713 if (DontExpandCondPseudos16) 718 if (DontExpandCondPseudos16)
714 return BB; 719 return BB;
715 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 720 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
716 unsigned regX = MI->getOperand(0).getReg(); 721 unsigned regX = MI.getOperand(0).getReg();
717 unsigned regY = MI->getOperand(1).getReg(); 722 unsigned regY = MI.getOperand(1).getReg();
718 MachineBasicBlock *target = MI->getOperand(2).getMBB(); 723 MachineBasicBlock *target = MI.getOperand(2).getMBB();
719 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX) 724 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(CmpOpc))
720 .addReg(regY); 725 .addReg(regX)
721 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target); 726 .addReg(regY);
722 MI->eraseFromParent(); // The pseudo instruction is gone now. 727 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(BtOpc)).addMBB(target);
728 MI.eraseFromParent(); // The pseudo instruction is gone now.
723 return BB; 729 return BB;
724 } 730 }
725 731
726 MachineBasicBlock *Mips16TargetLowering::emitFEXT_T8I8I16_ins( 732 MachineBasicBlock *Mips16TargetLowering::emitFEXT_T8I8I16_ins(
727 unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc, bool ImmSigned, 733 unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc, bool ImmSigned,
728 MachineInstr *MI, MachineBasicBlock *BB) const { 734 MachineInstr &MI, MachineBasicBlock *BB) const {
729 if (DontExpandCondPseudos16) 735 if (DontExpandCondPseudos16)
730 return BB; 736 return BB;
731 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 737 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
732 unsigned regX = MI->getOperand(0).getReg(); 738 unsigned regX = MI.getOperand(0).getReg();
733 int64_t imm = MI->getOperand(1).getImm(); 739 int64_t imm = MI.getOperand(1).getImm();
734 MachineBasicBlock *target = MI->getOperand(2).getMBB(); 740 MachineBasicBlock *target = MI.getOperand(2).getMBB();
735 unsigned CmpOpc; 741 unsigned CmpOpc;
736 if (isUInt<8>(imm)) 742 if (isUInt<8>(imm))
737 CmpOpc = CmpiOpc; 743 CmpOpc = CmpiOpc;
738 else if ((!ImmSigned && isUInt<16>(imm)) || 744 else if ((!ImmSigned && isUInt<16>(imm)) ||
739 (ImmSigned && isInt<16>(imm))) 745 (ImmSigned && isInt<16>(imm)))
740 CmpOpc = CmpiXOpc; 746 CmpOpc = CmpiXOpc;
741 else 747 else
742 llvm_unreachable("immediate field not usable"); 748 llvm_unreachable("immediate field not usable");
743 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX) 749 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addImm(imm);
744 .addImm(imm); 750 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(BtOpc)).addMBB(target);
745 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target); 751 MI.eraseFromParent(); // The pseudo instruction is gone now.
746 MI->eraseFromParent(); // The pseudo instruction is gone now.
747 return BB; 752 return BB;
748 } 753 }
749 754
750 static unsigned Mips16WhichOp8uOr16simm 755 static unsigned Mips16WhichOp8uOr16simm
751 (unsigned shortOp, unsigned longOp, int64_t Imm) { 756 (unsigned shortOp, unsigned longOp, int64_t Imm) {
756 else 761 else
757 llvm_unreachable("immediate field not usable"); 762 llvm_unreachable("immediate field not usable");
758 } 763 }
759 764
760 MachineBasicBlock * 765 MachineBasicBlock *
761 Mips16TargetLowering::emitFEXT_CCRX16_ins(unsigned SltOpc, MachineInstr *MI, 766 Mips16TargetLowering::emitFEXT_CCRX16_ins(unsigned SltOpc, MachineInstr &MI,
762 MachineBasicBlock *BB) const { 767 MachineBasicBlock *BB) const {
763 if (DontExpandCondPseudos16) 768 if (DontExpandCondPseudos16)
764 return BB; 769 return BB;
765 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 770 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
766 unsigned CC = MI->getOperand(0).getReg(); 771 unsigned CC = MI.getOperand(0).getReg();
767 unsigned regX = MI->getOperand(1).getReg(); 772 unsigned regX = MI.getOperand(1).getReg();
768 unsigned regY = MI->getOperand(2).getReg(); 773 unsigned regY = MI.getOperand(2).getReg();
769 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(SltOpc)).addReg(regX).addReg( 774 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(SltOpc))
770 regY); 775 .addReg(regX)
771 BuildMI(*BB, MI, MI->getDebugLoc(), 776 .addReg(regY);
772 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8); 777 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(Mips::MoveR3216), CC)
773 MI->eraseFromParent(); // The pseudo instruction is gone now. 778 .addReg(Mips::T8);
779 MI.eraseFromParent(); // The pseudo instruction is gone now.
774 return BB; 780 return BB;
775 } 781 }
776 782
777 MachineBasicBlock * 783 MachineBasicBlock *
778 Mips16TargetLowering::emitFEXT_CCRXI16_ins(unsigned SltiOpc, unsigned SltiXOpc, 784 Mips16TargetLowering::emitFEXT_CCRXI16_ins(unsigned SltiOpc, unsigned SltiXOpc,
779 MachineInstr *MI, 785 MachineInstr &MI,
780 MachineBasicBlock *BB) const { 786 MachineBasicBlock *BB) const {
781 if (DontExpandCondPseudos16) 787 if (DontExpandCondPseudos16)
782 return BB; 788 return BB;
783 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 789 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
784 unsigned CC = MI->getOperand(0).getReg(); 790 unsigned CC = MI.getOperand(0).getReg();
785 unsigned regX = MI->getOperand(1).getReg(); 791 unsigned regX = MI.getOperand(1).getReg();
786 int64_t Imm = MI->getOperand(2).getImm(); 792 int64_t Imm = MI.getOperand(2).getImm();
787 unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm); 793 unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm);
788 BuildMI(*BB, MI, MI->getDebugLoc(), 794 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(SltOpc)).addReg(regX).addImm(Imm);
789 TII->get(SltOpc)).addReg(regX).addImm(Imm); 795 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(Mips::MoveR3216), CC)
790 BuildMI(*BB, MI, MI->getDebugLoc(), 796 .addReg(Mips::T8);
791 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8); 797 MI.eraseFromParent(); // The pseudo instruction is gone now.
792 MI->eraseFromParent(); // The pseudo instruction is gone now.
793 return BB; 798 return BB;
794 799
795 } 800 }