CbC/CbC_llvm: lib/Target/Mips/MipsISelLowering.cpp comparison

comparison lib/Target/Mips/MipsISelLowering.cpp @ 120:1172e4bd9c6f

update 4.0.0

author	mir3636
date	Fri, 25 Nov 2016 19:14:25 +0900
parents	7d135dc70f03
children	803732b1fca8

comparison

equal deleted inserted replaced

-:34baf5011add
+:1172e4bd9c6f
 // we don't want this, since the fpcmp result goes to a flag register,
 // which is used implicitly by brcond and select operations.
 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
 // Mips Custom Operations
-setOperationAction(ISD::BR_JT,              MVT::Other, Custom);
+setOperationAction(ISD::BR_JT,              MVT::Other, Expand);
 setOperationAction(ISD::GlobalAddress,      MVT::i32,   Custom);
 setOperationAction(ISD::BlockAddress,       MVT::i32,   Custom);
 setOperationAction(ISD::GlobalTLSAddress,   MVT::i32,   Custom);
 setOperationAction(ISD::JumpTable,          MVT::i32,   Custom);
 setOperationAction(ISD::ConstantPool,       MVT::i32,   Custom);
 setOperationAction(ISD::SHL_PARTS,          MVT::i32,   Custom);
 setOperationAction(ISD::SRA_PARTS,          MVT::i32,   Custom);
 setOperationAction(ISD::SRL_PARTS,          MVT::i32,   Custom);
 }
-setOperationAction(ISD::ADD,                MVT::i32,   Custom);
+setOperationAction(ISD::EH_DWARF_CFA,         MVT::i32,   Custom);
 if (Subtarget.isGP64bit())
-setOperationAction(ISD::ADD,                MVT::i64,   Custom);
+setOperationAction(ISD::EH_DWARF_CFA,       MVT::i64,   Custom);
 setOperationAction(ISD::SDIV, MVT::i32, Expand);
 setOperationAction(ISD::SREM, MVT::i32, Expand);
 setOperationAction(ISD::UDIV, MVT::i32, Expand);
 setOperationAction(ISD::UREM, MVT::i32, Expand);
 setOperationAction(ISD::CTPOP,           MVT::i32,   Expand);
 setOperationAction(ISD::CTPOP,           MVT::i64,   Expand);
 }
 setOperationAction(ISD::CTTZ,              MVT::i32,   Expand);
 setOperationAction(ISD::CTTZ,              MVT::i64,   Expand);
-setOperationAction(ISD::CTTZ_ZERO_UNDEF,   MVT::i32,   Expand);
-setOperationAction(ISD::CTTZ_ZERO_UNDEF,   MVT::i64,   Expand);
-setOperationAction(ISD::CTLZ_ZERO_UNDEF,   MVT::i32,   Expand);
-setOperationAction(ISD::CTLZ_ZERO_UNDEF,   MVT::i64,   Expand);
 setOperationAction(ISD::ROTL,              MVT::i32,   Expand);
 setOperationAction(ISD::ROTL,              MVT::i64,   Expand);
 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32,  Expand);
 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64,  Expand);
 if (!Subtarget.isGP64bit()) {
 setOperationAction(ISD::ATOMIC_LOAD,     MVT::i64,   Expand);
 setOperationAction(ISD::ATOMIC_STORE,    MVT::i64,   Expand);
 }
-setInsertFencesForAtomic(true);
 if (!Subtarget.hasMips32r2()) {
 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8,  Expand);
 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
 }
 setTargetDAGCombine(ISD::UDIVREM);
 setTargetDAGCombine(ISD::SELECT);
 setTargetDAGCombine(ISD::AND);
 setTargetDAGCombine(ISD::OR);
 setTargetDAGCombine(ISD::ADD);
+setTargetDAGCombine(ISD::AssertZext);
+if (ABI.IsO32()) {
+// These libcalls are not available in 32-bit.
+setLibcallName(RTLIB::SHL_I128, nullptr);
+setLibcallName(RTLIB::SRL_I128, nullptr);
+setLibcallName(RTLIB::SRA_I128, nullptr);
+}
 setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2);
 // The arguments on the stack are defined in terms of 4-byte slots on O32
 // and 8-byte slots on N32/N64.
 // Create a fast isel object.
 FastISel *
 MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
 const TargetLibraryInfo *libInfo) const {
-if (!funcInfo.MF->getTarget().Options.EnableFastISel)
+const MipsTargetMachine &TM =
-return TargetLowering::createFastISel(funcInfo, libInfo);
+static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget());
-return Mips::createFastISel(funcInfo, libInfo);
+// We support only the standard encoding [MIPS32,MIPS32R5] ISAs.
+bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() &&
+!Subtarget.hasMips32r6() && !Subtarget.inMips16Mode() &&
+!Subtarget.inMicroMipsMode();
+// Disable if we don't generate PIC or the ABI isn't O32.
+if (!TM.isPositionIndependent() || !TM.getABI().IsO32())
+UseFastISel = false;
+return UseFastISel ? Mips::createFastISel(funcInfo, libInfo) : nullptr;
 }
 EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
 EVT VT) const {
 if (!VT.isVector())
 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32));
 }
 // Creates and returns a CMovFPT/F node.
 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
-SDValue False, SDLoc DL) {
+SDValue False, const SDLoc &DL) {
 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
 SDLoc DL(N);
 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
 Add.getOperand(0));
 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
+}
+static SDValue performAssertZextCombine(SDNode *N, SelectionDAG &DAG,
+TargetLowering::DAGCombinerInfo &DCI,
+const MipsSubtarget &Subtarget) {
+SDValue N0 = N->getOperand(0);
+EVT NarrowerVT = cast<VTSDNode>(N->getOperand(1))->getVT();
+if (N0.getOpcode() != ISD::TRUNCATE)
+return SDValue();
+if (N0.getOperand(0).getOpcode() != ISD::AssertZext)
+return SDValue();
+// fold (AssertZext (trunc (AssertZext x))) -> (trunc (AssertZext x))
+// if the type of the extension of the innermost AssertZext node is
+// smaller from that of the outermost node, eg:
+// (AssertZext:i32 (trunc:i32 (AssertZext:i64 X, i32)), i8)
+//   -> (trunc:i32 (AssertZext X, i8))
+SDValue WiderAssertZext = N0.getOperand(0);
+EVT WiderVT = cast<VTSDNode>(WiderAssertZext->getOperand(1))->getVT();
+if (NarrowerVT.bitsLT(WiderVT)) {
+SDValue NewAssertZext = DAG.getNode(
+ISD::AssertZext, SDLoc(N), WiderAssertZext.getValueType(),
+WiderAssertZext.getOperand(0), DAG.getValueType(NarrowerVT));
+return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0),
+NewAssertZext);
+}
+return SDValue();
 }
 SDValue  MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
 const {
 SelectionDAG &DAG = DCI.DAG;
 return performANDCombine(N, DAG, DCI, Subtarget);
 case ISD::OR:
 return performORCombine(N, DAG, DCI, Subtarget);
 case ISD::ADD:
 return performADDCombine(N, DAG, DCI, Subtarget);
+case ISD::AssertZext:
+return performAssertZextCombine(N, DAG, DCI, Subtarget);
 }
 return SDValue();
 }
 SDValue MipsTargetLowering::
 LowerOperation(SDValue Op, SelectionDAG &DAG) const
 {
 switch (Op.getOpcode())
 {
-case ISD::BR_JT:              return lowerBR_JT(Op, DAG);
 case ISD::BRCOND:             return lowerBRCOND(Op, DAG);
 case ISD::ConstantPool:       return lowerConstantPool(Op, DAG);
 case ISD::GlobalAddress:      return lowerGlobalAddress(Op, DAG);
 case ISD::BlockAddress:       return lowerBlockAddress(Op, DAG);
 case ISD::GlobalTLSAddress:   return lowerGlobalTLSAddress(Op, DAG);
 case ISD::SHL_PARTS:          return lowerShiftLeftParts(Op, DAG);
 case ISD::SRA_PARTS:          return lowerShiftRightParts(Op, DAG, true);
 case ISD::SRL_PARTS:          return lowerShiftRightParts(Op, DAG, false);
 case ISD::LOAD:               return lowerLOAD(Op, DAG);
 case ISD::STORE:              return lowerSTORE(Op, DAG);
-case ISD::ADD:                return lowerADD(Op, DAG);
+case ISD::EH_DWARF_CFA:       return lowerEH_DWARF_CFA(Op, DAG);
 case ISD::FP_TO_SINT:         return lowerFP_TO_SINT(Op, DAG);
 }
 return SDValue();
 }
 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
 MF.getRegInfo().addLiveIn(PReg, VReg);
 return VReg;
 }
-static MachineBasicBlock *insertDivByZeroTrap(MachineInstr *MI,
+static MachineBasicBlock *insertDivByZeroTrap(MachineInstr &MI,
 MachineBasicBlock &MBB,
 const TargetInstrInfo &TII,
-bool Is64Bit) {
+bool Is64Bit, bool IsMicroMips) {
 if (NoZeroDivCheck)
 return &MBB;
 // Insert instruction "teq $divisor_reg, $zero, 7".
 MachineBasicBlock::iterator I(MI);
 MachineInstrBuilder MIB;
-MachineOperand &Divisor = MI->getOperand(2);
+MachineOperand &Divisor = MI.getOperand(2);
-MIB = BuildMI(MBB, std::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ))
+MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(),
-.addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
+TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ))
-.addReg(Mips::ZERO).addImm(7);
+.addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
+.addReg(Mips::ZERO)
+.addImm(7);
 // Use the 32-bit sub-register if this is a 64-bit division.
 if (Is64Bit)
 MIB->getOperand(0).setSubReg(Mips::sub_32);
 return &MBB;
 }
 MachineBasicBlock *
-MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
+MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
 MachineBasicBlock *BB) const {
-switch (MI->getOpcode()) {
+switch (MI.getOpcode()) {
 default:
 llvm_unreachable("Unexpected instr type to insert");
 case Mips::ATOMIC_LOAD_ADD_I8:
 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
 case Mips::ATOMIC_LOAD_ADD_I16:
 case Mips::PseudoUDIV:
 case Mips::DIV:
 case Mips::DIVU:
 case Mips::MOD:
 case Mips::MODU:
-return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false);
+return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false,
+false);
+case Mips::SDIV_MM_Pseudo:
+case Mips::UDIV_MM_Pseudo:
+case Mips::SDIV_MM:
+case Mips::UDIV_MM:
+case Mips::DIV_MMR6:
+case Mips::DIVU_MMR6:
+case Mips::MOD_MMR6:
+case Mips::MODU_MMR6:
+return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true);
 case Mips::PseudoDSDIV:
 case Mips::PseudoDUDIV:
 case Mips::DDIV:
 case Mips::DDIVU:
 case Mips::DMOD:
 case Mips::DMODU:
-return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true);
+return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false);
+case Mips::DDIV_MM64R6:
+case Mips::DDIVU_MM64R6:
+case Mips::DMOD_MM64R6:
+case Mips::DMODU_MM64R6:
+return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, true);
 case Mips::SEL_D:
+case Mips::SEL_D_MMR6:
 return emitSEL_D(MI, BB);
 case Mips::PseudoSELECT_I:
 case Mips::PseudoSELECT_I64:
 case Mips::PseudoSELECT_S:
 }
 }
 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
-MachineBasicBlock *
+MachineBasicBlock *MipsTargetLowering::emitAtomicBinary(MachineInstr &MI,
-MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
+MachineBasicBlock *BB,
-unsigned Size, unsigned BinOpcode,
+unsigned Size,
-bool Nand) const {
+unsigned BinOpcode,
+bool Nand) const {
 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
 MachineFunction *MF = BB->getParent();
 MachineRegisterInfo &RegInfo = MF->getRegInfo();
 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
-DebugLoc DL = MI->getDebugLoc();
+const bool ArePtrs64bit = ABI.ArePtrs64bit();
+DebugLoc DL = MI.getDebugLoc();
 unsigned LL, SC, AND, NOR, ZERO, BEQ;
 if (Size == 4) {
 if (isMicroMips) {
 LL = Mips::LL_MM;
 SC = Mips::SC_MM;
 } else {
-LL = Subtarget.hasMips32r6() ? Mips::LL_R6 : Mips::LL;
+LL = Subtarget.hasMips32r6()
-SC = Subtarget.hasMips32r6() ? Mips::SC_R6 : Mips::SC;
+? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
+: (ArePtrs64bit ? Mips::LL64 : Mips::LL);
+SC = Subtarget.hasMips32r6()
+? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
+: (ArePtrs64bit ? Mips::SC64 : Mips::SC);
 }
 AND = Mips::AND;
 NOR = Mips::NOR;
 ZERO = Mips::ZERO;
 BEQ = Mips::BEQ;
 } else {
 NOR = Mips::NOR64;
 ZERO = Mips::ZERO_64;
 BEQ = Mips::BEQ64;
 }
-unsigned OldVal = MI->getOperand(0).getReg();
+unsigned OldVal = MI.getOperand(0).getReg();
-unsigned Ptr = MI->getOperand(1).getReg();
+unsigned Ptr = MI.getOperand(1).getReg();
-unsigned Incr = MI->getOperand(2).getReg();
+unsigned Incr = MI.getOperand(2).getReg();
 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
 unsigned AndRes = RegInfo.createVirtualRegister(RC);
 unsigned Success = RegInfo.createVirtualRegister(RC);
 StoreVal = Incr;
 }
 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
-MI->eraseFromParent(); // The instruction is gone now.
+MI.eraseFromParent(); // The instruction is gone now.
 return exitMBB;
 }
 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg(
-MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg,
+MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg,
 unsigned SrcReg) const {
 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
-DebugLoc DL = MI->getDebugLoc();
+const DebugLoc &DL = MI.getDebugLoc();
 if (Subtarget.hasMips32r2() && Size == 1) {
 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg);
 return BB;
 }
 return BB;
 }
 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
-MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
+MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
 bool Nand) const {
 assert((Size == 1 || Size == 2) &&
 "Unsupported size for EmitAtomicBinaryPartial.");
 MachineFunction *MF = BB->getParent();
 MachineRegisterInfo &RegInfo = MF->getRegInfo();
 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
+const bool ArePtrs64bit = ABI.ArePtrs64bit();
+const TargetRegisterClass *RCp =
+getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
-DebugLoc DL = MI->getDebugLoc();
+DebugLoc DL = MI.getDebugLoc();
-unsigned Dest = MI->getOperand(0).getReg();
+unsigned Dest = MI.getOperand(0).getReg();
-unsigned Ptr = MI->getOperand(1).getReg();
+unsigned Ptr = MI.getOperand(1).getReg();
-unsigned Incr = MI->getOperand(2).getReg();
+unsigned Incr = MI.getOperand(2).getReg();
-unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
+unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp);
 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
 unsigned Mask = RegInfo.createVirtualRegister(RC);
 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
 unsigned NewVal = RegInfo.createVirtualRegister(RC);
 unsigned OldVal = RegInfo.createVirtualRegister(RC);
 unsigned Incr2 = RegInfo.createVirtualRegister(RC);
-unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
+unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp);
 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
 unsigned AndRes = RegInfo.createVirtualRegister(RC);
 unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
 unsigned Success = RegInfo.createVirtualRegister(RC);
+unsigned LL, SC;
+if (isMicroMips) {
+LL = Mips::LL_MM;
+SC = Mips::SC_MM;
+} else {
+LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
+: (ArePtrs64bit ? Mips::LL64 : Mips::LL);
+SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
+: (ArePtrs64bit ? Mips::SC64 : Mips::SC);
+}
 // insert new blocks after the current block
 const BasicBlock *LLVM_BB = BB->getBasicBlock();
 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
 //    sll     mask,maskupper,shiftamt
 //    nor     mask2,$0,mask
 //    sll     incr2,incr,shiftamt
 int64_t MaskImm = (Size == 1) ? 255 : 65535;
-BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
+BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2)
-.addReg(Mips::ZERO).addImm(-4);
+.addReg(ABI.GetNullPtr()).addImm(-4);
-BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
+BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr)
 .addReg(Ptr).addReg(MaskLSB2);
-BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
+BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
+.addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
 if (Subtarget.isLittle()) {
 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
 } else {
 unsigned Off = RegInfo.createVirtualRegister(RC);
 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
 //   or      storeval,maskedoldval0,newval
 //   sc      success,storeval,0(alignedaddr)
 //   beq     success,$0,loopMBB
 BB = loopMBB;
-unsigned LL = isMicroMips ? Mips::LL_MM : Mips::LL;
 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
 if (Nand) {
 //  and andres, oldval, incr2
 //  nor binopres, $0, andres
 //  and newval, binopres, mask
 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
 .addReg(OldVal).addReg(Mask2);
 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
 .addReg(MaskedOldVal0).addReg(NewVal);
-unsigned SC = isMicroMips ? Mips::SC_MM : Mips::SC;
 BuildMI(BB, DL, TII->get(SC), Success)
 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
 BuildMI(BB, DL, TII->get(Mips::BEQ))
 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
 .addReg(OldVal).addReg(Mask);
 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
 .addReg(MaskedOldVal1).addReg(ShiftAmt);
 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
-MI->eraseFromParent(); // The instruction is gone now.
+MI.eraseFromParent(); // The instruction is gone now.
 return exitMBB;
 }
-MachineBasicBlock * MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
+MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI,
 MachineBasicBlock *BB,
 unsigned Size) const {
 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
 MachineFunction *MF = BB->getParent();
 MachineRegisterInfo &RegInfo = MF->getRegInfo();
 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
-DebugLoc DL = MI->getDebugLoc();
+const bool ArePtrs64bit = ABI.ArePtrs64bit();
+DebugLoc DL = MI.getDebugLoc();
 unsigned LL, SC, ZERO, BNE, BEQ;
 if (Size == 4) {
 if (isMicroMips) {
 LL = Mips::LL_MM;
 SC = Mips::SC_MM;
 } else {
-LL = Subtarget.hasMips32r6() ? Mips::LL_R6 : Mips::LL;
+LL = Subtarget.hasMips32r6()
-SC = Subtarget.hasMips32r6() ? Mips::SC_R6 : Mips::SC;
+? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
-}
+: (ArePtrs64bit ? Mips::LL64 : Mips::LL);
+SC = Subtarget.hasMips32r6()
+? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
+: (ArePtrs64bit ? Mips::SC64 : Mips::SC);
+}
 ZERO = Mips::ZERO;
 BNE = Mips::BNE;
 BEQ = Mips::BEQ;
 } else {
 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
 ZERO = Mips::ZERO_64;
 BNE = Mips::BNE64;
 BEQ = Mips::BEQ64;
 }
-unsigned Dest    = MI->getOperand(0).getReg();
+unsigned Dest = MI.getOperand(0).getReg();
-unsigned Ptr     = MI->getOperand(1).getReg();
+unsigned Ptr = MI.getOperand(1).getReg();
-unsigned OldVal  = MI->getOperand(2).getReg();
+unsigned OldVal = MI.getOperand(2).getReg();
-unsigned NewVal  = MI->getOperand(3).getReg();
+unsigned NewVal = MI.getOperand(3).getReg();
 unsigned Success = RegInfo.createVirtualRegister(RC);
 // insert new blocks after the current block
 const BasicBlock *LLVM_BB = BB->getBasicBlock();
 BuildMI(BB, DL, TII->get(SC), Success)
 .addReg(NewVal).addReg(Ptr).addImm(0);
 BuildMI(BB, DL, TII->get(BEQ))
 .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
-MI->eraseFromParent(); // The instruction is gone now.
+MI.eraseFromParent(); // The instruction is gone now.
 return exitMBB;
 }
-MachineBasicBlock *
+MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword(
-MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI,
+MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const {
-MachineBasicBlock *BB,
-unsigned Size) const {
 assert((Size == 1 || Size == 2) &&
 "Unsupported size for EmitAtomicCmpSwapPartial.");
 MachineFunction *MF = BB->getParent();
 MachineRegisterInfo &RegInfo = MF->getRegInfo();
 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
+const bool ArePtrs64bit = ABI.ArePtrs64bit();
+const TargetRegisterClass *RCp =
+getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
-DebugLoc DL = MI->getDebugLoc();
+DebugLoc DL = MI.getDebugLoc();
-unsigned Dest    = MI->getOperand(0).getReg();
+unsigned Dest = MI.getOperand(0).getReg();
-unsigned Ptr     = MI->getOperand(1).getReg();
+unsigned Ptr = MI.getOperand(1).getReg();
-unsigned CmpVal  = MI->getOperand(2).getReg();
+unsigned CmpVal = MI.getOperand(2).getReg();
-unsigned NewVal  = MI->getOperand(3).getReg();
+unsigned NewVal = MI.getOperand(3).getReg();
-unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
+unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp);
 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
 unsigned Mask = RegInfo.createVirtualRegister(RC);
 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
 unsigned OldVal = RegInfo.createVirtualRegister(RC);
 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
-unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
+unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp);
 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
 unsigned Success = RegInfo.createVirtualRegister(RC);
+unsigned LL, SC;
+if (isMicroMips) {
+LL = Mips::LL_MM;
+SC = Mips::SC_MM;
+} else {
+LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
+: (ArePtrs64bit ? Mips::LL64 : Mips::LL);
+SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
+: (ArePtrs64bit ? Mips::SC64 : Mips::SC);
+}
 // insert new blocks after the current block
 const BasicBlock *LLVM_BB = BB->getBasicBlock();
 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
 // FIXME: computation of newval2 can be moved to loop2MBB.
 //  thisMBB:
 //    addiu   masklsb2,$0,-4                # 0xfffffffc
 //    and     alignedaddr,ptr,masklsb2
 //    andi    ptrlsb2,ptr,3
+//    xori    ptrlsb2,ptrlsb2,3              # Only for BE
 //    sll     shiftamt,ptrlsb2,3
 //    ori     maskupper,$0,255               # 0xff
 //    sll     mask,maskupper,shiftamt
 //    nor     mask2,$0,mask
 //    andi    maskedcmpval,cmpval,255
 //    sll     shiftedcmpval,maskedcmpval,shiftamt
 //    andi    maskednewval,newval,255
 //    sll     shiftednewval,maskednewval,shiftamt
 int64_t MaskImm = (Size == 1) ? 255 : 65535;
-BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
+BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2)
-.addReg(Mips::ZERO).addImm(-4);
+.addReg(ABI.GetNullPtr()).addImm(-4);
-BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
+BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr)
 .addReg(Ptr).addReg(MaskLSB2);
-BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
+BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
+.addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
 if (Subtarget.isLittle()) {
 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
 } else {
 unsigned Off = RegInfo.createVirtualRegister(RC);
 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
 //  loop1MBB:
 //    ll      oldval,0(alginedaddr)
 //    and     maskedoldval0,oldval,mask
 //    bne     maskedoldval0,shiftedcmpval,sinkMBB
 BB = loop1MBB;
-unsigned LL = isMicroMips ? Mips::LL_MM : Mips::LL;
 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
 .addReg(OldVal).addReg(Mask);
 BuildMI(BB, DL, TII->get(Mips::BNE))
 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
 BB = loop2MBB;
 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
 .addReg(OldVal).addReg(Mask2);
 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
 .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
-unsigned SC = isMicroMips ? Mips::SC_MM : Mips::SC;
 BuildMI(BB, DL, TII->get(SC), Success)
 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
 BuildMI(BB, DL, TII->get(Mips::BEQ))
 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
 .addReg(MaskedOldVal0).addReg(ShiftAmt);
 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
-MI->eraseFromParent();   // The instruction is gone now.
+MI.eraseFromParent(); // The instruction is gone now.
 return exitMBB;
 }
-MachineBasicBlock *MipsTargetLowering::emitSEL_D(MachineInstr *MI,
+MachineBasicBlock *MipsTargetLowering::emitSEL_D(MachineInstr &MI,
 MachineBasicBlock *BB) const {
 MachineFunction *MF = BB->getParent();
 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
 MachineRegisterInfo &RegInfo = MF->getRegInfo();
-DebugLoc DL = MI->getDebugLoc();
+DebugLoc DL = MI.getDebugLoc();
 MachineBasicBlock::iterator II(MI);
-unsigned Fc = MI->getOperand(1).getReg();
+unsigned Fc = MI.getOperand(1).getReg();
 const auto &FGR64RegClass = TRI->getRegClass(Mips::FGR64RegClassID);
 unsigned Fc2 = RegInfo.createVirtualRegister(FGR64RegClass);
 BuildMI(*BB, II, DL, TII->get(Mips::SUBREG_TO_REG), Fc2)
 .addReg(Fc)
 .addImm(Mips::sub_lo);
 // We don't erase the original instruction, we just replace the condition
 // register with the 64-bit super-register.
-MI->getOperand(1).setReg(Fc2);
+MI.getOperand(1).setReg(Fc2);
 return BB;
-}
-//===----------------------------------------------------------------------===//
-//  Misc Lower Operation implementation
-//===----------------------------------------------------------------------===//
-SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
-SDValue Chain = Op.getOperand(0);
-SDValue Table = Op.getOperand(1);
-SDValue Index = Op.getOperand(2);
-SDLoc DL(Op);
-auto &TD = DAG.getDataLayout();
-EVT PTy = getPointerTy(TD);
-unsigned EntrySize =
-DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
-Index = DAG.getNode(ISD::MUL, DL, PTy, Index,
-DAG.getConstant(EntrySize, DL, PTy));
-SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table);
-EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
-Addr =
-DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr,
-MachinePointerInfo::getJumpTable(DAG.getMachineFunction()),
-MemVT, false, false, false, 0);
-Chain = Addr.getValue(1);
-if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) || ABI.IsN64()) {
-// For PIC, the sequence is:
-// BRIND(load(Jumptable + index) + RelocBase)
-// RelocBase can be JumpTable, GOT or some sort of global base.
-Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr,
-getPICJumpTableRelocBase(Table, DAG));
-}
-return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr);
 }
 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
 // The first operand is the chain, the second is the condition, the third is
 // the block to branch to if the condition is true.
 SelectionDAG &DAG) const {
 EVT Ty = Op.getValueType();
 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
 const GlobalValue *GV = N->getGlobal();
-if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !ABI.IsN64()) {
+if (!isPositionIndependent() && !ABI.IsN64()) {
 const MipsTargetObjectFile *TLOF =
 static_cast<const MipsTargetObjectFile *>(
 getTargetMachine().getObjFileLowering());
-if (TLOF->IsGlobalInSmallSection(GV, getTargetMachine()))
+const GlobalObject *GO = GV->getBaseObject();
+if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine()))
 // %gp_rel relocation
 return getAddrGPRel(N, SDLoc(N), Ty, DAG);
 // %hi/%lo relocation
 return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
 }
-if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV)))
+// Every other architecture would use shouldAssumeDSOLocal in here, but
+// mips is special.
+// * In PIC code mips requires got loads even for local statics!
+// * To save on got entries, for local statics the got entry contains the
+//   page and an additional add instruction takes care of the low bits.
+// * It is legal to access a hidden symbol with a non hidden undefined,
+//   so one cannot guarantee that all access to a hidden symbol will know
+//   it is hidden.
+// * Mips linkers don't support creating a page and a full got entry for
+//   the same symbol.
+// * Given all that, we have to use a full got entry for hidden symbols :-(
+if (GV->hasLocalLinkage())
 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
 if (LargeGOT)
 return getAddrGlobalLargeGOT(
 N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16,
 DAG.getEntryNode(),
 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
 return getAddrGlobal(
 N, SDLoc(N), Ty, DAG,
-(ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT16,
+(ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT,
 DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction()));
 }
 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
 SelectionDAG &DAG) const {
 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
 EVT Ty = Op.getValueType();
-if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !ABI.IsN64())
+if (!isPositionIndependent() && !ABI.IsN64())
 return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
 }
 Entry.Ty = PtrTy;
 Args.push_back(Entry);
 TargetLowering::CallLoweringInfo CLI(DAG);
 CLI.setDebugLoc(DL).setChain(DAG.getEntryNode())
-.setCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args), 0);
+.setCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args));
 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
 SDValue Ret = CallResult.first;
 if (model != TLSModel::LocalDynamic)
 // Initial Exec TLS Model
 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
 MipsII::MO_GOTTPREL);
 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),
 TGA);
-Offset = DAG.getLoad(PtrVT, DL,
+Offset =
-DAG.getEntryNode(), TGA, MachinePointerInfo(),
+DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo());
-false, false, false, 0);
 } else {
 // Local Exec TLS Model
 assert(model == TLSModel::LocalExec);
 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
 MipsII::MO_TPREL_HI);
 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
 {
 JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
 EVT Ty = Op.getValueType();
-if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !ABI.IsN64())
+if (!isPositionIndependent() && !ABI.IsN64())
 return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
 }
 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
 {
 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
 EVT Ty = Op.getValueType();
-if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !ABI.IsN64()) {
+if (!isPositionIndependent() && !ABI.IsN64()) {
 const MipsTargetObjectFile *TLOF =
 static_cast<const MipsTargetObjectFile *>(
 getTargetMachine().getObjFileLowering());
 if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(),
 // vastart just stores the address of the VarArgsFrameIndex slot into the
 // memory location argument.
 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
-MachinePointerInfo(SV), false, false, 0);
+MachinePointerInfo(SV));
 }
 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const {
 SDNode *Node = Op.getNode();
 EVT VT = Node->getValueType(0);
 unsigned Align = Node->getConstantOperandVal(3);
 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
 SDLoc DL(Node);
 unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4;
-SDValue VAListLoad =
+SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain,
-DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain, VAListPtr,
+VAListPtr, MachinePointerInfo(SV));
-MachinePointerInfo(SV), false, false, false, 0);
 SDValue VAList = VAListLoad;
 // Re-align the pointer if necessary.
 // It should only ever be necessary for 64-bit types on O32 since the minimum
 // argument alignment is the same as the maximum type alignment for N32/N64.
 DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
 DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes),
 DL, VAList.getValueType()));
 // Store the incremented VAList to the legalized pointer
 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr,
-MachinePointerInfo(SV), false, false, 0);
+MachinePointerInfo(SV));
 // In big-endian mode we must adjust the pointer when the load size is smaller
 // than the argument slot size. We must also reduce the known alignment to
 // match. For example in the N64 ABI, we must add 4 bytes to the offset to get
 // the correct half of the slot, and reduce the alignment from 8 (slot
 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
 VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList,
 DAG.getIntPtrConstant(Adjustment, DL));
 }
 // Load the actual argument out of the pointer VAList
-return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo(), false, false,
+return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo());
-false, 0);
 }
 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG,
 bool HasExtractInsert) {
 EVT TyX = Op.getOperand(0).getValueType();
 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
 // check the depth
 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
 "Frame address can only be determined for current frame.");
-MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
+MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
-MFI->setFrameAddressIsTaken(true);
+MFI.setFrameAddressIsTaken(true);
 EVT VT = Op.getValueType();
 SDLoc DL(Op);
 SDValue FrameAddr = DAG.getCopyFromReg(
 DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT);
 return FrameAddr;
 // check the depth
 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
 "Return address can be determined only for current frame.");
 MachineFunction &MF = DAG.getMachineFunction();
-MachineFrameInfo *MFI = MF.getFrameInfo();
+MachineFrameInfo &MFI = MF.getFrameInfo();
 MVT VT = Op.getSimpleValueType();
 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA;
-MFI->setReturnAddressIsTaken(true);
+MFI.setReturnAddressIsTaken(true);
 // Return RA, which contains the return address. Mark it an implicit live-in.
 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
 }
 return SDValue();
 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits());
 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy,
 Val.getOperand(0));
 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(),
-SD->getPointerInfo(), SD->isVolatile(),
+SD->getPointerInfo(), SD->getAlignment(),
-SD->isNonTemporal(), SD->getAlignment());
+SD->getMemOperand()->getFlags());
 }
 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
 StoreSDNode *SD = cast<StoreSDNode>(Op);
 EVT MemVT = SD->getMemoryVT();
 return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle());
 return lowerFP_TO_SINT_STORE(SD, DAG);
 }
-SDValue MipsTargetLowering::lowerADD(SDValue Op, SelectionDAG &DAG) const {
+SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op,
-if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR
+SelectionDAG &DAG) const {
-|| cast<ConstantSDNode>
-(Op->getOperand(0).getOperand(0))->getZExtValue() != 0
+// Return a fixed StackObject with offset 0 which points to the old stack
-|| Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET)
+// pointer.
-return SDValue();
+MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
-// The pattern
-//   (add (frameaddr 0), (frame_to_args_offset))
-// results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to
-//   (add FrameObject, 0)
-// where FrameObject is a fixed StackObject with offset 0 which points to
-// the old stack pointer.
-MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
 EVT ValTy = Op->getValueType(0);
-int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
+int FI = MFI.CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
-SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy);
+return DAG.getFrameIndex(FI, ValTy);
-SDLoc DL(Op);
-return DAG.getNode(ISD::ADD, DL, ValTy, InArgsAddr,
-DAG.getConstant(0, DL, ValTy));
 }
 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
 SelectionDAG &DAG) const {
 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
 static unsigned getNextIntArgReg(unsigned Reg) {
 assert((Reg == Mips::A0) || (Reg == Mips::A2));
 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
 }
-SDValue
+SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
-MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
+SDValue Chain, SDValue Arg,
-SDValue Chain, SDValue Arg, SDLoc DL,
+const SDLoc &DL, bool IsTailCall,
-bool IsTailCall, SelectionDAG &DAG) const {
+SelectionDAG &DAG) const {
 if (!IsTailCall) {
 SDValue PtrOff =
 DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
 DAG.getIntPtrConstant(Offset, DL));
-return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false,
+return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo());
-false, 0);
+}
-}
+MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
-MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
+int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
-int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
-/*isVolatile=*/ true, false, 0);
+/* Alignment = */ 0, MachineMemOperand::MOVolatile);
 }
 void MipsTargetLowering::
 getOpndList(SmallVectorImpl<SDValue> &Ops,
 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
 bool &IsTailCall                      = CLI.IsTailCall;
 CallingConv::ID CallConv              = CLI.CallConv;
 bool IsVarArg                         = CLI.IsVarArg;
 MachineFunction &MF = DAG.getMachineFunction();
-MachineFrameInfo *MFI = MF.getFrameInfo();
+MachineFrameInfo &MFI = MF.getFrameInfo();
 const TargetFrameLowering *TFL = Subtarget.getFrameLowering();
 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
-bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
+bool IsPIC = isPositionIndependent();
 // Analyze operands of the call, assigning locations to each operand.
 SmallVector<CCValAssign, 16> ArgLocs;
 MipsCCState CCInfo(
 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(),
 CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), Callee.getNode());
 // Get a count of how many bytes are to be pushed on the stack.
 unsigned NextStackOffset = CCInfo.getNextStackOffset();
-// Check if it's really possible to do a tail call.
+// Check if it's really possible to do a tail call. Restrict it to functions
-if (IsTailCall)
+// that are part of this compilation unit.
+bool InternalLinkage = false;
+if (IsTailCall) {
 IsTailCall = isEligibleForTailCallOptimization(
 CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>());
+if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
+InternalLinkage = G->getGlobal()->hasInternalLinkage();
+IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() ||
+G->getGlobal()->hasPrivateLinkage() ||
+G->getGlobal()->hasHiddenVisibility() ||
+G->getGlobal()->hasProtectedVisibility());
+}
+}
 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
 report_fatal_error("failed to perform tail call elimination on a call "
 "site marked musttail");
 if (IsTailCall)
 SDValue StackPtr =
 DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
 getPointerTy(DAG.getDataLayout()));
-// With EABI is it possible to have 16 args on registers.
 std::deque< std::pair<unsigned, SDValue> > RegsToPass;
 SmallVector<SDValue, 8> MemOpChains;
 CCInfo.rewindByValRegsInfo();
 case CCValAssign::BCvt:
 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
 break;
 case CCValAssign::SExtUpper:
 UseUpperBits = true;
-// Fallthrough
+LLVM_FALLTHROUGH;
 case CCValAssign::SExt:
 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
 break;
 case CCValAssign::ZExtUpper:
 UseUpperBits = true;
-// Fallthrough
+LLVM_FALLTHROUGH;
 case CCValAssign::ZExt:
 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
 break;
 case CCValAssign::AExtUpper:
 UseUpperBits = true;
-// Fallthrough
+LLVM_FALLTHROUGH;
 case CCValAssign::AExt:
 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
 break;
 }
 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
 // node so that legalize doesn't hack it.
 bool IsPICCall = (ABI.IsN64() || IsPIC); // true if calls are translated to
 // jalr $25
-bool GlobalOrExternal = false, InternalLinkage = false, IsCallReloc = false;
 SDValue CalleeLo;
 EVT Ty = Callee.getValueType();
+bool GlobalOrExternal = false, IsCallReloc = false;
 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
 if (IsPICCall) {
 const GlobalValue *Val = G->getGlobal();
 InternalLinkage = Val->hasInternalLinkage();
 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
 getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage,
 IsCallReloc, CLI, Callee, Chain);
-if (IsTailCall)
+if (IsTailCall) {
+MF.getFrameInfo().setHasTailCall();
 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops);
+}
 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops);
 SDValue InFlag = Chain.getValue(1);
 // Create the CALLSEQ_END node.
 /// LowerCallResult - Lower the result values of a call into the
 /// appropriate copies out of appropriate physical registers.
 SDValue MipsTargetLowering::LowerCallResult(
 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
-const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
+const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
-SmallVectorImpl<SDValue> &InVals,
+SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
 TargetLowering::CallLoweringInfo &CLI) const {
 // Assign locations to each value returned by this call.
 SmallVector<CCValAssign, 16> RVLocs;
 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
 *DAG.getContext());
 return Chain;
 }
 static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA,
-EVT ArgVT, SDLoc DL, SelectionDAG &DAG) {
+EVT ArgVT, const SDLoc &DL,
+SelectionDAG &DAG) {
 MVT LocVT = VA.getLocVT();
 EVT ValVT = VA.getValVT();
 // Shift into the upper bits if necessary.
 switch (VA.getLocInfo()) {
 //===----------------------------------------------------------------------===//
 //             Formal Arguments Calling Convention Implementation
 //===----------------------------------------------------------------------===//
 /// LowerFormalArguments - transform physical registers into virtual registers
 /// and generate load operations for arguments places on the stack.
-SDValue
+SDValue MipsTargetLowering::LowerFormalArguments(
-MipsTargetLowering::LowerFormalArguments(SDValue Chain,
+SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
-CallingConv::ID CallConv,
+const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
-bool IsVarArg,
+SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
-const SmallVectorImpl<ISD::InputArg> &Ins,
-SDLoc DL, SelectionDAG &DAG,
-SmallVectorImpl<SDValue> &InVals)
-const {
 MachineFunction &MF = DAG.getMachineFunction();
-MachineFrameInfo *MFI = MF.getFrameInfo();
+MachineFrameInfo &MFI = MF.getFrameInfo();
 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
 MipsFI->setVarArgsFrameIndex(0);
 // Used with vargs to acumulate store chains.
 // sanity check
 assert(VA.isMemLoc());
 // The stack pointer offset is relative to the caller stack frame.
-int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8,
+int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
 VA.getLocMemOffset(), true);
 // Create load nodes to retrieve arguments from the stack
 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
 SDValue ArgValue = DAG.getLoad(
 LocVT, DL, Chain, FIN,
-MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
+MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
-false, false, false, 0);
 OutChains.push_back(ArgValue.getValue(1));
 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
 InVals.push_back(ArgValue);
 return IsSigned;
 }
 SDValue
 MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
-SDLoc DL, SelectionDAG &DAG) const {
+const SDLoc &DL,
+SelectionDAG &DAG) const {
 MachineFunction &MF = DAG.getMachineFunction();
 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
 MipsFI->setISR();
 SDValue
 MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
 bool IsVarArg,
 const SmallVectorImpl<ISD::OutputArg> &Outs,
 const SmallVectorImpl<SDValue> &OutVals,
-SDLoc DL, SelectionDAG &DAG) const {
+const SDLoc &DL, SelectionDAG &DAG) const {
 // CCValAssign - represent the assignment of
 // the return value to a location
 SmallVector<CCValAssign, 16> RVLocs;
 MachineFunction &MF = DAG.getMachineFunction();
 case CCValAssign::BCvt:
 Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val);
 break;
 case CCValAssign::AExtUpper:
 UseUpperBits = true;
-// Fallthrough
+LLVM_FALLTHROUGH;
 case CCValAssign::AExt:
 Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val);
 break;
 case CCValAssign::ZExtUpper:
 UseUpperBits = true;
-// Fallthrough
+LLVM_FALLTHROUGH;
 case CCValAssign::ZExt:
 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val);
 break;
 case CCValAssign::SExtUpper:
 UseUpperBits = true;
-// Fallthrough
+LLVM_FALLTHROUGH;
 case CCValAssign::SExt:
 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val);
 break;
 }
 bool MipsTargetLowering::useSoftFloat() const {
 return Subtarget.useSoftFloat();
 }
 void MipsTargetLowering::copyByValRegs(
-SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, SelectionDAG &DAG,
+SDValue Chain, const SDLoc &DL, std::vector<SDValue> &OutChains,
-const ISD::ArgFlagsTy &Flags, SmallVectorImpl<SDValue> &InVals,
+SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
-const Argument *FuncArg, unsigned FirstReg, unsigned LastReg,
+SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg,
-const CCValAssign &VA, MipsCCState &State) const {
+unsigned FirstReg, unsigned LastReg, const CCValAssign &VA,
+MipsCCState &State) const {
 MachineFunction &MF = DAG.getMachineFunction();
-MachineFrameInfo *MFI = MF.getFrameInfo();
+MachineFrameInfo &MFI = MF.getFrameInfo();
 unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes();
 unsigned NumRegs = LastReg - FirstReg;
 unsigned RegAreaSize = NumRegs * GPRSizeInBytes;
 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
 int FrameObjOffset;
 else
 FrameObjOffset = VA.getLocMemOffset();
 // Create frame object.
 EVT PtrTy = getPointerTy(DAG.getDataLayout());
-int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true);
+int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, true);
 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
 InVals.push_back(FIN);
 if (!NumRegs)
 return;
 unsigned VReg = addLiveIn(MF, ArgReg, RC);
 unsigned Offset = I * GPRSizeInBytes;
 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
 DAG.getConstant(Offset, DL, PtrTy));
 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
-StorePtr, MachinePointerInfo(FuncArg, Offset),
+StorePtr, MachinePointerInfo(FuncArg, Offset));
-false, false, 0);
 OutChains.push_back(Store);
 }
 }
 // Copy byVal arg to registers and stack.
 void MipsTargetLowering::passByValArg(
-SDValue Chain, SDLoc DL,
+SDValue Chain, const SDLoc &DL,
 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
-MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg,
+MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg,
 unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle,
 const CCValAssign &VA) const {
 unsigned ByValSizeInBytes = Flags.getByValSize();
 unsigned OffsetInBytes = 0; // From beginning of struct
 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
 // Copy words to registers.
 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) {
 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
 DAG.getConstant(OffsetInBytes, DL, PtrTy));
 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
-MachinePointerInfo(), false, false, false,
+MachinePointerInfo(), Alignment);
-Alignment);
 MemOpChains.push_back(LoadVal.getValue(1));
 unsigned ArgReg = ArgRegs[FirstReg + I];
 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
 }
 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
 DAG.getConstant(OffsetInBytes, DL,
 PtrTy));
 SDValue LoadVal = DAG.getExtLoad(
 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
-MVT::getIntegerVT(LoadSizeInBytes * 8), false, false, false,
+MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment);
-Alignment);
 MemOpChains.push_back(LoadVal.getValue(1));
 // Shift the loaded value.
 unsigned Shamt;
 MachinePointerInfo(), MachinePointerInfo());
 MemOpChains.push_back(Chain);
 }
 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
-SDValue Chain, SDLoc DL,
+SDValue Chain, const SDLoc &DL,
 SelectionDAG &DAG,
 CCState &State) const {
 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs();
 unsigned Idx = State.getFirstUnallocated(ArgRegs);
 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
 const TargetRegisterClass *RC = getRegClassFor(RegTy);
 MachineFunction &MF = DAG.getMachineFunction();
-MachineFrameInfo *MFI = MF.getFrameInfo();
+MachineFrameInfo &MFI = MF.getFrameInfo();
 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
 // Offset of the first variable argument from stack pointer.
 int VaArgOffset;
 (int)(RegSizeInBytes * (ArgRegs.size() - Idx));
 }
 // Record the frame index of the first variable argument
 // which is a value necessary to VASTART.
-int FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
+int FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
 MipsFI->setVarArgsFrameIndex(FI);
 // Copy the integer registers that have not been used for argument passing
 // to the argument register save area. For O32, the save area is allocated
 // in the caller's stack frame, while for N32/64, it is allocated in the
 // callee's stack frame.
 for (unsigned I = Idx; I < ArgRegs.size();
 ++I, VaArgOffset += RegSizeInBytes) {
 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
-FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
+FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
-SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
+SDValue Store =
-MachinePointerInfo(), false, false, 0);
+DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo());
 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(
 (Value *)nullptr);
 OutChains.push_back(Store);
 }
 }
 }
 State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs);
 }
-MachineBasicBlock *
+MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI,
-MipsTargetLowering::emitPseudoSELECT(MachineInstr *MI, MachineBasicBlock *BB,
+MachineBasicBlock *BB,
-bool isFPCmp, unsigned Opc) const {
+bool isFPCmp,
+unsigned Opc) const {
 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) &&
 "Subtarget already supports SELECT nodes with the use of"
 "conditional-move instructions.");
 const TargetInstrInfo *TII =
 Subtarget.getInstrInfo();
-DebugLoc DL = MI->getDebugLoc();
+DebugLoc DL = MI.getDebugLoc();
 // To "insert" a SELECT instruction, we actually have to insert the
 // diamond control-flow pattern.  The incoming instruction knows the
 // destination vreg to set, the condition code register to branch on, the
 // true/false values to select between, and a branch opcode to use.
 BB->addSuccessor(sinkMBB);
 if (isFPCmp) {
 // bc1[tf] cc, sinkMBB
 BuildMI(BB, DL, TII->get(Opc))
-.addReg(MI->getOperand(1).getReg())
+.addReg(MI.getOperand(1).getReg())
 .addMBB(sinkMBB);
 } else {
 // bne rs, $0, sinkMBB
 BuildMI(BB, DL, TII->get(Opc))
-.addReg(MI->getOperand(1).getReg())
+.addReg(MI.getOperand(1).getReg())
 .addReg(Mips::ZERO)
 .addMBB(sinkMBB);
 }
 //  copy0MBB:
 //   %FalseValue = ...
 //   # fallthrough to sinkMBB
 //  sinkMBB:
 //   %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
 //  ...
 BB = sinkMBB;
-BuildMI(*BB, BB->begin(), DL,
+BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
-TII->get(Mips::PHI), MI->getOperand(0).getReg())
+.addReg(MI.getOperand(2).getReg())
-.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
+.addMBB(thisMBB)
-.addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB);
+.addReg(MI.getOperand(3).getReg())
+.addMBB(copy0MBB);
-MI->eraseFromParent();   // The pseudo instruction is gone now.
+MI.eraseFromParent(); // The pseudo instruction is gone now.
 return BB;
 }
 // FIXME? Maybe this could be a TableGen attribute on some registers and

Mercurial > hg > CbC > CbC_llvm

comparison lib/Target/Mips/MipsISelLowering.cpp @ 120:1172e4bd9c6f