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comparison lib/Target/Sparc/SparcISelLowering.h @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents 7d135dc70f03
children 803732b1fca8
comparison
equal deleted inserted replaced
101:34baf5011add 120:1172e4bd9c6f
31 BRFCC, // Branch to dest on fcc condition 31 BRFCC, // Branch to dest on fcc condition
32 SELECT_ICC, // Select between two values using the current ICC flags. 32 SELECT_ICC, // Select between two values using the current ICC flags.
33 SELECT_XCC, // Select between two values using the current XCC flags. 33 SELECT_XCC, // Select between two values using the current XCC flags.
34 SELECT_FCC, // Select between two values using the current FCC flags. 34 SELECT_FCC, // Select between two values using the current FCC flags.
35 35
36 EH_SJLJ_SETJMP, // builtin setjmp operation
37 EH_SJLJ_LONGJMP, // builtin longjmp operation
38
36 Hi, Lo, // Hi/Lo operations, typically on a global address. 39 Hi, Lo, // Hi/Lo operations, typically on a global address.
37 40
38 FTOI, // FP to Int within a FP register. 41 FTOI, // FP to Int within a FP register.
39 ITOF, // Int to FP within a FP register. 42 ITOF, // Int to FP within a FP register.
40 FTOX, // FP to Int64 within a FP register. 43 FTOX, // FP to Int64 within a FP register.
52 } 55 }
53 56
54 class SparcTargetLowering : public TargetLowering { 57 class SparcTargetLowering : public TargetLowering {
55 const SparcSubtarget *Subtarget; 58 const SparcSubtarget *Subtarget;
56 public: 59 public:
57 SparcTargetLowering(TargetMachine &TM, const SparcSubtarget &STI); 60 SparcTargetLowering(const TargetMachine &TM, const SparcSubtarget &STI);
58 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 61 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
59 62
63 bool useSoftFloat() const override;
64
60 /// computeKnownBitsForTargetNode - Determine which of the bits specified 65 /// computeKnownBitsForTargetNode - Determine which of the bits specified
61 /// in Mask are known to be either zero or one and return them in the 66 /// in Mask are known to be either zero or one and return them in the
62 /// KnownZero/KnownOne bitsets. 67 /// KnownZero/KnownOne bitsets.
63 void computeKnownBitsForTargetNode(const SDValue Op, 68 void computeKnownBitsForTargetNode(const SDValue Op,
64 APInt &KnownZero, 69 APInt &KnownZero,
65 APInt &KnownOne, 70 APInt &KnownOne,
66 const SelectionDAG &DAG, 71 const SelectionDAG &DAG,
67 unsigned Depth = 0) const override; 72 unsigned Depth = 0) const override;
68 73
69 MachineBasicBlock * 74 MachineBasicBlock *
70 EmitInstrWithCustomInserter(MachineInstr *MI, 75 EmitInstrWithCustomInserter(MachineInstr &MI,
71 MachineBasicBlock *MBB) const override; 76 MachineBasicBlock *MBB) const override;
72 77
73 const char *getTargetNodeName(unsigned Opcode) const override; 78 const char *getTargetNodeName(unsigned Opcode) const override;
74 79
75 ConstraintType getConstraintType(StringRef Constraint) const override; 80 ConstraintType getConstraintType(StringRef Constraint) const override;
76 ConstraintWeight 81 ConstraintWeight
78 const char *constraint) const override; 83 const char *constraint) const override;
79 void LowerAsmOperandForConstraint(SDValue Op, 84 void LowerAsmOperandForConstraint(SDValue Op,
80 std::string &Constraint, 85 std::string &Constraint,
81 std::vector<SDValue> &Ops, 86 std::vector<SDValue> &Ops,
82 SelectionDAG &DAG) const override; 87 SelectionDAG &DAG) const override;
88
89 unsigned
90 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
91 if (ConstraintCode == "o")
92 return InlineAsm::Constraint_o;
93 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
94 }
95
83 std::pair<unsigned, const TargetRegisterClass *> 96 std::pair<unsigned, const TargetRegisterClass *>
84 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 97 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
85 StringRef Constraint, MVT VT) const override; 98 StringRef Constraint, MVT VT) const override;
86 99
87 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 100 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
88 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { 101 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
89 return MVT::i32; 102 return MVT::i32;
90 } 103 }
104
105 unsigned getRegisterByName(const char* RegName, EVT VT,
106 SelectionDAG &DAG) const override;
91 107
92 /// If a physical register, this returns the register that receives the 108 /// If a physical register, this returns the register that receives the
93 /// exception address on entry to an EH pad. 109 /// exception address on entry to an EH pad.
94 unsigned 110 unsigned
95 getExceptionPointerRegister(const Constant *PersonalityFn) const override { 111 getExceptionPointerRegister(const Constant *PersonalityFn) const override {
101 unsigned 117 unsigned
102 getExceptionSelectorRegister(const Constant *PersonalityFn) const override { 118 getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
103 return SP::I1; 119 return SP::I1;
104 } 120 }
105 121
122 /// Override to support customized stack guard loading.
123 bool useLoadStackGuardNode() const override;
124 void insertSSPDeclarations(Module &M) const override;
125
106 /// getSetCCResultType - Return the ISD::SETCC ValueType 126 /// getSetCCResultType - Return the ISD::SETCC ValueType
107 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 127 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
108 EVT VT) const override; 128 EVT VT) const override;
109 129
110 SDValue 130 SDValue
111 LowerFormalArguments(SDValue Chain, 131 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
112 CallingConv::ID CallConv, 132 const SmallVectorImpl<ISD::InputArg> &Ins,
113 bool isVarArg, 133 const SDLoc &dl, SelectionDAG &DAG,
114 const SmallVectorImpl<ISD::InputArg> &Ins, 134 SmallVectorImpl<SDValue> &InVals) const override;
115 SDLoc dl, SelectionDAG &DAG, 135 SDValue LowerFormalArguments_32(SDValue Chain, CallingConv::ID CallConv,
116 SmallVectorImpl<SDValue> &InVals) const override;
117 SDValue LowerFormalArguments_32(SDValue Chain,
118 CallingConv::ID CallConv,
119 bool isVarArg, 136 bool isVarArg,
120 const SmallVectorImpl<ISD::InputArg> &Ins, 137 const SmallVectorImpl<ISD::InputArg> &Ins,
121 SDLoc dl, SelectionDAG &DAG, 138 const SDLoc &dl, SelectionDAG &DAG,
122 SmallVectorImpl<SDValue> &InVals) const; 139 SmallVectorImpl<SDValue> &InVals) const;
123 SDValue LowerFormalArguments_64(SDValue Chain, 140 SDValue LowerFormalArguments_64(SDValue Chain, CallingConv::ID CallConv,
124 CallingConv::ID CallConv,
125 bool isVarArg, 141 bool isVarArg,
126 const SmallVectorImpl<ISD::InputArg> &Ins, 142 const SmallVectorImpl<ISD::InputArg> &Ins,
127 SDLoc dl, SelectionDAG &DAG, 143 const SDLoc &dl, SelectionDAG &DAG,
128 SmallVectorImpl<SDValue> &InVals) const; 144 SmallVectorImpl<SDValue> &InVals) const;
129 145
130 SDValue 146 SDValue
131 LowerCall(TargetLowering::CallLoweringInfo &CLI, 147 LowerCall(TargetLowering::CallLoweringInfo &CLI,
132 SmallVectorImpl<SDValue> &InVals) const override; 148 SmallVectorImpl<SDValue> &InVals) const override;
133 SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI, 149 SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
134 SmallVectorImpl<SDValue> &InVals) const; 150 SmallVectorImpl<SDValue> &InVals) const;
135 SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI, 151 SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
136 SmallVectorImpl<SDValue> &InVals) const; 152 SmallVectorImpl<SDValue> &InVals) const;
137 153
138 SDValue 154 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
139 LowerReturn(SDValue Chain, 155 const SmallVectorImpl<ISD::OutputArg> &Outs,
140 CallingConv::ID CallConv, bool isVarArg, 156 const SmallVectorImpl<SDValue> &OutVals,
141 const SmallVectorImpl<ISD::OutputArg> &Outs, 157 const SDLoc &dl, SelectionDAG &DAG) const override;
142 const SmallVectorImpl<SDValue> &OutVals, 158 SDValue LowerReturn_32(SDValue Chain, CallingConv::ID CallConv,
143 SDLoc dl, SelectionDAG &DAG) const override; 159 bool IsVarArg,
144 SDValue LowerReturn_32(SDValue Chain,
145 CallingConv::ID CallConv, bool IsVarArg,
146 const SmallVectorImpl<ISD::OutputArg> &Outs, 160 const SmallVectorImpl<ISD::OutputArg> &Outs,
147 const SmallVectorImpl<SDValue> &OutVals, 161 const SmallVectorImpl<SDValue> &OutVals,
148 SDLoc DL, SelectionDAG &DAG) const; 162 const SDLoc &DL, SelectionDAG &DAG) const;
149 SDValue LowerReturn_64(SDValue Chain, 163 SDValue LowerReturn_64(SDValue Chain, CallingConv::ID CallConv,
150 CallingConv::ID CallConv, bool IsVarArg, 164 bool IsVarArg,
151 const SmallVectorImpl<ISD::OutputArg> &Outs, 165 const SmallVectorImpl<ISD::OutputArg> &Outs,
152 const SmallVectorImpl<SDValue> &OutVals, 166 const SmallVectorImpl<SDValue> &OutVals,
153 SDLoc DL, SelectionDAG &DAG) const; 167 const SDLoc &DL, SelectionDAG &DAG) const;
154 168
155 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 169 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
156 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 170 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
157 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 171 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
158 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 172 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
173
174 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG,
175 const SparcTargetLowering &TLI) const ;
176 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG,
177 const SparcTargetLowering &TLI) const ;
159 178
160 unsigned getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const; 179 unsigned getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const;
161 SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const; 180 SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const;
162 SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF, 181 SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
163 SelectionDAG &DAG) const; 182 SelectionDAG &DAG) const;
164 SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const; 183 SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const;
165 184
166 SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, 185 SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, SDValue Arg,
167 SDValue Arg, SDLoc DL, 186 const SDLoc &DL, SelectionDAG &DAG) const;
168 SelectionDAG &DAG) const;
169 SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG, 187 SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG,
170 const char *LibFuncName, 188 const char *LibFuncName,
171 unsigned numArgs) const; 189 unsigned numArgs) const;
172 SDValue LowerF128Compare(SDValue LHS, SDValue RHS, 190 SDValue LowerF128Compare(SDValue LHS, SDValue RHS, unsigned &SPCC,
173 unsigned &SPCC, 191 const SDLoc &DL, SelectionDAG &DAG) const;
174 SDLoc DL, 192
175 SelectionDAG &DAG) const; 193 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
176 194
177 bool ShouldShrinkFPConstant(EVT VT) const override { 195 bool ShouldShrinkFPConstant(EVT VT) const override {
178 // Do not shrink FP constpool if VT == MVT::f128. 196 // Do not shrink FP constpool if VT == MVT::f128.
179 // (ldd, call _Q_fdtoq) is more expensive than two ldds. 197 // (ldd, call _Q_fdtoq) is more expensive than two ldds.
180 return VT != MVT::f128; 198 return VT != MVT::f128;
181 } 199 }
182 200
201 bool shouldInsertFencesForAtomic(const Instruction *I) const override {
202 // FIXME: We insert fences for each atomics and generate
203 // sub-optimal code for PSO/TSO. (Approximately nobody uses any
204 // mode but TSO, which makes this even more silly)
205 return true;
206 }
207
208 AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
209
183 void ReplaceNodeResults(SDNode *N, 210 void ReplaceNodeResults(SDNode *N,
184 SmallVectorImpl<SDValue>& Results, 211 SmallVectorImpl<SDValue>& Results,
185 SelectionDAG &DAG) const override; 212 SelectionDAG &DAG) const override;
186 213
187 MachineBasicBlock *expandSelectCC(MachineInstr *MI, MachineBasicBlock *BB, 214 MachineBasicBlock *expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB,
188 unsigned BROpcode) const; 215 unsigned BROpcode) const;
189 MachineBasicBlock *expandAtomicRMW(MachineInstr *MI, 216 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI,
190 MachineBasicBlock *BB, 217 MachineBasicBlock *MBB) const;
191 unsigned Opcode, 218 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI,
192 unsigned CondCode = 0) const; 219 MachineBasicBlock *MBB) const;
193 }; 220 };
194 } // end namespace llvm 221 } // end namespace llvm
195 222
196 #endif // SPARC_ISELLOWERING_H 223 #endif // SPARC_ISELLOWERING_H