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comparison lib/Target/SystemZ/SystemZScheduleZ196.td @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
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101:34baf5011add 120:1172e4bd9c6f
1 //=- SystemZScheduleZ196.td - SystemZ Scheduling Definitions ---*- tblgen -*-=//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the machine model for Z196 to support instruction
11 // scheduling and other instruction cost heuristics.
12 //
13 //===----------------------------------------------------------------------===//
14
15 def Z196Model : SchedMachineModel {
16
17 let UnsupportedFeatures = Arch9UnsupportedFeatures.List;
18
19 let IssueWidth = 5;
20 let MicroOpBufferSize = 40; // Issue queues
21 let LoadLatency = 1; // Optimistic load latency.
22
23 let PostRAScheduler = 1;
24
25 // Extra cycles for a mispredicted branch.
26 let MispredictPenalty = 8;
27 }
28
29 let SchedModel = Z196Model in {
30
31 // These definitions could be put in a subtarget common include file,
32 // but it seems the include system in Tablegen currently rejects
33 // multiple includes of same file.
34 def : WriteRes<GroupAlone, []> {
35 let NumMicroOps = 0;
36 let BeginGroup = 1;
37 let EndGroup = 1;
38 }
39 def : WriteRes<EndGroup, []> {
40 let NumMicroOps = 0;
41 let EndGroup = 1;
42 }
43 def : WriteRes<Lat2, []> { let Latency = 2; let NumMicroOps = 0;}
44 def : WriteRes<Lat3, []> { let Latency = 3; let NumMicroOps = 0;}
45 def : WriteRes<Lat4, []> { let Latency = 4; let NumMicroOps = 0;}
46 def : WriteRes<Lat5, []> { let Latency = 5; let NumMicroOps = 0;}
47 def : WriteRes<Lat6, []> { let Latency = 6; let NumMicroOps = 0;}
48 def : WriteRes<Lat7, []> { let Latency = 7; let NumMicroOps = 0;}
49 def : WriteRes<Lat8, []> { let Latency = 8; let NumMicroOps = 0;}
50 def : WriteRes<Lat9, []> { let Latency = 9; let NumMicroOps = 0;}
51 def : WriteRes<Lat10, []> { let Latency = 10; let NumMicroOps = 0;}
52 def : WriteRes<Lat11, []> { let Latency = 11; let NumMicroOps = 0;}
53 def : WriteRes<Lat12, []> { let Latency = 12; let NumMicroOps = 0;}
54 def : WriteRes<Lat15, []> { let Latency = 15; let NumMicroOps = 0;}
55 def : WriteRes<Lat20, []> { let Latency = 20; let NumMicroOps = 0;}
56 def : WriteRes<Lat30, []> { let Latency = 30; let NumMicroOps = 0;}
57
58 // Execution units.
59 def Z196_FXUnit : ProcResource<2>;
60 def Z196_LSUnit : ProcResource<2>;
61 def Z196_FPUnit : ProcResource<1>;
62
63 // Subtarget specific definitions of scheduling resources.
64 def : WriteRes<FXU, [Z196_FXUnit]> { let Latency = 1; }
65 def : WriteRes<LSU, [Z196_LSUnit]> { let Latency = 4; }
66 def : WriteRes<LSU_lat1, [Z196_LSUnit]> { let Latency = 1; }
67 def : WriteRes<FPU, [Z196_FPUnit]> { let Latency = 8; }
68 def : WriteRes<FPU2, [Z196_FPUnit, Z196_FPUnit]> { let Latency = 9; }
69
70 // -------------------------- INSTRUCTIONS ---------------------------------- //
71
72 // InstRW constructs have been used in order to preserve the
73 // readability of the InstrInfo files.
74
75 // For each instruction, as matched by a regexp, provide a list of
76 // resources that it needs. These will be combined into a SchedClass.
77
78 //===----------------------------------------------------------------------===//
79 // Stack allocation
80 //===----------------------------------------------------------------------===//
81
82 def : InstRW<[FXU], (instregex "ADJDYNALLOC$")>; // Pseudo -> LA / LAY
83
84 //===----------------------------------------------------------------------===//
85 // Branch instructions
86 //===----------------------------------------------------------------------===//
87
88 // Branch
89 def : InstRW<[LSU, EndGroup], (instregex "(Call)?BRC(L)?(Asm.*)?$")>;
90 def : InstRW<[LSU, EndGroup], (instregex "(Call)?J(G)?(Asm.*)?$")>;
91 def : InstRW<[LSU, EndGroup], (instregex "(Call)?BC(R)?(Asm.*)?$")>;
92 def : InstRW<[LSU, EndGroup], (instregex "(Call)?B(R)?(Asm.*)?$")>;
93 def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "BRCT(G)?$")>;
94 def : InstRW<[FXU, FXU, FXU, LSU, Lat7, GroupAlone], (instregex "BRX(H|LE)$")>;
95
96 // Compare and branch
97 def : InstRW<[FXU, LSU, Lat5, GroupAlone],
98 (instregex "C(L)?(G)?(I|R)J(Asm.*)?$")>;
99 def : InstRW<[FXU, LSU, Lat5, GroupAlone],
100 (instregex "C(L)?(G)?(I|R)B(Call|Return|Asm.*)?$")>;
101
102 //===----------------------------------------------------------------------===//
103 // Trap instructions
104 //===----------------------------------------------------------------------===//
105
106 // Trap
107 def : InstRW<[LSU, EndGroup], (instregex "(Cond)?Trap$")>;
108
109 // Compare and trap
110 def : InstRW<[FXU], (instregex "C(G)?(I|R)T(Asm.*)?$")>;
111 def : InstRW<[FXU], (instregex "CL(G)?RT(Asm.*)?$")>;
112 def : InstRW<[FXU], (instregex "CL(F|G)IT(Asm.*)?$")>;
113
114 //===----------------------------------------------------------------------===//
115 // Call and return instructions
116 //===----------------------------------------------------------------------===//
117
118 // Call
119 def : InstRW<[LSU, FXU, FXU, Lat6, GroupAlone], (instregex "(Call)?BRAS$")>;
120 def : InstRW<[LSU, FXU, FXU, Lat6, GroupAlone], (instregex "(Call)?BRASL$")>;
121 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "(Call)?BAS(R)?$")>;
122 def : InstRW<[LSU, FXU, FXU, Lat6, GroupAlone], (instregex "TLS_(G|L)DCALL$")>;
123
124 // Return
125 def : InstRW<[LSU_lat1, EndGroup], (instregex "Return$")>;
126 def : InstRW<[LSU_lat1, EndGroup], (instregex "CondReturn$")>;
127
128 //===----------------------------------------------------------------------===//
129 // Select instructions
130 //===----------------------------------------------------------------------===//
131
132 // Select pseudo
133 def : InstRW<[FXU], (instregex "Select(32|64|32Mux)$")>;
134
135 // CondStore pseudos
136 def : InstRW<[FXU], (instregex "CondStore16(Inv)?$")>;
137 def : InstRW<[FXU], (instregex "CondStore16Mux(Inv)?$")>;
138 def : InstRW<[FXU], (instregex "CondStore32(Inv)?$")>;
139 def : InstRW<[FXU], (instregex "CondStore64(Inv)?$")>;
140 def : InstRW<[FXU], (instregex "CondStore8(Inv)?$")>;
141 def : InstRW<[FXU], (instregex "CondStore8Mux(Inv)?$")>;
142
143 //===----------------------------------------------------------------------===//
144 // Move instructions
145 //===----------------------------------------------------------------------===//
146
147 // Moves
148 def : InstRW<[FXU, LSU, Lat5], (instregex "MV(G|H)?HI$")>;
149 def : InstRW<[FXU, LSU, Lat5], (instregex "MVI(Y)?$")>;
150
151 // Move character
152 def : InstRW<[LSU, LSU, LSU, FXU, Lat8, GroupAlone], (instregex "MVC$")>;
153
154 // Pseudo -> reg move
155 def : InstRW<[FXU], (instregex "COPY(_TO_REGCLASS)?$")>;
156 def : InstRW<[FXU], (instregex "EXTRACT_SUBREG$")>;
157 def : InstRW<[FXU], (instregex "INSERT_SUBREG$")>;
158 def : InstRW<[FXU], (instregex "REG_SEQUENCE$")>;
159 def : InstRW<[FXU], (instregex "SUBREG_TO_REG$")>;
160
161 // Loads
162 def : InstRW<[LSU], (instregex "L(Y|FH|RL|Mux)?$")>;
163 def : InstRW<[LSU], (instregex "LG(RL)?$")>;
164 def : InstRW<[LSU], (instregex "L128$")>;
165
166 def : InstRW<[FXU], (instregex "LLIH(F|H|L)$")>;
167 def : InstRW<[FXU], (instregex "LLIL(F|H|L)$")>;
168
169 def : InstRW<[FXU], (instregex "LG(F|H)I$")>;
170 def : InstRW<[FXU], (instregex "LHI(Mux)?$")>;
171 def : InstRW<[FXU], (instregex "LR(Mux)?$")>;
172
173 // Load and test
174 def : InstRW<[FXU, LSU, Lat5], (instregex "LT(G)?$")>;
175 def : InstRW<[FXU], (instregex "LT(G)?R$")>;
176
177 // Stores
178 def : InstRW<[FXU, LSU, Lat5], (instregex "STG(RL)?$")>;
179 def : InstRW<[FXU, LSU, Lat5], (instregex "ST128$")>;
180 def : InstRW<[FXU, LSU, Lat5], (instregex "ST(Y|FH|RL|Mux)?$")>;
181
182 // String moves.
183 def : InstRW<[LSU, Lat30, GroupAlone], (instregex "MVST$")>;
184
185 //===----------------------------------------------------------------------===//
186 // Conditional move instructions
187 //===----------------------------------------------------------------------===//
188
189 def : InstRW<[FXU, Lat2, EndGroup], (instregex "LOC(G)?R(Asm.*)?$")>;
190 def : InstRW<[FXU, Lat2, EndGroup], (instregex "LOC(G)?HI(Asm.*)?$")>;
191 def : InstRW<[FXU, LSU, Lat6, EndGroup], (instregex "LOC(G)?(Asm.*)?$")>;
192 def : InstRW<[FXU, LSU, Lat5, EndGroup], (instregex "STOC(G)?(Asm.*)?$")>;
193
194 //===----------------------------------------------------------------------===//
195 // Sign extensions
196 //===----------------------------------------------------------------------===//
197 def : InstRW<[FXU], (instregex "L(B|H|G)R$")>;
198 def : InstRW<[FXU], (instregex "LG(B|H|F)R$")>;
199
200 def : InstRW<[FXU, LSU, Lat5], (instregex "LTGF$")>;
201 def : InstRW<[FXU], (instregex "LTGFR$")>;
202
203 def : InstRW<[FXU, LSU, Lat5], (instregex "LB(H|Mux)?$")>;
204 def : InstRW<[FXU, LSU, Lat5], (instregex "LH(Y)?$")>;
205 def : InstRW<[FXU, LSU, Lat5], (instregex "LH(H|Mux|RL)$")>;
206 def : InstRW<[FXU, LSU, Lat5], (instregex "LG(B|H|F)$")>;
207 def : InstRW<[FXU, LSU, Lat5], (instregex "LG(H|F)RL$")>;
208
209 //===----------------------------------------------------------------------===//
210 // Zero extensions
211 //===----------------------------------------------------------------------===//
212
213 def : InstRW<[FXU], (instregex "LLCR(Mux)?$")>;
214 def : InstRW<[FXU], (instregex "LLHR(Mux)?$")>;
215 def : InstRW<[FXU], (instregex "LLG(C|F|H|T)R$")>;
216 def : InstRW<[LSU], (instregex "LLC(Mux)?$")>;
217 def : InstRW<[LSU], (instregex "LLH(Mux)?$")>;
218 def : InstRW<[FXU, LSU, Lat5], (instregex "LL(C|H)H$")>;
219 def : InstRW<[LSU], (instregex "LLHRL$")>;
220 def : InstRW<[LSU], (instregex "LLG(C|F|H|T|FRL|HRL)$")>;
221
222 //===----------------------------------------------------------------------===//
223 // Truncations
224 //===----------------------------------------------------------------------===//
225
226 def : InstRW<[FXU, LSU, Lat5], (instregex "STC(H|Y|Mux)?$")>;
227 def : InstRW<[FXU, LSU, Lat5], (instregex "STH(H|Y|RL|Mux)?$")>;
228
229 //===----------------------------------------------------------------------===//
230 // Multi-register moves
231 //===----------------------------------------------------------------------===//
232
233 // Load multiple (estimated average of 5 ops)
234 def : InstRW<[LSU, LSU, LSU, LSU, LSU, Lat10, GroupAlone],
235 (instregex "LM(H|Y|G)?$")>;
236
237 // Store multiple (estimated average of 3 ops)
238 def : InstRW<[LSU, LSU, FXU, FXU, FXU, Lat10, GroupAlone],
239 (instregex "STM(H|Y|G)?$")>;
240
241 //===----------------------------------------------------------------------===//
242 // Byte swaps
243 //===----------------------------------------------------------------------===//
244
245 def : InstRW<[FXU], (instregex "LRV(G)?R$")>;
246 def : InstRW<[FXU, LSU, Lat5], (instregex "LRV(G|H)?$")>;
247 def : InstRW<[FXU, LSU, Lat5], (instregex "STRV(G|H)?$")>;
248
249 //===----------------------------------------------------------------------===//
250 // Load address instructions
251 //===----------------------------------------------------------------------===//
252
253 def : InstRW<[FXU], (instregex "LA(Y|RL)?$")>;
254
255 // Load the Global Offset Table address
256 def : InstRW<[FXU], (instregex "GOT$")>;
257
258 //===----------------------------------------------------------------------===//
259 // Absolute and Negation
260 //===----------------------------------------------------------------------===//
261
262 def : InstRW<[FXU, Lat2], (instregex "LP(G)?R$")>;
263 def : InstRW<[FXU, FXU, Lat3, GroupAlone], (instregex "L(N|P)GFR$")>;
264 def : InstRW<[FXU, Lat2], (instregex "LN(R|GR)$")>;
265 def : InstRW<[FXU], (instregex "LC(R|GR)$")>;
266 def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LCGFR$")>;
267
268 //===----------------------------------------------------------------------===//
269 // Insertion
270 //===----------------------------------------------------------------------===//
271
272 def : InstRW<[FXU, LSU, Lat5], (instregex "IC(Y)?$")>;
273 def : InstRW<[FXU, LSU, Lat5], (instregex "IC32(Y)?$")>;
274 def : InstRW<[FXU, LSU, Lat5], (instregex "ICM(H|Y)?$")>;
275 def : InstRW<[FXU], (instregex "II(F|H|L)Mux$")>;
276 def : InstRW<[FXU], (instregex "IIHF(64)?$")>;
277 def : InstRW<[FXU], (instregex "IIHH(64)?$")>;
278 def : InstRW<[FXU], (instregex "IIHL(64)?$")>;
279 def : InstRW<[FXU], (instregex "IILF(64)?$")>;
280 def : InstRW<[FXU], (instregex "IILH(64)?$")>;
281 def : InstRW<[FXU], (instregex "IILL(64)?$")>;
282
283 //===----------------------------------------------------------------------===//
284 // Addition
285 //===----------------------------------------------------------------------===//
286
287 def : InstRW<[FXU, LSU, Lat5], (instregex "A(Y|SI)?$")>;
288 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "AH(Y)?$")>;
289 def : InstRW<[FXU], (instregex "AIH$")>;
290 def : InstRW<[FXU], (instregex "AFI(Mux)?$")>;
291 def : InstRW<[FXU], (instregex "AGFI$")>;
292 def : InstRW<[FXU], (instregex "AGHI(K)?$")>;
293 def : InstRW<[FXU], (instregex "AGR(K)?$")>;
294 def : InstRW<[FXU], (instregex "AHI(K)?$")>;
295 def : InstRW<[FXU], (instregex "AHIMux(K)?$")>;
296 def : InstRW<[FXU, LSU, Lat5], (instregex "AL(Y)?$")>;
297 def : InstRW<[FXU], (instregex "AL(FI|HSIK)$")>;
298 def : InstRW<[FXU, LSU, Lat5], (instregex "ALG(F)?$")>;
299 def : InstRW<[FXU], (instregex "ALGHSIK$")>;
300 def : InstRW<[FXU], (instregex "ALGF(I|R)$")>;
301 def : InstRW<[FXU], (instregex "ALGR(K)?$")>;
302 def : InstRW<[FXU], (instregex "ALR(K)?$")>;
303 def : InstRW<[FXU], (instregex "AR(K)?$")>;
304 def : InstRW<[FXU, LSU, Lat5], (instregex "AG(SI)?$")>;
305
306 // Logical addition with carry
307 def : InstRW<[FXU, LSU, Lat7, GroupAlone], (instregex "ALC(G)?$")>;
308 def : InstRW<[FXU, Lat3, GroupAlone], (instregex "ALC(G)?R$")>;
309
310 // Add with sign extension (32 -> 64)
311 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "AGF$")>;
312 def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "AGFR$")>;
313
314 //===----------------------------------------------------------------------===//
315 // Subtraction
316 //===----------------------------------------------------------------------===//
317
318 def : InstRW<[FXU, LSU, Lat5], (instregex "S(G|Y)?$")>;
319 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "SH(Y)?$")>;
320 def : InstRW<[FXU], (instregex "SGR(K)?$")>;
321 def : InstRW<[FXU], (instregex "SLFI$")>;
322 def : InstRW<[FXU, LSU, Lat5], (instregex "SL(G|GF|Y)?$")>;
323 def : InstRW<[FXU], (instregex "SLGF(I|R)$")>;
324 def : InstRW<[FXU], (instregex "SLGR(K)?$")>;
325 def : InstRW<[FXU], (instregex "SLR(K)?$")>;
326 def : InstRW<[FXU], (instregex "SR(K)?$")>;
327
328 // Subtraction with borrow
329 def : InstRW<[FXU, LSU, Lat7, GroupAlone], (instregex "SLB(G)?$")>;
330 def : InstRW<[FXU, Lat3, GroupAlone], (instregex "SLB(G)?R$")>;
331
332 // Subtraction with sign extension (32 -> 64)
333 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "SGF$")>;
334 def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "SGFR$")>;
335
336 //===----------------------------------------------------------------------===//
337 // AND
338 //===----------------------------------------------------------------------===//
339
340 def : InstRW<[FXU, LSU, Lat5], (instregex "N(G|Y)?$")>;
341 def : InstRW<[FXU], (instregex "NGR(K)?$")>;
342 def : InstRW<[FXU], (instregex "NI(FMux|HMux|LMux)$")>;
343 def : InstRW<[FXU, LSU, Lat5], (instregex "NI(Y)?$")>;
344 def : InstRW<[FXU], (instregex "NIHF(64)?$")>;
345 def : InstRW<[FXU], (instregex "NIHH(64)?$")>;
346 def : InstRW<[FXU], (instregex "NIHL(64)?$")>;
347 def : InstRW<[FXU], (instregex "NILF(64)?$")>;
348 def : InstRW<[FXU], (instregex "NILH(64)?$")>;
349 def : InstRW<[FXU], (instregex "NILL(64)?$")>;
350 def : InstRW<[FXU], (instregex "NR(K)?$")>;
351 def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "NC$")>;
352
353 //===----------------------------------------------------------------------===//
354 // OR
355 //===----------------------------------------------------------------------===//
356
357 def : InstRW<[FXU, LSU, Lat5], (instregex "O(G|Y)?$")>;
358 def : InstRW<[FXU], (instregex "OGR(K)?$")>;
359 def : InstRW<[FXU, LSU, Lat5], (instregex "OI(Y)?$")>;
360 def : InstRW<[FXU], (instregex "OI(FMux|HMux|LMux)$")>;
361 def : InstRW<[FXU], (instregex "OIHF(64)?$")>;
362 def : InstRW<[FXU], (instregex "OIHH(64)?$")>;
363 def : InstRW<[FXU], (instregex "OIHL(64)?$")>;
364 def : InstRW<[FXU], (instregex "OILF(64)?$")>;
365 def : InstRW<[FXU], (instregex "OILH(64)?$")>;
366 def : InstRW<[FXU], (instregex "OILL(64)?$")>;
367 def : InstRW<[FXU], (instregex "OR(K)?$")>;
368 def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "OC$")>;
369
370 //===----------------------------------------------------------------------===//
371 // XOR
372 //===----------------------------------------------------------------------===//
373
374 def : InstRW<[FXU, LSU, Lat5], (instregex "X(G|Y)?$")>;
375 def : InstRW<[FXU, LSU, Lat5], (instregex "XI(Y)?$")>;
376 def : InstRW<[FXU], (instregex "XIFMux$")>;
377 def : InstRW<[FXU], (instregex "XGR(K)?$")>;
378 def : InstRW<[FXU], (instregex "XIHF(64)?$")>;
379 def : InstRW<[FXU], (instregex "XILF(64)?$")>;
380 def : InstRW<[FXU], (instregex "XR(K)?$")>;
381 def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "XC$")>;
382
383 //===----------------------------------------------------------------------===//
384 // Multiplication
385 //===----------------------------------------------------------------------===//
386
387 def : InstRW<[FXU, LSU, Lat10], (instregex "MS(GF|Y)?$")>;
388 def : InstRW<[FXU, Lat6], (instregex "MS(R|FI)$")>;
389 def : InstRW<[FXU, LSU, Lat12], (instregex "MSG$")>;
390 def : InstRW<[FXU, Lat8], (instregex "MSGR$")>;
391 def : InstRW<[FXU, Lat6], (instregex "MSGF(I|R)$")>;
392 def : InstRW<[FXU, LSU, Lat15, GroupAlone], (instregex "MLG$")>;
393 def : InstRW<[FXU, Lat9, GroupAlone], (instregex "MLGR$")>;
394 def : InstRW<[FXU, Lat5], (instregex "MGHI$")>;
395 def : InstRW<[FXU, Lat5], (instregex "MHI$")>;
396 def : InstRW<[FXU, LSU, Lat9], (instregex "MH(Y)?$")>;
397
398 //===----------------------------------------------------------------------===//
399 // Division and remainder
400 //===----------------------------------------------------------------------===//
401
402 def : InstRW<[FPU2, FPU2, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
403 (instregex "DSG(F)?R$")>;
404 def : InstRW<[FPU2, FPU2, LSU, FXU, FXU, FXU, Lat30, GroupAlone],
405 (instregex "DSG(F)?$")>;
406 def : InstRW<[FPU2, FPU2, FXU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
407 (instregex "DL(G)?R$")>;
408 def : InstRW<[FPU2, FPU2, LSU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
409 (instregex "DL(G)?$")>;
410
411 //===----------------------------------------------------------------------===//
412 // Shifts
413 //===----------------------------------------------------------------------===//
414
415 def : InstRW<[FXU], (instregex "SLL(G|K)?$")>;
416 def : InstRW<[FXU], (instregex "SRL(G|K)?$")>;
417 def : InstRW<[FXU], (instregex "SRA(G|K)?$")>;
418 def : InstRW<[FXU, Lat2], (instregex "SLA(K)?$")>;
419
420 // Rotate
421 def : InstRW<[FXU, LSU, Lat6], (instregex "RLL(G)?$")>;
422
423 // Rotate and insert
424 def : InstRW<[FXU], (instregex "RISBG(32)?$")>;
425 def : InstRW<[FXU], (instregex "RISBH(G|H|L)$")>;
426 def : InstRW<[FXU], (instregex "RISBL(G|H|L)$")>;
427 def : InstRW<[FXU], (instregex "RISBMux$")>;
428
429 // Rotate and Select
430 def : InstRW<[FXU, FXU, Lat3, GroupAlone], (instregex "R(N|O|X)SBG$")>;
431
432 //===----------------------------------------------------------------------===//
433 // Comparison
434 //===----------------------------------------------------------------------===//
435
436 def : InstRW<[FXU, LSU, Lat5], (instregex "C(G|Y|Mux|RL)?$")>;
437 def : InstRW<[FXU], (instregex "CFI(Mux)?$")>;
438 def : InstRW<[FXU], (instregex "CG(F|H)I$")>;
439 def : InstRW<[FXU, LSU, Lat5], (instregex "CG(HSI|RL)$")>;
440 def : InstRW<[FXU], (instregex "C(G)?R$")>;
441 def : InstRW<[FXU], (instregex "C(HI|IH)$")>;
442 def : InstRW<[FXU, LSU, Lat5], (instregex "CH(F|SI)$")>;
443 def : InstRW<[FXU, LSU, Lat5], (instregex "CL(Y|Mux|FHSI)?$")>;
444 def : InstRW<[FXU], (instregex "CLFI(Mux)?$")>;
445 def : InstRW<[FXU, LSU, Lat5], (instregex "CLG(HRL|HSI)?$")>;
446 def : InstRW<[FXU, LSU, Lat5], (instregex "CLGF(RL)?$")>;
447 def : InstRW<[FXU], (instregex "CLGF(I|R)$")>;
448 def : InstRW<[FXU], (instregex "CLGR$")>;
449 def : InstRW<[FXU, LSU, Lat5], (instregex "CLGRL$")>;
450 def : InstRW<[FXU, LSU, Lat5], (instregex "CLH(F|RL|HSI)$")>;
451 def : InstRW<[FXU], (instregex "CLIH$")>;
452 def : InstRW<[FXU, LSU, Lat5], (instregex "CLI(Y)?$")>;
453 def : InstRW<[FXU], (instregex "CLR$")>;
454 def : InstRW<[FXU, LSU, Lat5], (instregex "CLRL$")>;
455
456 // Compare halfword
457 def : InstRW<[FXU, LSU, FXU, Lat6, GroupAlone], (instregex "CH(Y|RL)?$")>;
458 def : InstRW<[FXU, LSU, FXU, Lat6, GroupAlone], (instregex "CGH(RL)?$")>;
459 def : InstRW<[FXU, LSU, FXU, Lat6, GroupAlone], (instregex "CHHSI$")>;
460
461 // Compare with sign extension (32 -> 64)
462 def : InstRW<[FXU, FXU, LSU, Lat6, Lat2, GroupAlone], (instregex "CGF(RL)?$")>;
463 def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "CGFR$")>;
464
465 // Compare logical character
466 def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "CLC$")>;
467
468 def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CLST$")>;
469
470 // Test under mask
471 def : InstRW<[FXU, LSU, Lat5], (instregex "TM(Y)?$")>;
472 def : InstRW<[FXU], (instregex "TM(H|L)Mux$")>;
473 def : InstRW<[FXU], (instregex "TMHH(64)?$")>;
474 def : InstRW<[FXU], (instregex "TMHL(64)?$")>;
475 def : InstRW<[FXU], (instregex "TMLH(64)?$")>;
476 def : InstRW<[FXU], (instregex "TMLL(64)?$")>;
477
478 //===----------------------------------------------------------------------===//
479 // Prefetch
480 //===----------------------------------------------------------------------===//
481
482 def : InstRW<[LSU, GroupAlone], (instregex "PFD(RL)?$")>;
483
484 //===----------------------------------------------------------------------===//
485 // Atomic operations
486 //===----------------------------------------------------------------------===//
487
488 def : InstRW<[LSU, EndGroup], (instregex "Serialize$")>;
489
490 def : InstRW<[FXU, LSU, Lat5], (instregex "LAA(G)?$")>;
491 def : InstRW<[FXU, LSU, Lat5], (instregex "LAAL(G)?$")>;
492 def : InstRW<[FXU, LSU, Lat5], (instregex "LAN(G)?$")>;
493 def : InstRW<[FXU, LSU, Lat5], (instregex "LAO(G)?$")>;
494 def : InstRW<[FXU, LSU, Lat5], (instregex "LAX(G)?$")>;
495
496 // Compare and swap
497 def : InstRW<[FXU, LSU, FXU, Lat6, GroupAlone], (instregex "CS(G|Y)?$")>;
498
499 //===----------------------------------------------------------------------===//
500 // Access registers
501 //===----------------------------------------------------------------------===//
502
503 // Extract/set/copy access register
504 def : InstRW<[LSU], (instregex "(EAR|SAR|CPYA)$")>;
505
506 // Load address extended
507 def : InstRW<[LSU, FXU, Lat5, GroupAlone], (instregex "LAE(Y)?$")>;
508
509 // Load/store access multiple (not modeled precisely)
510 def : InstRW<[LSU, Lat30, GroupAlone], (instregex "(L|ST)AM(Y)?$")>;
511
512 //===----------------------------------------------------------------------===//
513 // Program mask and addressing mode
514 //===----------------------------------------------------------------------===//
515
516 // Insert Program Mask
517 def : InstRW<[FXU, Lat3, EndGroup], (instregex "IPM$")>;
518
519 // Set Program Mask
520 def : InstRW<[LSU, EndGroup], (instregex "SPM$")>;
521
522 // Branch and link
523 def : InstRW<[FXU, FXU, LSU, Lat8, GroupAlone], (instregex "BAL(R)?$")>;
524
525 // Test addressing mode
526 def : InstRW<[FXU], (instregex "TAM$")>;
527
528 // Set addressing mode
529 def : InstRW<[LSU, EndGroup], (instregex "SAM(24|31|64)$")>;
530
531 // Branch (and save) and set mode.
532 def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "BSM$")>;
533 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "BASSM$")>;
534
535 //===----------------------------------------------------------------------===//
536 // Miscellaneous Instructions.
537 //===----------------------------------------------------------------------===//
538
539 // Find leftmost one
540 def : InstRW<[FXU, Lat7, GroupAlone], (instregex "FLOGR$")>;
541
542 // Population count
543 def : InstRW<[FXU, Lat3], (instregex "POPCNT$")>;
544
545 // Extend
546 def : InstRW<[FXU], (instregex "AEXT128_64$")>;
547 def : InstRW<[FXU], (instregex "ZEXT128_(32|64)$")>;
548
549 // String instructions
550 def : InstRW<[FXU, LSU, Lat30], (instregex "SRST$")>;
551
552 // Move with key
553 def : InstRW<[LSU, Lat8, GroupAlone], (instregex "MVCK$")>;
554
555 // Extract CPU Time
556 def : InstRW<[FXU, Lat5, LSU], (instregex "ECTG$")>;
557
558 // Execute
559 def : InstRW<[LSU, GroupAlone], (instregex "EX(RL)?$")>;
560
561 // Program return
562 def : InstRW<[FXU, Lat30], (instregex "PR$")>;
563
564 // Inline assembly
565 def : InstRW<[FXU, LSU, Lat15], (instregex "STCK$")>;
566 def : InstRW<[FXU, LSU, Lat12], (instregex "STCKF$")>;
567 def : InstRW<[LSU, FXU, Lat5], (instregex "STCKE$")>;
568 def : InstRW<[FXU, LSU, Lat5], (instregex "STFLE$")>;
569 def : InstRW<[FXU, Lat30], (instregex "SVC$")>;
570
571 // Store real address
572 def : InstRW<[FXU, LSU, Lat5], (instregex "STRAG$")>;
573
574 //===----------------------------------------------------------------------===//
575 // .insn directive instructions
576 //===----------------------------------------------------------------------===//
577
578 // An "empty" sched-class will be assigned instead of the "invalid sched-class".
579 // getNumDecoderSlots() will then return 1 instead of 0.
580 def : InstRW<[], (instregex "Insn.*")>;
581
582
583 // ----------------------------- Floating point ----------------------------- //
584
585 //===----------------------------------------------------------------------===//
586 // FP: Select instructions
587 //===----------------------------------------------------------------------===//
588
589 def : InstRW<[FXU], (instregex "SelectF(32|64|128)$")>;
590 def : InstRW<[FXU], (instregex "CondStoreF32(Inv)?$")>;
591 def : InstRW<[FXU], (instregex "CondStoreF64(Inv)?$")>;
592
593 //===----------------------------------------------------------------------===//
594 // FP: Move instructions
595 //===----------------------------------------------------------------------===//
596
597 // Load zero
598 def : InstRW<[FXU], (instregex "LZ(DR|ER)$")>;
599 def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LZXR$")>;
600
601 // Load
602 def : InstRW<[FXU], (instregex "LER$")>;
603 def : InstRW<[FXU], (instregex "LD(R|R32|GR)$")>;
604 def : InstRW<[FXU, Lat3], (instregex "LGDR$")>;
605 def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LXR$")>;
606
607 // Load and Test
608 def : InstRW<[FPU], (instregex "LT(D|E)BR$")>;
609 def : InstRW<[FPU], (instregex "LTEBRCompare(_VecPseudo)?$")>;
610 def : InstRW<[FPU], (instregex "LTDBRCompare(_VecPseudo)?$")>;
611 def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], (instregex "LTXBR$")>;
612 def : InstRW<[FPU2, FPU2, Lat9, GroupAlone],
613 (instregex "LTXBRCompare(_VecPseudo)?$")>;
614
615 // Copy sign
616 def : InstRW<[FXU, FXU, Lat5, GroupAlone], (instregex "CPSDRd(d|s)$")>;
617 def : InstRW<[FXU, FXU, Lat5, GroupAlone], (instregex "CPSDRs(d|s)$")>;
618
619 //===----------------------------------------------------------------------===//
620 // FP: Load instructions
621 //===----------------------------------------------------------------------===//
622
623 def : InstRW<[LSU], (instregex "LE(Y)?$")>;
624 def : InstRW<[LSU], (instregex "LD(Y|E32)?$")>;
625 def : InstRW<[LSU], (instregex "LX$")>;
626
627 //===----------------------------------------------------------------------===//
628 // FP: Store instructions
629 //===----------------------------------------------------------------------===//
630
631 def : InstRW<[FXU, LSU, Lat7], (instregex "STD(Y)?$")>;
632 def : InstRW<[FXU, LSU, Lat7], (instregex "STE(Y)?$")>;
633 def : InstRW<[FXU, LSU, Lat5], (instregex "STX$")>;
634
635 //===----------------------------------------------------------------------===//
636 // FP: Conversion instructions
637 //===----------------------------------------------------------------------===//
638
639 // Load rounded
640 def : InstRW<[FPU], (instregex "LEDBR(A)?$")>;
641 def : InstRW<[FPU, FPU, Lat20], (instregex "LEXBR(A)?$")>;
642 def : InstRW<[FPU, FPU, Lat20], (instregex "LDXBR(A)?$")>;
643
644 // Load lengthened
645 def : InstRW<[FPU, LSU, Lat12], (instregex "LDEB$")>;
646 def : InstRW<[FPU], (instregex "LDEBR$")>;
647 def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "LX(D|E)B$")>;
648 def : InstRW<[FPU2, FPU2, Lat10, GroupAlone], (instregex "LX(D|E)BR$")>;
649
650 // Convert from fixed / logical
651 def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CE(F|G)BR(A)?$")>;
652 def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CD(F|G)BR(A)?$")>;
653 def : InstRW<[FXU, FPU2, FPU2, Lat11, GroupAlone], (instregex "CX(F|G)BR(A)?$")>;
654 def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CEL(F|G)BR$")>;
655 def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CDL(F|G)BR$")>;
656 def : InstRW<[FXU, FPU2, FPU2, Lat11, GroupAlone], (instregex "CXL(F|G)BR$")>;
657
658 // Convert to fixed / logical
659 def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CF(E|D)BR(A)?$")>;
660 def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CG(E|D)BR(A)?$")>;
661 def : InstRW<[FXU, FPU, FPU, Lat20, GroupAlone], (instregex "C(F|G)XBR(A)?$")>;
662 def : InstRW<[FXU, FPU, Lat11, GroupAlone], (instregex "CLF(E|D)BR$")>;
663 def : InstRW<[FXU, FPU, Lat11, GroupAlone], (instregex "CLG(E|D)BR$")>;
664 def : InstRW<[FXU, FPU, FPU, Lat20, GroupAlone], (instregex "CL(F|G)XBR$")>;
665
666 //===----------------------------------------------------------------------===//
667 // FP: Unary arithmetic
668 //===----------------------------------------------------------------------===//
669
670 // Load Complement / Negative / Positive
671 def : InstRW<[FPU], (instregex "L(C|N|P)DBR$")>;
672 def : InstRW<[FPU], (instregex "L(C|N|P)EBR$")>;
673 def : InstRW<[FXU], (instregex "LCDFR(_32)?$")>;
674 def : InstRW<[FXU], (instregex "LNDFR(_32)?$")>;
675 def : InstRW<[FXU], (instregex "LPDFR(_32)?$")>;
676 def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], (instregex "L(C|N|P)XBR$")>;
677
678 // Square root
679 def : InstRW<[FPU, LSU, Lat30], (instregex "SQ(E|D)B$")>;
680 def : InstRW<[FPU, Lat30], (instregex "SQ(E|D)BR$")>;
681 def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "SQXBR$")>;
682
683 // Load FP integer
684 def : InstRW<[FPU], (instregex "FIEBR(A)?$")>;
685 def : InstRW<[FPU], (instregex "FIDBR(A)?$")>;
686 def : InstRW<[FPU2, FPU2, Lat15, GroupAlone], (instregex "FIXBR(A)?$")>;
687
688 //===----------------------------------------------------------------------===//
689 // FP: Binary arithmetic
690 //===----------------------------------------------------------------------===//
691
692 // Addition
693 def : InstRW<[FPU, LSU, Lat12], (instregex "A(E|D)B$")>;
694 def : InstRW<[FPU], (instregex "A(E|D)BR$")>;
695 def : InstRW<[FPU2, FPU2, Lat20, GroupAlone], (instregex "AXBR$")>;
696
697 // Subtraction
698 def : InstRW<[FPU, LSU, Lat12], (instregex "S(E|D)B$")>;
699 def : InstRW<[FPU], (instregex "S(E|D)BR$")>;
700 def : InstRW<[FPU2, FPU2, Lat20, GroupAlone], (instregex "SXBR$")>;
701
702 // Multiply
703 def : InstRW<[FPU, LSU, Lat12], (instregex "M(D|DE|EE)B$")>;
704 def : InstRW<[FPU], (instregex "M(D|DE|EE)BR$")>;
705 def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "MXDB$")>;
706 def : InstRW<[FPU2, FPU2, Lat10, GroupAlone], (instregex "MXDBR$")>;
707 def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "MXBR$")>;
708
709 // Multiply and add / subtract
710 def : InstRW<[FPU, LSU, Lat12, GroupAlone], (instregex "M(A|S)EB$")>;
711 def : InstRW<[FPU, GroupAlone], (instregex "M(A|S)EBR$")>;
712 def : InstRW<[FPU, LSU, Lat12, GroupAlone], (instregex "M(A|S)DB$")>;
713 def : InstRW<[FPU, GroupAlone], (instregex "M(A|S)DBR$")>;
714
715 // Division
716 def : InstRW<[FPU, LSU, Lat30], (instregex "D(E|D)B$")>;
717 def : InstRW<[FPU, Lat30], (instregex "D(E|D)BR$")>;
718 def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "DXBR$")>;
719
720 //===----------------------------------------------------------------------===//
721 // FP: Comparisons
722 //===----------------------------------------------------------------------===//
723
724 // Compare
725 def : InstRW<[FPU, LSU, Lat12], (instregex "C(E|D)B$")>;
726 def : InstRW<[FPU], (instregex "C(E|D)BR$")>;
727 def : InstRW<[FPU, FPU, Lat30], (instregex "CXBR$")>;
728
729 // Test Data Class
730 def : InstRW<[FPU, LSU, Lat15], (instregex "TC(E|D)B$")>;
731 def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "TCXB$")>;
732
733 }
734