Mercurial > hg > CbC > CbC_llvm

comparison lib/Target/SystemZ/SystemZTargetMachine.cpp @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents 7d135dc70f03
children 803732b1fca8
comparison
equal deleted inserted replaced
101:34baf5011add 120:1172e4bd9c6f
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 9
10 #include "SystemZTargetMachine.h" 10 #include "SystemZTargetMachine.h"
11 #include "SystemZTargetTransformInfo.h" 11 #include "SystemZTargetTransformInfo.h"
12 #include "SystemZMachineScheduler.h"
12 #include "llvm/CodeGen/Passes.h" 13 #include "llvm/CodeGen/Passes.h"
14 #include "llvm/CodeGen/TargetPassConfig.h"
13 #include "llvm/Support/TargetRegistry.h" 15 #include "llvm/Support/TargetRegistry.h"
14 #include "llvm/Transforms/Scalar.h" 16 #include "llvm/Transforms/Scalar.h"
15 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 17 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
16 18
17 using namespace llvm; 19 using namespace llvm;
18 20
19 extern cl::opt<bool> MISchedPostRA;
20 extern "C" void LLVMInitializeSystemZTarget() { 21 extern "C" void LLVMInitializeSystemZTarget() {
21 // Register the target. 22 // Register the target.
22 RegisterTargetMachine<SystemZTargetMachine> X(TheSystemZTarget); 23 RegisterTargetMachine<SystemZTargetMachine> X(getTheSystemZTarget());
23 } 24 }
24 25
25 // Determine whether we use the vector ABI. 26 // Determine whether we use the vector ABI.
26 static bool UsesVectorABI(StringRef CPU, StringRef FS) { 27 static bool UsesVectorABI(StringRef CPU, StringRef FS) {
27 // We use the vector ABI whenever the vector facility is avaiable. 28 // We use the vector ABI whenever the vector facility is avaiable.
77 Ret += "-n32:64"; 78 Ret += "-n32:64";
78 79
79 return Ret; 80 return Ret;
80 } 81 }
81 82
83 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
84 // Static code is suitable for use in a dynamic executable; there is no
85 // separate DynamicNoPIC model.
86 if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
87 return Reloc::Static;
88 return *RM;
89 }
90
82 SystemZTargetMachine::SystemZTargetMachine(const Target &T, const Triple &TT, 91 SystemZTargetMachine::SystemZTargetMachine(const Target &T, const Triple &TT,
83 StringRef CPU, StringRef FS, 92 StringRef CPU, StringRef FS,
84 const TargetOptions &Options, 93 const TargetOptions &Options,
85 Reloc::Model RM, CodeModel::Model CM, 94 Optional<Reloc::Model> RM,
95 CodeModel::Model CM,
86 CodeGenOpt::Level OL) 96 CodeGenOpt::Level OL)
87 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options, 97 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options,
88 RM, CM, OL), 98 getEffectiveRelocModel(RM), CM, OL),
89 TLOF(make_unique<TargetLoweringObjectFileELF>()), 99 TLOF(make_unique<TargetLoweringObjectFileELF>()),
90 Subtarget(TT, CPU, FS, *this) { 100 Subtarget(TT, CPU, FS, *this) {
91 initAsmInfo(); 101 initAsmInfo();
92 } 102 }
93 103
102 112
103 SystemZTargetMachine &getSystemZTargetMachine() const { 113 SystemZTargetMachine &getSystemZTargetMachine() const {
104 return getTM<SystemZTargetMachine>(); 114 return getTM<SystemZTargetMachine>();
105 } 115 }
106 116
117 ScheduleDAGInstrs *
118 createPostMachineScheduler(MachineSchedContext *C) const override {
119 return new ScheduleDAGMI(C, make_unique<SystemZPostRASchedStrategy>(C),
120 /*RemoveKillFlags=*/true);
121 }
122
107 void addIRPasses() override; 123 void addIRPasses() override;
108 bool addInstSelector() override; 124 bool addInstSelector() override;
109 void addPreSched2() override; 125 void addPreSched2() override;
110 void addPreEmitPass() override; 126 void addPreEmitPass() override;
111 }; 127 };
112 } // end anonymous namespace 128 } // end anonymous namespace
113 129
114 void SystemZPassConfig::addIRPasses() { 130 void SystemZPassConfig::addIRPasses() {
131 if (getOptLevel() != CodeGenOpt::None)
132 addPass(createSystemZTDCPass());
133
115 TargetPassConfig::addIRPasses(); 134 TargetPassConfig::addIRPasses();
116 } 135 }
117 136
118 bool SystemZPassConfig::addInstSelector() { 137 bool SystemZPassConfig::addInstSelector() {
119 addPass(createSystemZISelDag(getSystemZTargetMachine(), getOptLevel())); 138 addPass(createSystemZISelDag(getSystemZTargetMachine(), getOptLevel()));
123 142
124 return false; 143 return false;
125 } 144 }
126 145
127 void SystemZPassConfig::addPreSched2() { 146 void SystemZPassConfig::addPreSched2() {
128 if (getOptLevel() != CodeGenOpt::None && 147 if (getOptLevel() != CodeGenOpt::None)
129 getSystemZTargetMachine().getSubtargetImpl()->hasLoadStoreOnCond())
130 addPass(&IfConverterID); 148 addPass(&IfConverterID);
131 } 149 }
132 150
133 void SystemZPassConfig::addPreEmitPass() { 151 void SystemZPassConfig::addPreEmitPass() {
134 152
166 addPass(createSystemZLongBranchPass(getSystemZTargetMachine())); 184 addPass(createSystemZLongBranchPass(getSystemZTargetMachine()));
167 185
168 // Do final scheduling after all other optimizations, to get an 186 // Do final scheduling after all other optimizations, to get an
169 // optimal input for the decoder (branch relaxation must happen 187 // optimal input for the decoder (branch relaxation must happen
170 // after block placement). 188 // after block placement).
171 if (getOptLevel() != CodeGenOpt::None) { 189 if (getOptLevel() != CodeGenOpt::None)
172 if (MISchedPostRA) 190 addPass(&PostMachineSchedulerID);
173 addPass(&PostMachineSchedulerID);
174 else
175 addPass(&PostRASchedulerID);
176 }
177 } 191 }
178 192
179 TargetPassConfig *SystemZTargetMachine::createPassConfig(PassManagerBase &PM) { 193 TargetPassConfig *SystemZTargetMachine::createPassConfig(PassManagerBase &PM) {
180 return new SystemZPassConfig(this, PM); 194 return new SystemZPassConfig(this, PM);
181 } 195 }