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comparison test/CodeGen/AArch64/arm64-extern-weak.ll @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents afa8332a0e37
children 803732b1fca8
comparison
equal deleted inserted replaced
101:34baf5011add 120:1172e4bd9c6f
1 ; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -o - < %s | FileCheck %s 1 ; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -o - < %s | FileCheck %s
2 ; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=static -o - < %s | FileCheck --check-prefix=CHECK-STATIC %s 2 ; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=static -o - < %s | FileCheck --check-prefix=CHECK %s
3 ; RUN: llc -mtriple=arm64-none-linux-gnu -code-model=large -o - < %s | FileCheck --check-prefix=CHECK-LARGE %s 3 ; RUN: llc -mtriple=arm64-none-linux-gnu -code-model=large -o - < %s | FileCheck --check-prefix=CHECK-LARGE %s
4 4
5 declare extern_weak i32 @var() 5 declare extern_weak i32 @var()
6 6
7 define i32()* @foo() { 7 define i32()* @foo() {
10 ; otherwise a litpool entry. 10 ; otherwise a litpool entry.
11 ret i32()* @var 11 ret i32()* @var
12 12
13 ; CHECK: adrp x[[VAR:[0-9]+]], :got:var 13 ; CHECK: adrp x[[VAR:[0-9]+]], :got:var
14 ; CHECK: ldr x0, [x[[VAR]], :got_lo12:var] 14 ; CHECK: ldr x0, [x[[VAR]], :got_lo12:var]
15
16 ; CHECK-STATIC: .LCPI0_0:
17 ; CHECK-STATIC-NEXT: .xword var
18 ; CHECK-STATIC: adrp x[[VAR:[0-9]+]], .LCPI0_0
19 ; CHECK-STATIC: ldr x0, [x[[VAR]], :lo12:.LCPI0_0]
20 15
21 ; In the large model, the usual relocations are absolute and can 16 ; In the large model, the usual relocations are absolute and can
22 ; materialise 0. 17 ; materialise 0.
23 ; CHECK-LARGE: movz x0, #:abs_g3:var 18 ; CHECK-LARGE: movz x0, #:abs_g3:var
24 ; CHECK-LARGE: movk x0, #:abs_g2_nc:var 19 ; CHECK-LARGE: movk x0, #:abs_g2_nc:var
34 ; CHECK: adrp x[[ARR_VAR_HI:[0-9]+]], :got:arr_var 29 ; CHECK: adrp x[[ARR_VAR_HI:[0-9]+]], :got:arr_var
35 ; CHECK: ldr [[ARR_VAR:x[0-9]+]], [x[[ARR_VAR_HI]], :got_lo12:arr_var] 30 ; CHECK: ldr [[ARR_VAR:x[0-9]+]], [x[[ARR_VAR_HI]], :got_lo12:arr_var]
36 ; CHECK: add x0, [[ARR_VAR]], #20 31 ; CHECK: add x0, [[ARR_VAR]], #20
37 ret i32* %addr 32 ret i32* %addr
38 33
39 ; CHECK-STATIC: .LCPI1_0:
40 ; CHECK-STATIC-NEXT: .xword arr_var
41 ; CHECK-STATIC: ldr [[BASE:x[0-9]+]], [{{x[0-9]+}}, :lo12:.LCPI1_0]
42 ; CHECK-STATIC: add x0, [[BASE]], #20
43
44 ; In the large model, the usual relocations are absolute and can 34 ; In the large model, the usual relocations are absolute and can
45 ; materialise 0. 35 ; materialise 0.
46 ; CHECK-LARGE: movz [[ARR_VAR:x[0-9]+]], #:abs_g3:arr_var 36 ; CHECK-LARGE: movz [[ARR_VAR:x[0-9]+]], #:abs_g3:arr_var
47 ; CHECK-LARGE: movk [[ARR_VAR]], #:abs_g2_nc:arr_var 37 ; CHECK-LARGE: movk [[ARR_VAR]], #:abs_g2_nc:arr_var
48 ; CHECK-LARGE: movk [[ARR_VAR]], #:abs_g1_nc:arr_var 38 ; CHECK-LARGE: movk [[ARR_VAR]], #:abs_g1_nc:arr_var
54 define i32* @wibble() { 44 define i32* @wibble() {
55 ret i32* @defined_weak_var 45 ret i32* @defined_weak_var
56 ; CHECK: adrp [[BASE:x[0-9]+]], defined_weak_var 46 ; CHECK: adrp [[BASE:x[0-9]+]], defined_weak_var
57 ; CHECK: add x0, [[BASE]], :lo12:defined_weak_var 47 ; CHECK: add x0, [[BASE]], :lo12:defined_weak_var
58 48
59 ; CHECK-STATIC: adrp [[BASE:x[0-9]+]], defined_weak_var
60 ; CHECK-STATIC: add x0, [[BASE]], :lo12:defined_weak_var
61
62 ; CHECK-LARGE: movz x0, #:abs_g3:defined_weak_var 49 ; CHECK-LARGE: movz x0, #:abs_g3:defined_weak_var
63 ; CHECK-LARGE: movk x0, #:abs_g2_nc:defined_weak_var 50 ; CHECK-LARGE: movk x0, #:abs_g2_nc:defined_weak_var
64 ; CHECK-LARGE: movk x0, #:abs_g1_nc:defined_weak_var 51 ; CHECK-LARGE: movk x0, #:abs_g1_nc:defined_weak_var
65 ; CHECK-LARGE: movk x0, #:abs_g0_nc:defined_weak_var 52 ; CHECK-LARGE: movk x0, #:abs_g0_nc:defined_weak_var
66 } 53 }