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comparison test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents 54457678186b
children 803732b1fca8
comparison
equal deleted inserted replaced
101:34baf5011add 120:1172e4bd9c6f
6 ; 6 ;
7 ; CHECK: ********** MI Scheduling ********** 7 ; CHECK: ********** MI Scheduling **********
8 ; CHECK: shiftable 8 ; CHECK: shiftable
9 ; CHECK: SU(2): %vreg2<def> = SUBXri %vreg1, 20, 0 9 ; CHECK: SU(2): %vreg2<def> = SUBXri %vreg1, 20, 0
10 ; CHECK: Successors: 10 ; CHECK: Successors:
11 ; CHECK-NEXT: val SU(4): Latency=1 Reg=%vreg2 11 ; CHECK-NEXT: data SU(4): Latency=1 Reg=%vreg2
12 ; CHECK-NEXT: val SU(3): Latency=2 Reg=%vreg2 12 ; CHECK-NEXT: data SU(3): Latency=2 Reg=%vreg2
13 ; CHECK: ********** INTERVALS ********** 13 ; CHECK: ********** INTERVALS **********
14 define i64 @shiftable(i64 %A, i64 %B) { 14 define i64 @shiftable(i64 %A, i64 %B) {
15 %tmp0 = sub i64 %B, 20 15 %tmp0 = sub i64 %B, 20
16 %tmp1 = shl i64 %tmp0, 5; 16 %tmp1 = shl i64 %tmp0, 5;
17 %tmp2 = add i64 %A, %tmp1; 17 %tmp2 = add i64 %A, %tmp1;