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comparison test/CodeGen/AArch64/tailcall_misched_graph.ll @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents afa8332a0e37
children 803732b1fca8
comparison
equal deleted inserted replaced
101:34baf5011add 120:1172e4bd9c6f
35 ; Without this edge the scheduler would be free to move the store accross the load. 35 ; Without this edge the scheduler would be free to move the store accross the load.
36 36
37 ; CHECK: SU({{.*}}): [[VRB]]<def> = LDRXui <fi#-2> 37 ; CHECK: SU({{.*}}): [[VRB]]<def> = LDRXui <fi#-2>
38 ; CHECK-NOT: SU 38 ; CHECK-NOT: SU
39 ; CHECK: Successors: 39 ; CHECK: Successors:
40 ; CHECK: ch SU([[DEPSTORE:.*]]): Latency=0 40 ; CHECK: ord SU([[DEPSTOREB:.*]]): Latency=0
41 ; CHECK: ord SU([[DEPSTOREA:.*]]): Latency=0
41 42
42 ; CHECK: SU([[DEPSTORE]]): STRXui %vreg0, <fi#-4> 43 ; CHECK: SU([[DEPSTOREA]]): STRXui %vreg{{.*}}, <fi#-4>
44 ; CHECK: SU([[DEPSTOREB]]): STRXui %vreg{{.*}}, <fi#-3>