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comparison test/CodeGen/AMDGPU/bitreverse.ll @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents 7d135dc70f03
children 803732b1fca8
comparison
equal deleted inserted replaced
101:34baf5011add 120:1172e4bd9c6f
1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s 1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s 2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
3 ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC %s
3 4
4 declare i16 @llvm.bitreverse.i16(i16) #1 5 declare i16 @llvm.bitreverse.i16(i16) #1
5 declare i32 @llvm.bitreverse.i32(i32) #1 6 declare i32 @llvm.bitreverse.i32(i32) #1
6 declare i64 @llvm.bitreverse.i64(i64) #1 7 declare i64 @llvm.bitreverse.i64(i64) #1
7 8
9 declare <4 x i32> @llvm.bitreverse.v4i32(<4 x i32>) #1 10 declare <4 x i32> @llvm.bitreverse.v4i32(<4 x i32>) #1
10 11
11 declare <2 x i64> @llvm.bitreverse.v2i64(<2 x i64>) #1 12 declare <2 x i64> @llvm.bitreverse.v2i64(<2 x i64>) #1
12 declare <4 x i64> @llvm.bitreverse.v4i64(<4 x i64>) #1 13 declare <4 x i64> @llvm.bitreverse.v4i64(<4 x i64>) #1
13 14
14 declare i32 @llvm.AMDGPU.brev(i32) #1
15
16 ; FUNC-LABEL: {{^}}s_brev_i16: 15 ; FUNC-LABEL: {{^}}s_brev_i16:
17 ; SI: s_brev_b32 16 ; SI: s_brev_b32
18 define void @s_brev_i16(i16 addrspace(1)* noalias %out, i16 %val) #0 { 17 define void @s_brev_i16(i16 addrspace(1)* noalias %out, i16 %val) #0 {
19 %brev = call i16 @llvm.bitreverse.i16(i16 %val) #1 18 %brev = call i16 @llvm.bitreverse.i16(i16 %val) #1
20 store i16 %brev, i16 addrspace(1)* %out 19 store i16 %brev, i16 addrspace(1)* %out
21 ret void 20 ret void
22 } 21 }
79 store i64 %brev, i64 addrspace(1)* %out 78 store i64 %brev, i64 addrspace(1)* %out
80 ret void 79 ret void
81 } 80 }
82 81
83 ; FUNC-LABEL: {{^}}v_brev_i64: 82 ; FUNC-LABEL: {{^}}v_brev_i64:
83 ; SI-NOT: v_or_b32_e64 v{{[0-9]+}}, 0, 0
84 define void @v_brev_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %valptr) #0 { 84 define void @v_brev_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %valptr) #0 {
85 %val = load i64, i64 addrspace(1)* %valptr 85 %val = load i64, i64 addrspace(1)* %valptr
86 %brev = call i64 @llvm.bitreverse.i64(i64 %val) #1 86 %brev = call i64 @llvm.bitreverse.i64(i64 %val) #1
87 store i64 %brev, i64 addrspace(1)* %out 87 store i64 %brev, i64 addrspace(1)* %out
88 ret void 88 ret void
101 %brev = call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> %val) #1 101 %brev = call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> %val) #1
102 store <2 x i64> %brev, <2 x i64> addrspace(1)* %out 102 store <2 x i64> %brev, <2 x i64> addrspace(1)* %out
103 ret void 103 ret void
104 } 104 }
105 105
106 ; FUNC-LABEL: {{^}}legacy_s_brev_i32:
107 ; SI: s_brev_b32
108 define void @legacy_s_brev_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind {
109 %brev = call i32 @llvm.AMDGPU.brev(i32 %val) #1
110 store i32 %brev, i32 addrspace(1)* %out
111 ret void
112 }
113
114 attributes #0 = { nounwind } 106 attributes #0 = { nounwind }
115 attributes #1 = { nounwind readnone } 107 attributes #1 = { nounwind readnone }