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comparison test/CodeGen/AMDGPU/floor.ll @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents afa8332a0e37
children
comparison
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101:34baf5011add 120:1172e4bd9c6f
1 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s 1 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s
2 2
3 ; CHECK: FLOOR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 3 ; CHECK: FLOOR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
4 define void @test(<4 x float> inreg %reg0) #0 { 4 define amdgpu_ps void @test(<4 x float> inreg %reg0) {
5 %r0 = extractelement <4 x float> %reg0, i32 0 5 %r0 = extractelement <4 x float> %reg0, i32 0
6 %r1 = call float @floor(float %r0) 6 %r1 = call float @floor(float %r0)
7 %vec = insertelement <4 x float> undef, float %r1, i32 0 7 %vec = insertelement <4 x float> undef, float %r1, i32 0
8 call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) 8 call void @llvm.r600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
9 ret void 9 ret void
10 } 10 }
11 11
12 declare float @floor(float) readonly 12 declare float @floor(float) readonly
13 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) 13 declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)
14 14
15 attributes #0 = { "ShaderType"="0" }