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comparison test/CodeGen/AMDGPU/fptosi.f16.ll @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
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children 803732b1fca8
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101:34baf5011add 120:1172e4bd9c6f
1 ; RUN: llc -march=amdgcn -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
2 ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
3
4 ; GCN-LABEL: {{^}}fptosi_f16_to_i16
5 ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
6 ; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
7 ; GCN: v_cvt_i32_f32_e32 v[[R_I16:[0-9]+]], v[[A_F32]]
8 ; GCN: buffer_store_short v[[R_I16]]
9 ; GCN: s_endpgm
10 define void @fptosi_f16_to_i16(
11 i16 addrspace(1)* %r,
12 half addrspace(1)* %a) {
13 entry:
14 %a.val = load half, half addrspace(1)* %a
15 %r.val = fptosi half %a.val to i16
16 store i16 %r.val, i16 addrspace(1)* %r
17 ret void
18 }
19
20 ; GCN-LABEL: {{^}}fptosi_f16_to_i32
21 ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
22 ; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
23 ; GCN: v_cvt_i32_f32_e32 v[[R_I32:[0-9]+]], v[[A_F32]]
24 ; GCN: buffer_store_dword v[[R_I32]]
25 ; GCN: s_endpgm
26 define void @fptosi_f16_to_i32(
27 i32 addrspace(1)* %r,
28 half addrspace(1)* %a) {
29 entry:
30 %a.val = load half, half addrspace(1)* %a
31 %r.val = fptosi half %a.val to i32
32 store i32 %r.val, i32 addrspace(1)* %r
33 ret void
34 }
35
36 ; Need to make sure we promote f16 to f32 when converting f16 to i64. Existing
37 ; test checks code generated for 'i64 = fp_to_sint f32'.
38
39 ; GCN-LABEL: {{^}}fptosi_f16_to_i64
40 ; GCN: buffer_load_ushort
41 ; GCN: v_cvt_f32_f16_e32
42 ; GCN: s_endpgm
43 define void @fptosi_f16_to_i64(
44 i64 addrspace(1)* %r,
45 half addrspace(1)* %a) {
46 entry:
47 %a.val = load half, half addrspace(1)* %a
48 %r.val = fptosi half %a.val to i64
49 store i64 %r.val, i64 addrspace(1)* %r
50 ret void
51 }
52
53 ; GCN-LABEL: {{^}}fptosi_v2f16_to_v2i16
54 ; GCN: buffer_load_dword v[[A_V2_F16:[0-9]+]]
55 ; GCN: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
56 ; GCN: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]]
57 ; GCN: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]]
58 ; GCN: v_cvt_i32_f32_e32 v[[R_I16_0:[0-9]+]], v[[A_F32_0]]
59 ; GCN: v_cvt_i32_f32_e32 v[[R_I16_1:[0-9]+]], v[[A_F32_1]]
60 ; GCN: v_and_b32_e32 v[[R_I16_LO:[0-9]+]], 0xffff, v[[R_I16_0]]
61 ; GCN: v_lshlrev_b32_e32 v[[R_I16_HI:[0-9]+]], 16, v[[R_I16_1]]
62 ; GCN: v_or_b32_e32 v[[R_V2_I16:[0-9]+]], v[[R_I16_HI]], v[[R_I16_LO]]
63 ; GCN: buffer_store_dword v[[R_V2_I16]]
64 ; GCN: s_endpgm
65 define void @fptosi_v2f16_to_v2i16(
66 <2 x i16> addrspace(1)* %r,
67 <2 x half> addrspace(1)* %a) {
68 entry:
69 %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
70 %r.val = fptosi <2 x half> %a.val to <2 x i16>
71 store <2 x i16> %r.val, <2 x i16> addrspace(1)* %r
72 ret void
73 }
74
75 ; GCN-LABEL: {{^}}fptosi_v2f16_to_v2i32
76 ; GCN: buffer_load_dword
77 ; GCN: v_cvt_f32_f16_e32
78 ; GCN: v_cvt_f32_f16_e32
79 ; GCN: v_cvt_i32_f32_e32
80 ; GCN: v_cvt_i32_f32_e32
81 ; GCN: buffer_store_dwordx2
82 ; GCN: s_endpgm
83 define void @fptosi_v2f16_to_v2i32(
84 <2 x i32> addrspace(1)* %r,
85 <2 x half> addrspace(1)* %a) {
86 entry:
87 %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
88 %r.val = fptosi <2 x half> %a.val to <2 x i32>
89 store <2 x i32> %r.val, <2 x i32> addrspace(1)* %r
90 ret void
91 }
92
93 ; Need to make sure we promote f16 to f32 when converting f16 to i64. Existing
94 ; test checks code generated for 'i64 = fp_to_sint f32'.
95
96 ; GCN-LABEL: {{^}}fptosi_v2f16_to_v2i64
97 ; GCN: buffer_load_dword
98 ; GCN: v_cvt_f32_f16_e32
99 ; GCN: v_cvt_f32_f16_e32
100 ; GCN: s_endpgm
101 define void @fptosi_v2f16_to_v2i64(
102 <2 x i64> addrspace(1)* %r,
103 <2 x half> addrspace(1)* %a) {
104 entry:
105 %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
106 %r.val = fptosi <2 x half> %a.val to <2 x i64>
107 store <2 x i64> %r.val, <2 x i64> addrspace(1)* %r
108 ret void
109 }