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comparison test/CodeGen/Mips/fcmp.ll @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents afa8332a0e37
children 803732b1fca8
comparison
equal deleted inserted replaced
101:34baf5011add 120:1172e4bd9c6f
1 ; RUN: llc < %s -march=mips -mcpu=mips32 | \ 1 ; RUN: llc < %s -march=mips -mcpu=mips32 | \
2 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32-C 2 ; RUN: FileCheck %s -check-prefixes=ALL,32-C
3 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | \ 3 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | \
4 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32-C 4 ; RUN: FileCheck %s -check-prefixes=ALL,32-C
5 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | \ 5 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | \
6 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32-CMP 6 ; RUN: FileCheck %s -check-prefixes=ALL,32-CMP
7 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | \ 7 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | \
8 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64-C 8 ; RUN: FileCheck %s -check-prefixes=ALL,64-C
9 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | \ 9 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | \
10 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64-C 10 ; RUN: FileCheck %s -check-prefixes=ALL,64-C
11 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | \ 11 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | \
12 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64-C 12 ; RUN: FileCheck %s -check-prefixes=ALL,64-C
13 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | \ 13 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | \
14 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64-CMP 14 ; RUN: FileCheck %s -check-prefixes=ALL,64-CMP
15 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
16 ; RUN: -check-prefixes=ALL,MM,MM32R3
17 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
18 ; RUN: -check-prefixes=ALL,MM,MMR6,MM32R6
19 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \
20 ; RUN: -check-prefixes=ALL,MM,MMR6,MM64R6
15 21
16 define i32 @false_f32(float %a, float %b) nounwind { 22 define i32 @false_f32(float %a, float %b) nounwind {
17 ; ALL-LABEL: false_f32: 23 ; ALL-LABEL: false_f32:
18 ; ALL: addiu $2, $zero, 0 24 ; 32-C: addiu $2, $zero, 0
25
26 ; 32-CMP: addiu $2, $zero, 0
27
28 ; 64-C: addiu $2, $zero, 0
29
30 ; 64-CMP: addiu $2, $zero, 0
31
32 ; MM-DAG: li16 $2, 0
19 33
20 %1 = fcmp false float %a, %b 34 %1 = fcmp false float %a, %b
21 %2 = zext i1 %1 to i32 35 %2 = zext i1 %1 to i32
22 ret i32 %2 36 ret i32 %2
23 } 37 }
39 53
40 ; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13 54 ; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
41 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] 55 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
42 ; 64-CMP-DAG: andi $2, $[[T1]], 1 56 ; 64-CMP-DAG: andi $2, $[[T1]], 1
43 57
58 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
59 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
60 ; MM32R3-DAG: c.eq.s $f12, $f14
61 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
62
63 ; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
64 ; MM64R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
65 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
66 ; MMR6-DAG: andi16 $2, $[[T1]], 1
67
44 %1 = fcmp oeq float %a, %b 68 %1 = fcmp oeq float %a, %b
45 %2 = zext i1 %1 to i32 69 %2 = zext i1 %1 to i32
46 ret i32 %2 70 ret i32 %2
47 } 71 }
48 72
63 87
64 ; 64-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12 88 ; 64-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12
65 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] 89 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
66 ; 64-CMP-DAG: andi $2, $[[T1]], 1 90 ; 64-CMP-DAG: andi $2, $[[T1]], 1
67 91
92 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
93 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
94 ; MM32R3-DAG: c.ule.s $f12, $f14
95 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
96
97 ; MM32R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12
98 ; MM64R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12
99 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
100 ; MMR6-DAG: andi16 $2, $[[T1]], 1
101
68 %1 = fcmp ogt float %a, %b 102 %1 = fcmp ogt float %a, %b
69 %2 = zext i1 %1 to i32 103 %2 = zext i1 %1 to i32
70 ret i32 %2 104 ret i32 %2
71 } 105 }
72 106
87 121
88 ; 64-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f13, $f12 122 ; 64-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f13, $f12
89 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] 123 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
90 ; 64-CMP-DAG: andi $2, $[[T1]], 1 124 ; 64-CMP-DAG: andi $2, $[[T1]], 1
91 125
126 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
127 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
128 ; MM32R3-DAG: c.ult.s $f12, $f14
129 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
130
131 ; MM32R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f14, $f12
132 ; MM64R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f13, $f12
133 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
134 ; MMR6-DAG: andi16 $2, $[[T1]], 1
135
92 %1 = fcmp oge float %a, %b 136 %1 = fcmp oge float %a, %b
93 %2 = zext i1 %1 to i32 137 %2 = zext i1 %1 to i32
94 ret i32 %2 138 ret i32 %2
95 } 139 }
96 140
111 155
112 ; 64-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13 156 ; 64-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13
113 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] 157 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
114 ; 64-CMP-DAG: andi $2, $[[T1]], 1 158 ; 64-CMP-DAG: andi $2, $[[T1]], 1
115 159
160 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
161 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
162 ; MM32R3-DAG: c.olt.s $f12, $f14
163 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
164
165 ; MM32R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14
166 ; MM64R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13
167 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
168 ; MMR6-DAG: andi16 $2, $[[T1]], 1
169
116 %1 = fcmp olt float %a, %b 170 %1 = fcmp olt float %a, %b
117 %2 = zext i1 %1 to i32 171 %2 = zext i1 %1 to i32
118 ret i32 %2 172 ret i32 %2
119 } 173 }
120 174
135 189
136 ; 64-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f13 190 ; 64-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f13
137 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] 191 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
138 ; 64-CMP-DAG: andi $2, $[[T1]], 1 192 ; 64-CMP-DAG: andi $2, $[[T1]], 1
139 193
194 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
195 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
196 ; MM32R3-DAG: c.ole.s $f12, $f14
197 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
198
199 ; MM32R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f14
200 ; MM64R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f13
201 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
202 ; MMR6-DAG: andi16 $2, $[[T1]], 1
203
140 %1 = fcmp ole float %a, %b 204 %1 = fcmp ole float %a, %b
141 %2 = zext i1 %1 to i32 205 %2 = zext i1 %1 to i32
142 ret i32 %2 206 ret i32 %2
143 } 207 }
144 208
161 ; 64-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13 225 ; 64-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
162 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] 226 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
163 ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] 227 ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
164 ; 64-CMP-DAG: andi $2, $[[T2]], 1 228 ; 64-CMP-DAG: andi $2, $[[T2]], 1
165 229
230 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
231 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
232 ; MM32R3-DAG: c.ueq.s $f12, $f14
233 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
234
235 ; MM32R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
236 ; MM64R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
237 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
238 ; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]]
239 ; MMR6-DAG: andi16 $2, $[[T2]], 1
240
166 %1 = fcmp one float %a, %b 241 %1 = fcmp one float %a, %b
167 %2 = zext i1 %1 to i32 242 %2 = zext i1 %1 to i32
168 ret i32 %2 243 ret i32 %2
169 } 244 }
170 245
187 ; 64-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13 262 ; 64-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
188 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] 263 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
189 ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] 264 ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
190 ; 64-CMP-DAG: andi $2, $[[T2]], 1 265 ; 64-CMP-DAG: andi $2, $[[T2]], 1
191 266
267 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
268 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
269 ; MM32R3-DAG: c.un.s $f12, $f14
270 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
271
272 ; MM32R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
273 ; MM64R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
274 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
275 ; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]]
276 ; MMR6-DAG: andi16 $2, $[[T2]], 1
277
192 %1 = fcmp ord float %a, %b 278 %1 = fcmp ord float %a, %b
193 %2 = zext i1 %1 to i32 279 %2 = zext i1 %1 to i32
194 ret i32 %2 280 ret i32 %2
195 } 281 }
196 282
211 297
212 ; 64-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13 298 ; 64-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
213 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] 299 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
214 ; 64-CMP-DAG: andi $2, $[[T1]], 1 300 ; 64-CMP-DAG: andi $2, $[[T1]], 1
215 301
302 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
303 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
304 ; MM32R3-DAG: c.ueq.s $f12, $f14
305 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
306
307 ; MM32R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
308 ; MM64R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
309 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
310 ; MMR6-DAG: andi16 $2, $[[T1]], 1
311
216 %1 = fcmp ueq float %a, %b 312 %1 = fcmp ueq float %a, %b
217 %2 = zext i1 %1 to i32 313 %2 = zext i1 %1 to i32
218 ret i32 %2 314 ret i32 %2
219 } 315 }
220 316
235 331
236 ; 64-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12 332 ; 64-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12
237 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] 333 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
238 ; 64-CMP-DAG: andi $2, $[[T1]], 1 334 ; 64-CMP-DAG: andi $2, $[[T1]], 1
239 335
336 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
337 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
338 ; MM32R3-DAG: c.ole.s $f12, $f14
339 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
340
341 ; MM32R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12
342 ; MM64R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12
343 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
344 ; MMR6-DAG: andi16 $2, $[[T1]], 1
345
240 %1 = fcmp ugt float %a, %b 346 %1 = fcmp ugt float %a, %b
241 %2 = zext i1 %1 to i32 347 %2 = zext i1 %1 to i32
242 ret i32 %2 348 ret i32 %2
243 } 349 }
244 350
259 365
260 ; 64-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12 366 ; 64-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12
261 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] 367 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
262 ; 64-CMP-DAG: andi $2, $[[T1]], 1 368 ; 64-CMP-DAG: andi $2, $[[T1]], 1
263 369
370 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
371 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
372 ; MM32R3-DAG: c.olt.s $f12, $f14
373 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
374
375 ; MM32R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12
376 ; MM64R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12
377 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
378 ; MMR6-DAG: andi16 $2, $[[T1]], 1
379
264 %1 = fcmp uge float %a, %b 380 %1 = fcmp uge float %a, %b
265 %2 = zext i1 %1 to i32 381 %2 = zext i1 %1 to i32
266 ret i32 %2 382 ret i32 %2
267 } 383 }
268 384
283 399
284 ; 64-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13 400 ; 64-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13
285 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] 401 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
286 ; 64-CMP-DAG: andi $2, $[[T1]], 1 402 ; 64-CMP-DAG: andi $2, $[[T1]], 1
287 403
404 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
405 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
406 ; MM32R3-DAG: c.ult.s $f12, $f14
407 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
408
409 ; MM32R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14
410 ; MM64R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13
411 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
412 ; MMR6-DAG: andi16 $2, $[[T1]], 1
288 413
289 %1 = fcmp ult float %a, %b 414 %1 = fcmp ult float %a, %b
290 %2 = zext i1 %1 to i32 415 %2 = zext i1 %1 to i32
291 ret i32 %2 416 ret i32 %2
292 } 417 }
308 433
309 ; 64-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13 434 ; 64-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13
310 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] 435 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
311 ; 64-CMP-DAG: andi $2, $[[T1]], 1 436 ; 64-CMP-DAG: andi $2, $[[T1]], 1
312 437
438 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
439 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
440 ; MM32R3-DAG: c.ule.s $f12, $f14
441 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
442
443 ; MM32R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14
444 ; MM64R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13
445 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
446 ; MMR6-DAG: andi16 $2, $[[T1]], 1
447
313 %1 = fcmp ule float %a, %b 448 %1 = fcmp ule float %a, %b
314 %2 = zext i1 %1 to i32 449 %2 = zext i1 %1 to i32
315 ret i32 %2 450 ret i32 %2
316 } 451 }
317 452
334 ; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13 469 ; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
335 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] 470 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
336 ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] 471 ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
337 ; 64-CMP-DAG: andi $2, $[[T2]], 1 472 ; 64-CMP-DAG: andi $2, $[[T2]], 1
338 473
474 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
475 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
476 ; MM32R3-DAG: c.eq.s $f12, $f14
477 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
478
479 ; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
480 ; MM64R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
481 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
482 ; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]]
483 ; MMR6-DAG: andi16 $2, $[[T2]], 1
484
339 %1 = fcmp une float %a, %b 485 %1 = fcmp une float %a, %b
340 %2 = zext i1 %1 to i32 486 %2 = zext i1 %1 to i32
341 ret i32 %2 487 ret i32 %2
342 } 488 }
343 489
358 504
359 ; 64-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13 505 ; 64-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
360 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] 506 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
361 ; 64-CMP-DAG: andi $2, $[[T1]], 1 507 ; 64-CMP-DAG: andi $2, $[[T1]], 1
362 508
509 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
510 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
511 ; MM32R3-DAG: c.un.s $f12, $f14
512 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
513
514 ; MM32R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
515 ; MM64R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
516 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
517 ; MMR6-DAG: andi16 $2, $[[T1]], 1
518
363 %1 = fcmp uno float %a, %b 519 %1 = fcmp uno float %a, %b
364 %2 = zext i1 %1 to i32 520 %2 = zext i1 %1 to i32
365 ret i32 %2 521 ret i32 %2
366 } 522 }
367 523
368 define i32 @true_f32(float %a, float %b) nounwind { 524 define i32 @true_f32(float %a, float %b) nounwind {
369 ; ALL-LABEL: true_f32: 525 ; ALL-LABEL: true_f32:
370 ; ALL: addiu $2, $zero, 1 526 ; 32-C: addiu $2, $zero, 1
527
528 ; 32-CMP: addiu $2, $zero, 1
529
530 ; 64-C: addiu $2, $zero, 1
531
532 ; 64-CMP: addiu $2, $zero, 1
533
534 ; MM-DAG: li16 $2, 1
371 535
372 %1 = fcmp true float %a, %b 536 %1 = fcmp true float %a, %b
373 %2 = zext i1 %1 to i32 537 %2 = zext i1 %1 to i32
374 ret i32 %2 538 ret i32 %2
375 } 539 }
376 540
377 define i32 @false_f64(double %a, double %b) nounwind { 541 define i32 @false_f64(double %a, double %b) nounwind {
378 ; ALL-LABEL: false_f64: 542 ; ALL-LABEL: false_f64:
379 ; ALL: addiu $2, $zero, 0 543 ; 32-C: addiu $2, $zero, 0
544
545 ; 32-CMP: addiu $2, $zero, 0
546
547 ; 64-C: addiu $2, $zero, 0
548
549 ; 64-CMP: addiu $2, $zero, 0
550
551 ; MM-DAG: li16 $2, 0
380 552
381 %1 = fcmp false double %a, %b 553 %1 = fcmp false double %a, %b
382 %2 = zext i1 %1 to i32 554 %2 = zext i1 %1 to i32
383 ret i32 %2 555 ret i32 %2
384 } 556 }
400 572
401 ; 64-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13 573 ; 64-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
402 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] 574 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
403 ; 64-CMP-DAG: andi $2, $[[T1]], 1 575 ; 64-CMP-DAG: andi $2, $[[T1]], 1
404 576
577 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
578 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
579 ; MM32R3-DAG: c.eq.d $f12, $f14
580 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
581
582 ; MM32R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
583 ; MM64R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
584 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
585 ; MMR6-DAG: andi16 $2, $[[T1]], 1
586
405 %1 = fcmp oeq double %a, %b 587 %1 = fcmp oeq double %a, %b
406 %2 = zext i1 %1 to i32 588 %2 = zext i1 %1 to i32
407 ret i32 %2 589 ret i32 %2
408 } 590 }
409 591
424 606
425 ; 64-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12 607 ; 64-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12
426 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] 608 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
427 ; 64-CMP-DAG: andi $2, $[[T1]], 1 609 ; 64-CMP-DAG: andi $2, $[[T1]], 1
428 610
611 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
612 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
613 ; MM32R3-DAG: c.ule.d $f12, $f14
614 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
615
616 ; MM32R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12
617 ; MM64R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12
618 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
619 ; MMR6-DAG: andi16 $2, $[[T1]], 1
620
429 %1 = fcmp ogt double %a, %b 621 %1 = fcmp ogt double %a, %b
430 %2 = zext i1 %1 to i32 622 %2 = zext i1 %1 to i32
431 ret i32 %2 623 ret i32 %2
432 } 624 }
433 625
448 640
449 ; 64-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f13, $f12 641 ; 64-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f13, $f12
450 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] 642 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
451 ; 64-CMP-DAG: andi $2, $[[T1]], 1 643 ; 64-CMP-DAG: andi $2, $[[T1]], 1
452 644
645 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
646 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
647 ; MM32R3-DAG: c.ult.d $f12, $f14
648 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
649
650 ; MM32R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f14, $f12
651 ; MM64R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f13, $f12
652 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
653 ; MMR6-DAG: andi16 $2, $[[T1]], 1
654
453 %1 = fcmp oge double %a, %b 655 %1 = fcmp oge double %a, %b
454 %2 = zext i1 %1 to i32 656 %2 = zext i1 %1 to i32
455 ret i32 %2 657 ret i32 %2
456 } 658 }
457 659
472 674
473 ; 64-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13 675 ; 64-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13
474 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] 676 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
475 ; 64-CMP-DAG: andi $2, $[[T1]], 1 677 ; 64-CMP-DAG: andi $2, $[[T1]], 1
476 678
679 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
680 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
681 ; MM32R3-DAG: c.olt.d $f12, $f14
682 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
683
684 ; MM32R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14
685 ; MM64R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13
686 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
687 ; MMR6-DAG: andi16 $2, $[[T1]], 1
688
477 %1 = fcmp olt double %a, %b 689 %1 = fcmp olt double %a, %b
478 %2 = zext i1 %1 to i32 690 %2 = zext i1 %1 to i32
479 ret i32 %2 691 ret i32 %2
480 } 692 }
481 693
496 708
497 ; 64-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f13 709 ; 64-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f13
498 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] 710 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
499 ; 64-CMP-DAG: andi $2, $[[T1]], 1 711 ; 64-CMP-DAG: andi $2, $[[T1]], 1
500 712
713 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
714 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
715 ; MM32R3-DAG: c.ole.d $f12, $f14
716 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
717
718 ; MM32R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f14
719 ; MM64R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f13
720 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
721 ; MMR6-DAG: andi16 $2, $[[T1]], 1
722
501 %1 = fcmp ole double %a, %b 723 %1 = fcmp ole double %a, %b
502 %2 = zext i1 %1 to i32 724 %2 = zext i1 %1 to i32
503 ret i32 %2 725 ret i32 %2
504 } 726 }
505 727
522 ; 64-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13 744 ; 64-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
523 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] 745 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
524 ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] 746 ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
525 ; 64-CMP-DAG: andi $2, $[[T2]], 1 747 ; 64-CMP-DAG: andi $2, $[[T2]], 1
526 748
749 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
750 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
751 ; MM32R3-DAG: c.ueq.d $f12, $f14
752 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
753
754 ; MM32R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
755 ; MM64R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
756 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
757 ; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]]
758 ; MMR6-DAG: andi16 $2, $[[T2]], 1
759
527 %1 = fcmp one double %a, %b 760 %1 = fcmp one double %a, %b
528 %2 = zext i1 %1 to i32 761 %2 = zext i1 %1 to i32
529 ret i32 %2 762 ret i32 %2
530 } 763 }
531 764
548 ; 64-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13 781 ; 64-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
549 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] 782 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
550 ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] 783 ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
551 ; 64-CMP-DAG: andi $2, $[[T2]], 1 784 ; 64-CMP-DAG: andi $2, $[[T2]], 1
552 785
786 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
787 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
788 ; MM32R3-DAG: c.un.d $f12, $f14
789 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
790
791 ; MM32R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
792 ; MM64R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
793 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
794 ; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]]
795 ; MMR6-DAG: andi16 $2, $[[T2]], 1
796
553 %1 = fcmp ord double %a, %b 797 %1 = fcmp ord double %a, %b
554 %2 = zext i1 %1 to i32 798 %2 = zext i1 %1 to i32
555 ret i32 %2 799 ret i32 %2
556 } 800 }
557 801
572 816
573 ; 64-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13 817 ; 64-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
574 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] 818 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
575 ; 64-CMP-DAG: andi $2, $[[T1]], 1 819 ; 64-CMP-DAG: andi $2, $[[T1]], 1
576 820
821 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
822 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
823 ; MM32R3-DAG: c.ueq.d $f12, $f14
824 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
825
826 ; MM32R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
827 ; MM64R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
828 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
829 ; MMR6-DAG: andi16 $2, $[[T1]], 1
830
577 %1 = fcmp ueq double %a, %b 831 %1 = fcmp ueq double %a, %b
578 %2 = zext i1 %1 to i32 832 %2 = zext i1 %1 to i32
579 ret i32 %2 833 ret i32 %2
580 } 834 }
581 835
596 850
597 ; 64-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12 851 ; 64-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12
598 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] 852 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
599 ; 64-CMP-DAG: andi $2, $[[T1]], 1 853 ; 64-CMP-DAG: andi $2, $[[T1]], 1
600 854
855 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
856 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
857 ; MM32R3-DAG: c.ole.d $f12, $f14
858 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
859
860 ; MM32R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12
861 ; MM64R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12
862 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
863 ; MMR6-DAG: andi16 $2, $[[T1]], 1
864
601 %1 = fcmp ugt double %a, %b 865 %1 = fcmp ugt double %a, %b
602 %2 = zext i1 %1 to i32 866 %2 = zext i1 %1 to i32
603 ret i32 %2 867 ret i32 %2
604 } 868 }
605 869
620 884
621 ; 64-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12 885 ; 64-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12
622 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] 886 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
623 ; 64-CMP-DAG: andi $2, $[[T1]], 1 887 ; 64-CMP-DAG: andi $2, $[[T1]], 1
624 888
889 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
890 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
891 ; MM32R3-DAG: c.olt.d $f12, $f14
892 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
893
894 ; MM32R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12
895 ; MM64R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12
896 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
897 ; MMR6-DAG: andi16 $2, $[[T1]], 1
898
625 %1 = fcmp uge double %a, %b 899 %1 = fcmp uge double %a, %b
626 %2 = zext i1 %1 to i32 900 %2 = zext i1 %1 to i32
627 ret i32 %2 901 ret i32 %2
628 } 902 }
629 903
644 918
645 ; 64-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13 919 ; 64-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13
646 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] 920 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
647 ; 64-CMP-DAG: andi $2, $[[T1]], 1 921 ; 64-CMP-DAG: andi $2, $[[T1]], 1
648 922
923 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
924 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
925 ; MM32R3-DAG: c.ult.d $f12, $f14
926 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
927
928 ; MM32R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14
929 ; MM64R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13
930 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
931 ; MMR6-DAG: andi16 $2, $[[T1]], 1
932
649 %1 = fcmp ult double %a, %b 933 %1 = fcmp ult double %a, %b
650 %2 = zext i1 %1 to i32 934 %2 = zext i1 %1 to i32
651 ret i32 %2 935 ret i32 %2
652 } 936 }
653 937
668 952
669 ; 64-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13 953 ; 64-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13
670 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] 954 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
671 ; 64-CMP-DAG: andi $2, $[[T1]], 1 955 ; 64-CMP-DAG: andi $2, $[[T1]], 1
672 956
957 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
958 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
959 ; MM32R3-DAG: c.ule.d $f12, $f14
960 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
961
962 ; MM32R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14
963 ; MM64R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13
964 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
965 ; MMR6-DAG: andi16 $2, $[[T1]], 1
966
673 %1 = fcmp ule double %a, %b 967 %1 = fcmp ule double %a, %b
674 %2 = zext i1 %1 to i32 968 %2 = zext i1 %1 to i32
675 ret i32 %2 969 ret i32 %2
676 } 970 }
677 971
694 ; 64-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13 988 ; 64-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
695 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] 989 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
696 ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] 990 ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
697 ; 64-CMP-DAG: andi $2, $[[T2]], 1 991 ; 64-CMP-DAG: andi $2, $[[T2]], 1
698 992
993 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
994 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
995 ; MM32R3-DAG: c.eq.d $f12, $f14
996 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
997
998 ; MM32R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
999 ; MM64R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
1000 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
1001 ; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]]
1002 ; MMR6-DAG: andi16 $2, $[[T2]], 1
1003
699 %1 = fcmp une double %a, %b 1004 %1 = fcmp une double %a, %b
700 %2 = zext i1 %1 to i32 1005 %2 = zext i1 %1 to i32
701 ret i32 %2 1006 ret i32 %2
702 } 1007 }
703 1008
718 1023
719 ; 64-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13 1024 ; 64-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
720 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] 1025 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
721 ; 64-CMP-DAG: andi $2, $[[T1]], 1 1026 ; 64-CMP-DAG: andi $2, $[[T1]], 1
722 1027
1028 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
1029 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
1030 ; MM32R3-DAG: c.un.d $f12, $f14
1031 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
1032
1033 ; MM32R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
1034 ; MM64R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
1035 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
1036 ; MMR6-DAG: andi16 $2, $[[T1]], 1
1037
723 %1 = fcmp uno double %a, %b 1038 %1 = fcmp uno double %a, %b
724 %2 = zext i1 %1 to i32 1039 %2 = zext i1 %1 to i32
725 ret i32 %2 1040 ret i32 %2
726 } 1041 }
727 1042
728 define i32 @true_f64(double %a, double %b) nounwind { 1043 define i32 @true_f64(double %a, double %b) nounwind {
729 ; ALL-LABEL: true_f64: 1044 ; ALL-LABEL: true_f64:
730 ; ALL: addiu $2, $zero, 1 1045 ; 32-C: addiu $2, $zero, 1
1046
1047 ; 32-CMP: addiu $2, $zero, 1
1048
1049 ; 64-C: addiu $2, $zero, 1
1050
1051 ; 64-CMP: addiu $2, $zero, 1
1052
1053 ; MM-DAG: li16 $2, 1
731 1054
732 %1 = fcmp true double %a, %b 1055 %1 = fcmp true double %a, %b
733 %2 = zext i1 %1 to i32 1056 %2 = zext i1 %1 to i32
734 ret i32 %2 1057 ret i32 %2
735 } 1058 }
748 ; 32-CMP-DAG: lwc1 $[[T1:f[0-9]+]], %lo($CPI32_0)( 1071 ; 32-CMP-DAG: lwc1 $[[T1:f[0-9]+]], %lo($CPI32_0)(
749 ; 32-CMP-DAG: cmp.le.s $[[T2:f[0-9]+]], $[[T0]], $[[T1]] 1072 ; 32-CMP-DAG: cmp.le.s $[[T2:f[0-9]+]], $[[T0]], $[[T1]]
750 ; 32-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]] 1073 ; 32-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]]
751 ; FIXME: This instruction is redundant. 1074 ; FIXME: This instruction is redundant.
752 ; 32-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1 1075 ; 32-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1
753 ; 32-CMP-DAG: bnez $[[T4]], 1076 ; 32-CMP-DAG: bnezc $[[T4]],
754 1077
755 ; 64-C-DAG: add.s $[[T0:f[0-9]+]], $f13, $f12 1078 ; 64-C-DAG: add.s $[[T0:f[0-9]+]], $f13, $f12
756 ; 64-C-DAG: lwc1 $[[T1:f[0-9]+]], %got_ofst($CPI32_0)( 1079 ; 64-C-DAG: lwc1 $[[T1:f[0-9]+]], %got_ofst(.LCPI32_0)(
757 ; 64-C-DAG: c.ole.s $[[T0]], $[[T1]] 1080 ; 64-C-DAG: c.ole.s $[[T0]], $[[T1]]
758 ; 64-C-DAG: bc1t 1081 ; 64-C-DAG: bc1t
759 1082
760 ; 64-CMP-DAG: add.s $[[T0:f[0-9]+]], $f13, $f12 1083 ; 64-CMP-DAG: add.s $[[T0:f[0-9]+]], $f13, $f12
761 ; 64-CMP-DAG: lwc1 $[[T1:f[0-9]+]], %got_ofst($CPI32_0)( 1084 ; 64-CMP-DAG: lwc1 $[[T1:f[0-9]+]], %got_ofst(.LCPI32_0)(
762 ; 64-CMP-DAG: cmp.le.s $[[T2:f[0-9]+]], $[[T0]], $[[T1]] 1085 ; 64-CMP-DAG: cmp.le.s $[[T2:f[0-9]+]], $[[T0]], $[[T1]]
763 ; 64-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]] 1086 ; 64-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]]
764 ; FIXME: This instruction is redundant. 1087 ; FIXME: This instruction is redundant.
765 ; 64-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1 1088 ; 64-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1
766 ; 64-CMP-DAG: bnez $[[T4]], 1089 ; 64-CMP-DAG: bnezc $[[T4]],
1090
1091 ; MM32R3-DAG: add.s $[[T0:f[0-9]+]], $f14, $f12
1092 ; MM32R3-DAG: lui $[[T1:[0-9]+]], %hi($CPI32_0)
1093 ; MM32R3-DAG: lwc1 $[[T2:f[0-9]+]], %lo($CPI32_0)($[[T1]])
1094 ; MM32R3-DAG: c.ole.s $[[T0]], $[[T2]]
1095 ; MM32R3-DAG: bc1t
1096
1097 ; MM32R6-DAG: add.s $[[T0:f[0-9]+]], $f14, $f12
1098 ; MM32R6-DAG: lui $[[T1:[0-9]+]], %hi($CPI32_0)
1099 ; MM32R6-DAG: lwc1 $[[T2:f[0-9]+]], %lo($CPI32_0)($[[T1]])
1100 ; MM32R6-DAG: cmp.le.s $[[T3:f[0-9]+]], $[[T0]], $[[T2]]
1101 ; MM32R6-DAG: mfc1 $[[T4:[0-9]+]], $[[T3:f[0-9]+]]
1102 ; MM32R6-DAG: andi16 $[[T5:[0-9]+]], $[[T4]], 1
1103 ; MM32R6-DAG: bnez $[[T5]],
1104
1105 ; MM64R6-DAG: lui $[[T0:[0-9]+]], %hi(%neg(%gp_rel(bug1_f32)))
1106 ; MM64R6-DAG: daddu $[[T1:[0-9]+]], $[[T0]], $25
1107 ; MM64R6-DAG: daddiu $[[T2:[0-9]+]], $[[T1]], %lo(%neg(%gp_rel(bug1_f32)))
1108 ; MM64R6-DAG: add.s $[[T3:f[0-9]+]], $f13, $f12
1109 ; MM64R6-DAG: ld $[[T4:[0-9]+]], %got_page(.LCPI32_0)($[[T2]])
1110 ; MM64R6-DAG: lwc1 $[[T5:f[0-9]+]], %got_ofst(.LCPI32_0)($[[T4]])
1111 ; MM64R6-DAG: cmp.le.s $[[T6:f[0-9]+]], $[[T3]], $[[T5]]
1112 ; MM64R6-DAG: mfc1 $[[T7:[0-9]+]], $[[T6]]
1113 ; MM64R6-DAG: andi16 $[[T8:[0-9]+]], $[[T7]], 1
1114 ; MM64R6-DAG: bnez $[[T8]],
767 1115
768 %add = fadd fast float %at, %angle 1116 %add = fadd fast float %at, %angle
769 %cmp = fcmp ogt float %add, 1.000000e+00 1117 %cmp = fcmp ogt float %add, 1.000000e+00
770 br i1 %cmp, label %if.then, label %if.end 1118 br i1 %cmp, label %if.then, label %if.end
771 1119
792 ; 32-CMP-DAG: ldc1 $[[T1:f[0-9]+]], %lo($CPI33_0)( 1140 ; 32-CMP-DAG: ldc1 $[[T1:f[0-9]+]], %lo($CPI33_0)(
793 ; 32-CMP-DAG: cmp.le.d $[[T2:f[0-9]+]], $[[T0]], $[[T1]] 1141 ; 32-CMP-DAG: cmp.le.d $[[T2:f[0-9]+]], $[[T0]], $[[T1]]
794 ; 32-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]] 1142 ; 32-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]]
795 ; FIXME: This instruction is redundant. 1143 ; FIXME: This instruction is redundant.
796 ; 32-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1 1144 ; 32-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1
797 ; 32-CMP-DAG: bnez $[[T4]], 1145 ; 32-CMP-DAG: bnezc $[[T4]],
798 1146
799 ; 64-C-DAG: add.d $[[T0:f[0-9]+]], $f13, $f12 1147 ; 64-C-DAG: add.d $[[T0:f[0-9]+]], $f13, $f12
800 ; 64-C-DAG: ldc1 $[[T1:f[0-9]+]], %got_ofst($CPI33_0)( 1148 ; 64-C-DAG: ldc1 $[[T1:f[0-9]+]], %got_ofst(.LCPI33_0)(
801 ; 64-C-DAG: c.ole.d $[[T0]], $[[T1]] 1149 ; 64-C-DAG: c.ole.d $[[T0]], $[[T1]]
802 ; 64-C-DAG: bc1t 1150 ; 64-C-DAG: bc1t
803 1151
804 ; 64-CMP-DAG: add.d $[[T0:f[0-9]+]], $f13, $f12 1152 ; 64-CMP-DAG: add.d $[[T0:f[0-9]+]], $f13, $f12
805 ; 64-CMP-DAG: ldc1 $[[T1:f[0-9]+]], %got_ofst($CPI33_0)( 1153 ; 64-CMP-DAG: ldc1 $[[T1:f[0-9]+]], %got_ofst(.LCPI33_0)(
806 ; 64-CMP-DAG: cmp.le.d $[[T2:f[0-9]+]], $[[T0]], $[[T1]] 1154 ; 64-CMP-DAG: cmp.le.d $[[T2:f[0-9]+]], $[[T0]], $[[T1]]
807 ; 64-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]] 1155 ; 64-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]]
808 ; FIXME: This instruction is redundant. 1156 ; FIXME: This instruction is redundant.
809 ; 64-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1 1157 ; 64-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1
810 ; 64-CMP-DAG: bnez $[[T4]], 1158 ; 64-CMP-DAG: bnezc $[[T4]],
1159
1160 ; MM32R3-DAG: add.d $[[T0:f[0-9]+]], $f14, $f12
1161 ; MM32R3-DAG: lui $[[T1:[0-9]+]], %hi($CPI33_0)
1162 ; MM32R3-DAG: ldc1 $[[T2:f[0-9]+]], %lo($CPI33_0)($[[T1]])
1163 ; MM32R3-DAG: c.ole.d $[[T0]], $[[T2]]
1164 ; MM32R3-DAG: bc1t
1165
1166 ; MM32R6-DAG: add.d $[[T0:f[0-9]+]], $f14, $f12
1167 ; MM32R6-DAG: lui $[[T1:[0-9]+]], %hi($CPI33_0)
1168 ; MM32R6-DAG: ldc1 $[[T2:f[0-9]+]], %lo($CPI33_0)($[[T1]])
1169 ; MM32R6-DAG: cmp.le.d $[[T3:f[0-9]+]], $[[T0]], $[[T2]]
1170 ; MM32R6-DAG: mfc1 $[[T4:[0-9]+]], $[[T3]]
1171 ; MM32R6-DAG: andi16 $[[T5:[0-9]+]], $[[T4]], 1
1172 ; MM32R6-DAG: bnez $[[T5]],
1173
1174 ; MM64R6-DAG: lui $[[T0:[0-9]+]], %hi(%neg(%gp_rel(bug1_f64)))
1175 ; MM64R6-DAG: daddu $[[T1:[0-9]+]], $[[T0]], $25
1176 ; MM64R6-DAG: daddiu $[[T2:[0-9]+]], $[[T1]], %lo(%neg(%gp_rel(bug1_f64)))
1177 ; MM64R6-DAG: add.d $[[T3:f[0-9]+]], $f13, $f12
1178 ; MM64R6-DAG: ld $[[T4:[0-9]+]], %got_page(.LCPI33_0)($[[T2]])
1179 ; MM64R6-DAG: ldc1 $[[T5:f[0-9]+]], %got_ofst(.LCPI33_0)($[[T4]])
1180 ; MM64R6-DAG: cmp.le.d $[[T6:f[0-9]+]], $[[T3]], $[[T5]]
1181 ; MM64R6-DAG: mfc1 $[[T7:[0-9]+]], $[[T6]]
1182 ; MM64R6-DAG: andi16 $[[T8:[0-9]+]], $[[T7]], 1
1183 ; MM64R6-DAG: bnez $[[T8]],
811 1184
812 %add = fadd fast double %at, %angle 1185 %add = fadd fast double %at, %angle
813 %cmp = fcmp ogt double %add, 1.000000e+00 1186 %cmp = fcmp ogt double %add, 1.000000e+00
814 br i1 %cmp, label %if.then, label %if.end 1187 br i1 %cmp, label %if.then, label %if.end
815 1188