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comparison test/CodeGen/PowerPC/builtins-ppc-p8vector.ll @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents afa8332a0e37
children
comparison
equal deleted inserted replaced
101:34baf5011add 120:1172e4bd9c6f
1 ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s 1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
2 ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s 2 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
3 ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+power8-vector -mattr=-vsx < %s | FileCheck %s 3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+power8-vector -mattr=-vsx < %s | FileCheck %s
4 ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-VSX 4 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-VSX
5 5
6 @vsc = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 16 6 @vsc = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 16
7 @vsc2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 16
7 @vuc = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 16 8 @vuc = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 16
9 @vuc2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 16
8 @res_vll = common global <2 x i64> zeroinitializer, align 16 10 @res_vll = common global <2 x i64> zeroinitializer, align 16
9 @res_vull = common global <2 x i64> zeroinitializer, align 16 11 @res_vull = common global <2 x i64> zeroinitializer, align 16
10 @res_vsc = common global <16 x i8> zeroinitializer, align 16 12 @res_vsc = common global <16 x i8> zeroinitializer, align 16
11 @res_vuc = common global <16 x i8> zeroinitializer, align 16 13 @res_vuc = common global <16 x i8> zeroinitializer, align 16
12 14
13 ; Function Attrs: nounwind 15 ; Function Attrs: nounwind
14 define void @test1() { 16 define void @test1() {
15 entry: 17 entry:
16 %__a.addr.i = alloca <16 x i8>, align 16
17 %__b.addr.i = alloca <16 x i8>, align 16
18 %0 = load <16 x i8>, <16 x i8>* @vsc, align 16 18 %0 = load <16 x i8>, <16 x i8>* @vsc, align 16
19 %1 = load <16 x i8>, <16 x i8>* @vsc, align 16 19 %1 = load <16 x i8>, <16 x i8>* @vsc2, align 16
20 store <16 x i8> %0, <16 x i8>* %__a.addr.i, align 16 20 %2 = call <2 x i64> @llvm.ppc.altivec.vbpermq(<16 x i8> %0, <16 x i8> %1)
21 store <16 x i8> %1, <16 x i8>* %__b.addr.i, align 16 21 store <2 x i64> %2, <2 x i64>* @res_vll, align 16
22 %2 = load <16 x i8>, <16 x i8>* %__a.addr.i, align 16
23 %3 = load <16 x i8>, <16 x i8>* %__b.addr.i, align 16
24 %4 = call <2 x i64> @llvm.ppc.altivec.vbpermq(<16 x i8> %2, <16 x i8> %3)
25 store <2 x i64> %4, <2 x i64>* @res_vll, align 16
26 ret void 22 ret void
27 ; CHECK-LABEL: @test1 23 ; CHECK-LABEL: @test1
28 ; CHECK: lvx [[REG1:[0-9]+]], 24 ; CHECK: lvx [[REG1:[0-9]+]], 0, 3
29 ; CHECK: lvx [[REG2:[0-9]+]], 25 ; CHECK: lvx [[REG2:[0-9]+]], 0, 4
30 ; CHECK: vbpermq {{[0-9]+}}, [[REG2]], [[REG1]] 26 ; CHECK: vbpermq {{[0-9]+}}, [[REG1]], [[REG2]]
31 ; CHECK-VSX: vbpermq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} 27 ; CHECK-VSX: vbpermq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
32 } 28 }
33 29
34 ; Function Attrs: nounwind 30 ; Function Attrs: nounwind
35 define void @test2() { 31 define void @test2() {
36 entry: 32 entry:
37 %__a.addr.i = alloca <16 x i8>, align 16
38 %__b.addr.i = alloca <16 x i8>, align 16
39 %0 = load <16 x i8>, <16 x i8>* @vuc, align 16 33 %0 = load <16 x i8>, <16 x i8>* @vuc, align 16
40 %1 = load <16 x i8>, <16 x i8>* @vuc, align 16 34 %1 = load <16 x i8>, <16 x i8>* @vuc2, align 16
41 store <16 x i8> %0, <16 x i8>* %__a.addr.i, align 16 35 %2 = call <2 x i64> @llvm.ppc.altivec.vbpermq(<16 x i8> %0, <16 x i8> %1)
42 store <16 x i8> %1, <16 x i8>* %__b.addr.i, align 16 36 store <2 x i64> %2, <2 x i64>* @res_vull, align 16
43 %2 = load <16 x i8>, <16 x i8>* %__a.addr.i, align 16
44 %3 = load <16 x i8>, <16 x i8>* %__b.addr.i, align 16
45 %4 = call <2 x i64> @llvm.ppc.altivec.vbpermq(<16 x i8> %2, <16 x i8> %3)
46 store <2 x i64> %4, <2 x i64>* @res_vull, align 16
47 ret void 37 ret void
48 ; CHECK-LABEL: @test2 38 ; CHECK-LABEL: @test2
49 ; CHECK: lvx [[REG1:[0-9]+]], 39 ; CHECK: lvx [[REG1:[0-9]+]], 0, 3
50 ; CHECK: lvx [[REG2:[0-9]+]], 40 ; CHECK: lvx [[REG2:[0-9]+]], 0, 4
51 ; CHECK: vbpermq {{[0-9]+}}, [[REG2]], [[REG1]] 41 ; CHECK: vbpermq {{[0-9]+}}, [[REG1]], [[REG2]]
52 ; CHECK-VSX: vbpermq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} 42 ; CHECK-VSX: vbpermq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
53 } 43 }
54 44
55 ; Function Attrs: nounwind 45 ; Function Attrs: nounwind
56 define void @test3() { 46 define void @test3() {
57 entry: 47 entry:
58 %__a.addr.i = alloca <16 x i8>, align 16
59 %0 = load <16 x i8>, <16 x i8>* @vsc, align 16 48 %0 = load <16 x i8>, <16 x i8>* @vsc, align 16
60 store <16 x i8> %0, <16 x i8>* %__a.addr.i, align 16 49 %1 = call <16 x i8> @llvm.ppc.altivec.vgbbd(<16 x i8> %0)
61 %1 = load <16 x i8>, <16 x i8>* %__a.addr.i, align 16 50 store <16 x i8> %1, <16 x i8>* @res_vsc, align 16
62 %2 = call <16 x i8> @llvm.ppc.altivec.vgbbd(<16 x i8> %1)
63 store <16 x i8> %2, <16 x i8>* @res_vsc, align 16
64 ret void 51 ret void
65 ; CHECK-LABEL: @test3 52 ; CHECK-LABEL: @test3
66 ; CHECK: lvx [[REG1:[0-9]+]], 53 ; CHECK: lvx [[REG1:[0-9]+]],
67 ; CHECK: vgbbd {{[0-9]+}}, [[REG1]] 54 ; CHECK: vgbbd {{[0-9]+}}, [[REG1]]
68 ; CHECK-VSX: vgbbd {{[0-9]+}}, {{[0-9]+}} 55 ; CHECK-VSX: vgbbd {{[0-9]+}}, {{[0-9]+}}
69 } 56 }
70 57
71 ; Function Attrs: nounwind 58 ; Function Attrs: nounwind
72 define void @test4() { 59 define void @test4() {
73 entry: 60 entry:
74 %__a.addr.i = alloca <16 x i8>, align 16
75 %0 = load <16 x i8>, <16 x i8>* @vuc, align 16 61 %0 = load <16 x i8>, <16 x i8>* @vuc, align 16
76 store <16 x i8> %0, <16 x i8>* %__a.addr.i, align 16 62 %1 = call <16 x i8> @llvm.ppc.altivec.vgbbd(<16 x i8> %0)
77 %1 = load <16 x i8>, <16 x i8>* %__a.addr.i, align 16 63 store <16 x i8> %1, <16 x i8>* @res_vuc, align 16
78 %2 = call <16 x i8> @llvm.ppc.altivec.vgbbd(<16 x i8> %1)
79 store <16 x i8> %2, <16 x i8>* @res_vuc, align 16
80 ret void 64 ret void
81 ; CHECK-LABEL: @test4 65 ; CHECK-LABEL: @test4
82 ; CHECK: lvx [[REG1:[0-9]+]], 66 ; CHECK: lvx [[REG1:[0-9]+]],
83 ; CHECK: vgbbd {{[0-9]+}}, [[REG1]] 67 ; CHECK: vgbbd {{[0-9]+}}, [[REG1]]
84 ; CHECK-VSX: vgbbd {{[0-9]+}}, {{[0-9]+}} 68 ; CHECK-VSX: vgbbd {{[0-9]+}}, {{[0-9]+}}