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comparison test/CodeGen/X86/mmx-bitcast.ll @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents afa8332a0e37
children 803732b1fca8
comparison
equal deleted inserted replaced
101:34baf5011add 120:1172e4bd9c6f
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mtriple=x86_64-darwin -mattr=+mmx,+sse2 | FileCheck %s 2 ; RUN: llc < %s -mtriple=x86_64-darwin -mattr=+mmx,+sse2 | FileCheck %s
2 3
3 define i64 @t0(x86_mmx* %p) { 4 define i64 @t0(x86_mmx* %p) {
4 ; CHECK-LABEL: t0: 5 ; CHECK-LABEL: t0:
5 ; CHECK: ## BB#0: 6 ; CHECK: ## BB#0:
6 ; CHECK-NEXT: movq 7 ; CHECK-NEXT: movq (%rdi), %mm0
7 ; CHECK-NEXT: paddq %mm0, %mm0 8 ; CHECK-NEXT: paddq %mm0, %mm0
8 ; CHECK-NEXT: movd %mm0, %rax 9 ; CHECK-NEXT: movd %mm0, %rax
9 ; CHECK-NEXT: retq 10 ; CHECK-NEXT: retq
10 %t = load x86_mmx, x86_mmx* %p 11 %t = load x86_mmx, x86_mmx* %p
11 %u = tail call x86_mmx @llvm.x86.mmx.padd.q(x86_mmx %t, x86_mmx %t) 12 %u = tail call x86_mmx @llvm.x86.mmx.padd.q(x86_mmx %t, x86_mmx %t)
14 } 15 }
15 16
16 define i64 @t1(x86_mmx* %p) { 17 define i64 @t1(x86_mmx* %p) {
17 ; CHECK-LABEL: t1: 18 ; CHECK-LABEL: t1:
18 ; CHECK: ## BB#0: 19 ; CHECK: ## BB#0:
19 ; CHECK-NEXT: movq 20 ; CHECK-NEXT: movq (%rdi), %mm0
20 ; CHECK-NEXT: paddd %mm0, %mm0 21 ; CHECK-NEXT: paddd %mm0, %mm0
21 ; CHECK-NEXT: movd %mm0, %rax 22 ; CHECK-NEXT: movd %mm0, %rax
22 ; CHECK-NEXT: retq 23 ; CHECK-NEXT: retq
23 %t = load x86_mmx, x86_mmx* %p 24 %t = load x86_mmx, x86_mmx* %p
24 %u = tail call x86_mmx @llvm.x86.mmx.padd.d(x86_mmx %t, x86_mmx %t) 25 %u = tail call x86_mmx @llvm.x86.mmx.padd.d(x86_mmx %t, x86_mmx %t)
27 } 28 }
28 29
29 define i64 @t2(x86_mmx* %p) { 30 define i64 @t2(x86_mmx* %p) {
30 ; CHECK-LABEL: t2: 31 ; CHECK-LABEL: t2:
31 ; CHECK: ## BB#0: 32 ; CHECK: ## BB#0:
32 ; CHECK-NEXT: movq 33 ; CHECK-NEXT: movq (%rdi), %mm0
33 ; CHECK-NEXT: paddw %mm0, %mm0 34 ; CHECK-NEXT: paddw %mm0, %mm0
34 ; CHECK-NEXT: movd %mm0, %rax 35 ; CHECK-NEXT: movd %mm0, %rax
35 ; CHECK-NEXT: retq 36 ; CHECK-NEXT: retq
36 %t = load x86_mmx, x86_mmx* %p 37 %t = load x86_mmx, x86_mmx* %p
37 %u = tail call x86_mmx @llvm.x86.mmx.padd.w(x86_mmx %t, x86_mmx %t) 38 %u = tail call x86_mmx @llvm.x86.mmx.padd.w(x86_mmx %t, x86_mmx %t)
40 } 41 }
41 42
42 define i64 @t3(x86_mmx* %p) { 43 define i64 @t3(x86_mmx* %p) {
43 ; CHECK-LABEL: t3: 44 ; CHECK-LABEL: t3:
44 ; CHECK: ## BB#0: 45 ; CHECK: ## BB#0:
45 ; CHECK-NEXT: movq 46 ; CHECK-NEXT: movq (%rdi), %mm0
46 ; CHECK-NEXT: paddb %mm0, %mm0 47 ; CHECK-NEXT: paddb %mm0, %mm0
47 ; CHECK-NEXT: movd %mm0, %rax 48 ; CHECK-NEXT: movd %mm0, %rax
48 ; CHECK-NEXT: retq 49 ; CHECK-NEXT: retq
49 %t = load x86_mmx, x86_mmx* %p 50 %t = load x86_mmx, x86_mmx* %p
50 %u = tail call x86_mmx @llvm.x86.mmx.padd.b(x86_mmx %t, x86_mmx %t) 51 %u = tail call x86_mmx @llvm.x86.mmx.padd.b(x86_mmx %t, x86_mmx %t)
55 @R = external global x86_mmx 56 @R = external global x86_mmx
56 57
57 define void @t4(<1 x i64> %A, <1 x i64> %B) { 58 define void @t4(<1 x i64> %A, <1 x i64> %B) {
58 ; CHECK-LABEL: t4: 59 ; CHECK-LABEL: t4:
59 ; CHECK: ## BB#0: ## %entry 60 ; CHECK: ## BB#0: ## %entry
60 ; CHECK-NEXT: movd 61 ; CHECK-NEXT: movd %rdi, %mm0
61 ; CHECK-NEXT: movd 62 ; CHECK-NEXT: movd %rsi, %mm1
62 ; CHECK: retq 63 ; CHECK-NEXT: paddusw %mm0, %mm1
64 ; CHECK-NEXT: movq _R@{{.*}}(%rip), %rax
65 ; CHECK-NEXT: movq %mm1, (%rax)
66 ; CHECK-NEXT: emms
67 ; CHECK-NEXT: retq
63 entry: 68 entry:
64 %tmp2 = bitcast <1 x i64> %A to x86_mmx 69 %tmp2 = bitcast <1 x i64> %A to x86_mmx
65 %tmp3 = bitcast <1 x i64> %B to x86_mmx 70 %tmp3 = bitcast <1 x i64> %B to x86_mmx
66 %tmp7 = tail call x86_mmx @llvm.x86.mmx.paddus.w(x86_mmx %tmp2, x86_mmx %tmp3) 71 %tmp7 = tail call x86_mmx @llvm.x86.mmx.paddus.w(x86_mmx %tmp2, x86_mmx %tmp3)
67 store x86_mmx %tmp7, x86_mmx* @R 72 store x86_mmx %tmp7, x86_mmx* @R
70 } 75 }
71 76
72 define i64 @t5(i32 %a, i32 %b) nounwind readnone { 77 define i64 @t5(i32 %a, i32 %b) nounwind readnone {
73 ; CHECK-LABEL: t5: 78 ; CHECK-LABEL: t5:
74 ; CHECK: ## BB#0: 79 ; CHECK: ## BB#0:
75 ; CHECK-NEXT: movd 80 ; CHECK-NEXT: movd %esi, %xmm0
76 ; CHECK-NEXT: movd 81 ; CHECK-NEXT: movd %edi, %xmm1
77 ; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] 82 ; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
78 ; CHECK-NEXT: movd %xmm1, %rax 83 ; CHECK-NEXT: movd %xmm1, %rax
79 ; CHECK-NEXT: retq 84 ; CHECK-NEXT: retq
80 %v0 = insertelement <2 x i32> undef, i32 %a, i32 0 85 %v0 = insertelement <2 x i32> undef, i32 %a, i32 0
81 %v1 = insertelement <2 x i32> %v0, i32 %b, i32 1 86 %v1 = insertelement <2 x i32> %v0, i32 %b, i32 1
86 declare x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx, i32) 91 declare x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx, i32)
87 92
88 define <1 x i64> @t6(i64 %t) { 93 define <1 x i64> @t6(i64 %t) {
89 ; CHECK-LABEL: t6: 94 ; CHECK-LABEL: t6:
90 ; CHECK: ## BB#0: 95 ; CHECK: ## BB#0:
91 ; CHECK-NEXT: movd 96 ; CHECK-NEXT: movd %rdi, %mm0
92 ; CHECK-NEXT: psllq $48, %mm0 97 ; CHECK-NEXT: psllq $48, %mm0
93 ; CHECK-NEXT: movd %mm0, %rax 98 ; CHECK-NEXT: movd %mm0, %rax
94 ; CHECK-NEXT: retq 99 ; CHECK-NEXT: retq
95 %t1 = insertelement <1 x i64> undef, i64 %t, i32 0 100 %t1 = insertelement <1 x i64> undef, i64 %t, i32 0
96 %t0 = bitcast <1 x i64> %t1 to x86_mmx 101 %t0 = bitcast <1 x i64> %t1 to x86_mmx