Mercurial > hg > CbC > CbC_llvm

comparison test/CodeGen/X86/vec_setcc.ll @ 120:1172e4bd9c6f

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents 60c9769439b8
children 3a76565eade5
comparison
equal deleted inserted replaced
101:34baf5011add 120:1172e4bd9c6f
1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=sse2 | FileCheck %s -check-prefix=SSE2 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=sse4.1 | FileCheck %s -check-prefix=SSE41 2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE2
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=avx | FileCheck %s -check-prefix=AVX 3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE41
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX
4 5
5 define <16 x i8> @v16i8_icmp_uge(<16 x i8> %a, <16 x i8> %b) nounwind readnone ssp uwtable { 6 define <16 x i8> @v16i8_icmp_uge(<16 x i8> %a, <16 x i8> %b) nounwind readnone ssp uwtable {
7 ; SSE-LABEL: v16i8_icmp_uge:
8 ; SSE: # BB#0:
9 ; SSE-NEXT: pmaxub %xmm0, %xmm1
10 ; SSE-NEXT: pcmpeqb %xmm1, %xmm0
11 ; SSE-NEXT: retq
12 ;
13 ; AVX-LABEL: v16i8_icmp_uge:
14 ; AVX: # BB#0:
15 ; AVX-NEXT: vpmaxub %xmm1, %xmm0, %xmm1
16 ; AVX-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
17 ; AVX-NEXT: retq
6 %1 = icmp uge <16 x i8> %a, %b 18 %1 = icmp uge <16 x i8> %a, %b
7 %2 = sext <16 x i1> %1 to <16 x i8> 19 %2 = sext <16 x i1> %1 to <16 x i8>
8 ret <16 x i8> %2 20 ret <16 x i8> %2
9 ; SSE2-LABEL: v16i8_icmp_uge:
10 ; SSE2: pmaxub %xmm0, %xmm1
11 ; SSE2: pcmpeqb %xmm1, %xmm0
12
13 ; SSE41-LABEL: v16i8_icmp_uge:
14 ; SSE41: pmaxub %xmm0, %xmm1
15 ; SSE41: pcmpeqb %xmm1, %xmm0
16
17 ; AVX-LABEL: v16i8_icmp_uge:
18 ; AVX: vpmaxub %xmm1, %xmm0, %xmm1
19 ; AVX: vpcmpeqb %xmm1, %xmm0, %xmm0
20 } 21 }
21 22
22 define <16 x i8> @v16i8_icmp_ule(<16 x i8> %a, <16 x i8> %b) nounwind readnone ssp uwtable { 23 define <16 x i8> @v16i8_icmp_ule(<16 x i8> %a, <16 x i8> %b) nounwind readnone ssp uwtable {
24 ; SSE-LABEL: v16i8_icmp_ule:
25 ; SSE: # BB#0:
26 ; SSE-NEXT: pminub %xmm0, %xmm1
27 ; SSE-NEXT: pcmpeqb %xmm1, %xmm0
28 ; SSE-NEXT: retq
29 ;
30 ; AVX-LABEL: v16i8_icmp_ule:
31 ; AVX: # BB#0:
32 ; AVX-NEXT: vpminub %xmm1, %xmm0, %xmm1
33 ; AVX-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
34 ; AVX-NEXT: retq
23 %1 = icmp ule <16 x i8> %a, %b 35 %1 = icmp ule <16 x i8> %a, %b
24 %2 = sext <16 x i1> %1 to <16 x i8> 36 %2 = sext <16 x i1> %1 to <16 x i8>
25 ret <16 x i8> %2 37 ret <16 x i8> %2
26 ; SSE2-LABEL: v16i8_icmp_ule:
27 ; SSE2: pminub %xmm0, %xmm1
28 ; SSE2: pcmpeqb %xmm1, %xmm0
29
30 ; SSE41-LABEL: v16i8_icmp_ule:
31 ; SSE41: pminub %xmm0, %xmm1
32 ; SSE41: pcmpeqb %xmm1, %xmm0
33
34 ; AVX-LABEL: v16i8_icmp_ule:
35 ; AVX: vpminub %xmm1, %xmm0, %xmm1
36 ; AVX: vpcmpeqb %xmm1, %xmm0, %xmm0
37 } 38 }
38 39
39
40 define <8 x i16> @v8i16_icmp_uge(<8 x i16> %a, <8 x i16> %b) nounwind readnone ssp uwtable { 40 define <8 x i16> @v8i16_icmp_uge(<8 x i16> %a, <8 x i16> %b) nounwind readnone ssp uwtable {
41 ; SSE2-LABEL: v8i16_icmp_uge:
42 ; SSE2: # BB#0:
43 ; SSE2-NEXT: psubusw %xmm0, %xmm1
44 ; SSE2-NEXT: pxor %xmm0, %xmm0
45 ; SSE2-NEXT: pcmpeqw %xmm1, %xmm0
46 ; SSE2-NEXT: retq
47 ;
48 ; SSE41-LABEL: v8i16_icmp_uge:
49 ; SSE41: # BB#0:
50 ; SSE41-NEXT: pmaxuw %xmm0, %xmm1
51 ; SSE41-NEXT: pcmpeqw %xmm1, %xmm0
52 ; SSE41-NEXT: retq
53 ;
54 ; AVX-LABEL: v8i16_icmp_uge:
55 ; AVX: # BB#0:
56 ; AVX-NEXT: vpmaxuw %xmm1, %xmm0, %xmm1
57 ; AVX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
58 ; AVX-NEXT: retq
41 %1 = icmp uge <8 x i16> %a, %b 59 %1 = icmp uge <8 x i16> %a, %b
42 %2 = sext <8 x i1> %1 to <8 x i16> 60 %2 = sext <8 x i1> %1 to <8 x i16>
43 ret <8 x i16> %2 61 ret <8 x i16> %2
44 ; SSE2-LABEL: v8i16_icmp_uge:
45 ; SSE2: psubusw %xmm0, %xmm1
46 ; SEE2: pxor %xmm0, %xmm0
47 ; SSE2: pcmpeqw %xmm1, %xmm0
48
49 ; SSE41-LABEL: v8i16_icmp_uge:
50 ; SSE41: pmaxuw %xmm0, %xmm1
51 ; SSE41: pcmpeqw %xmm1, %xmm0
52
53 ; AVX-LABEL: v8i16_icmp_uge:
54 ; AVX: vpmaxuw %xmm1, %xmm0, %xmm1
55 ; AVX: vpcmpeqw %xmm1, %xmm0, %xmm0
56 } 62 }
57 63
58 define <8 x i16> @v8i16_icmp_ule(<8 x i16> %a, <8 x i16> %b) nounwind readnone ssp uwtable { 64 define <8 x i16> @v8i16_icmp_ule(<8 x i16> %a, <8 x i16> %b) nounwind readnone ssp uwtable {
65 ; SSE2-LABEL: v8i16_icmp_ule:
66 ; SSE2: # BB#0:
67 ; SSE2-NEXT: psubusw %xmm1, %xmm0
68 ; SSE2-NEXT: pxor %xmm1, %xmm1
69 ; SSE2-NEXT: pcmpeqw %xmm1, %xmm0
70 ; SSE2-NEXT: retq
71 ;
72 ; SSE41-LABEL: v8i16_icmp_ule:
73 ; SSE41: # BB#0:
74 ; SSE41-NEXT: pminuw %xmm0, %xmm1
75 ; SSE41-NEXT: pcmpeqw %xmm1, %xmm0
76 ; SSE41-NEXT: retq
77 ;
78 ; AVX-LABEL: v8i16_icmp_ule:
79 ; AVX: # BB#0:
80 ; AVX-NEXT: vpminuw %xmm1, %xmm0, %xmm1
81 ; AVX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
82 ; AVX-NEXT: retq
59 %1 = icmp ule <8 x i16> %a, %b 83 %1 = icmp ule <8 x i16> %a, %b
60 %2 = sext <8 x i1> %1 to <8 x i16> 84 %2 = sext <8 x i1> %1 to <8 x i16>
61 ret <8 x i16> %2 85 ret <8 x i16> %2
62 ; SSE2-LABEL: v8i16_icmp_ule:
63 ; SSE2: psubusw %xmm1, %xmm0
64 ; SSE2: pxor %xmm1, %xmm1
65 ; SSE2: pcmpeqw %xmm1, %xmm0
66
67 ; SSE41-LABEL: v8i16_icmp_ule:
68 ; SSE41: pminuw %xmm0, %xmm1
69 ; SSE41: pcmpeqw %xmm1, %xmm0
70
71 ; AVX-LABEL: v8i16_icmp_ule:
72 ; AVX: vpminuw %xmm1, %xmm0, %xmm1
73 ; AVX: vpcmpeqw %xmm1, %xmm0, %xmm0
74 } 86 }
75 87
76
77 define <4 x i32> @v4i32_icmp_uge(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp uwtable { 88 define <4 x i32> @v4i32_icmp_uge(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp uwtable {
89 ; SSE2-LABEL: v4i32_icmp_uge:
90 ; SSE2: # BB#0:
91 ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
92 ; SSE2-NEXT: pxor %xmm2, %xmm0
93 ; SSE2-NEXT: pxor %xmm1, %xmm2
94 ; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
95 ; SSE2-NEXT: pcmpeqd %xmm0, %xmm0
96 ; SSE2-NEXT: pxor %xmm2, %xmm0
97 ; SSE2-NEXT: retq
98 ;
99 ; SSE41-LABEL: v4i32_icmp_uge:
100 ; SSE41: # BB#0:
101 ; SSE41-NEXT: pmaxud %xmm0, %xmm1
102 ; SSE41-NEXT: pcmpeqd %xmm1, %xmm0
103 ; SSE41-NEXT: retq
104 ;
105 ; AVX-LABEL: v4i32_icmp_uge:
106 ; AVX: # BB#0:
107 ; AVX-NEXT: vpmaxud %xmm1, %xmm0, %xmm1
108 ; AVX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
109 ; AVX-NEXT: retq
78 %1 = icmp uge <4 x i32> %a, %b 110 %1 = icmp uge <4 x i32> %a, %b
79 %2 = sext <4 x i1> %1 to <4 x i32> 111 %2 = sext <4 x i1> %1 to <4 x i32>
80 ret <4 x i32> %2 112 ret <4 x i32> %2
81 ; SSE2-LABEL: v4i32_icmp_uge:
82 ; SSE2: movdqa {{.*}}(%rip), %xmm2
83 ; SSE2: pxor %xmm2, %xmm0
84 ; SSE2: pxor %xmm1, %xmm2
85 ; SSE2: pcmpgtd %xmm0, %xmm2
86 ; SSE2: pcmpeqd %xmm0, %xmm0
87 ; SSE2: pxor %xmm2, %xmm0
88
89 ; SSE41-LABEL: v4i32_icmp_uge:
90 ; SSE41: pmaxud %xmm0, %xmm1
91 ; SSE41: pcmpeqd %xmm1, %xmm0
92
93 ; AVX-LABEL: v4i32_icmp_uge:
94 ; AVX: vpmaxud %xmm1, %xmm0, %xmm1
95 ; AVX: vpcmpeqd %xmm1, %xmm0, %xmm0
96 } 113 }
97 114
98 define <4 x i32> @v4i32_icmp_ule(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp uwtable { 115 define <4 x i32> @v4i32_icmp_ule(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp uwtable {
116 ; SSE2-LABEL: v4i32_icmp_ule:
117 ; SSE2: # BB#0:
118 ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
119 ; SSE2-NEXT: pxor %xmm2, %xmm1
120 ; SSE2-NEXT: pxor %xmm2, %xmm0
121 ; SSE2-NEXT: pcmpgtd %xmm1, %xmm0
122 ; SSE2-NEXT: pcmpeqd %xmm1, %xmm1
123 ; SSE2-NEXT: pxor %xmm1, %xmm0
124 ; SSE2-NEXT: retq
125 ;
126 ; SSE41-LABEL: v4i32_icmp_ule:
127 ; SSE41: # BB#0:
128 ; SSE41-NEXT: pminud %xmm0, %xmm1
129 ; SSE41-NEXT: pcmpeqd %xmm1, %xmm0
130 ; SSE41-NEXT: retq
131 ;
132 ; AVX-LABEL: v4i32_icmp_ule:
133 ; AVX: # BB#0:
134 ; AVX-NEXT: vpminud %xmm1, %xmm0, %xmm1
135 ; AVX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
136 ; AVX-NEXT: retq
99 %1 = icmp ule <4 x i32> %a, %b 137 %1 = icmp ule <4 x i32> %a, %b
100 %2 = sext <4 x i1> %1 to <4 x i32> 138 %2 = sext <4 x i1> %1 to <4 x i32>
101 ret <4 x i32> %2 139 ret <4 x i32> %2
102 ; SSE2-LABEL: v4i32_icmp_ule:
103 ; SSE2: movdqa {{.*}}(%rip), %xmm2
104 ; SSE2: pxor %xmm2, %xmm1
105 ; SSE2: pxor %xmm2, %xmm0
106 ; SSE2: pcmpgtd %xmm1, %xmm0
107 ; SSE2: pcmpeqd %xmm1, %xmm1
108 ; SSE2: pxor %xmm1, %xmm0
109
110 ; SSE41-LABEL: v4i32_icmp_ule:
111 ; SSE41: pminud %xmm0, %xmm1
112 ; SSE41: pcmpeqd %xmm1, %xmm0
113
114 ; AVX-LABEL: v4i32_icmp_ule:
115 ; AVX: pminud %xmm1, %xmm0, %xmm1
116 ; AVX: pcmpeqd %xmm1, %xmm0, %xmm0
117 } 140 }
118 141
119 ; At one point we were incorrectly constant-folding a setcc to 0x1 instead of 142 ; At one point we were incorrectly constant-folding a setcc to 0x1 instead of
120 ; 0xff, leading to a constpool load. The instruction doesn't matter here, but it 143 ; 0xff, leading to a constpool load. The instruction doesn't matter here, but it
121 ; should set all bits to 1. 144 ; should set all bits to 1.
122 define <16 x i8> @test_setcc_constfold_vi8(<16 x i8> %l, <16 x i8> %r) { 145 define <16 x i8> @test_setcc_constfold_vi8(<16 x i8> %l, <16 x i8> %r) {
146 ; SSE-LABEL: test_setcc_constfold_vi8:
147 ; SSE: # BB#0:
148 ; SSE-NEXT: pcmpeqd %xmm0, %xmm0
149 ; SSE-NEXT: retq
150 ;
151 ; AVX-LABEL: test_setcc_constfold_vi8:
152 ; AVX: # BB#0:
153 ; AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
154 ; AVX-NEXT: retq
123 %test1 = icmp eq <16 x i8> %l, %r 155 %test1 = icmp eq <16 x i8> %l, %r
124 %mask1 = sext <16 x i1> %test1 to <16 x i8> 156 %mask1 = sext <16 x i1> %test1 to <16 x i8>
125
126 %test2 = icmp ne <16 x i8> %l, %r 157 %test2 = icmp ne <16 x i8> %l, %r
127 %mask2 = sext <16 x i1> %test2 to <16 x i8> 158 %mask2 = sext <16 x i1> %test2 to <16 x i8>
128
129 %res = or <16 x i8> %mask1, %mask2 159 %res = or <16 x i8> %mask1, %mask2
130 ret <16 x i8> %res 160 ret <16 x i8> %res
131 ; SSE2-LABEL: test_setcc_constfold_vi8:
132 ; SSE2: pcmpeqd %xmm0, %xmm0
133
134 ; SSE41-LABEL: test_setcc_constfold_vi8:
135 ; SSE41: pcmpeqd %xmm0, %xmm0
136
137 ; AVX-LABEL: test_setcc_constfold_vi8:
138 ; AVX: vpcmpeqd %xmm0, %xmm0, %xmm0
139 } 161 }
140 162
141 ; Make sure sensible results come from doing extension afterwards 163 ; Make sure sensible results come from doing extension afterwards
142 define <16 x i8> @test_setcc_constfold_vi1(<16 x i8> %l, <16 x i8> %r) { 164 define <16 x i8> @test_setcc_constfold_vi1(<16 x i8> %l, <16 x i8> %r) {
165 ; SSE-LABEL: test_setcc_constfold_vi1:
166 ; SSE: # BB#0:
167 ; SSE-NEXT: pcmpeqd %xmm0, %xmm0
168 ; SSE-NEXT: retq
169 ;
170 ; AVX-LABEL: test_setcc_constfold_vi1:
171 ; AVX: # BB#0:
172 ; AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
173 ; AVX-NEXT: retq
143 %test1 = icmp eq <16 x i8> %l, %r 174 %test1 = icmp eq <16 x i8> %l, %r
144 %test2 = icmp ne <16 x i8> %l, %r 175 %test2 = icmp ne <16 x i8> %l, %r
145
146 %res = or <16 x i1> %test1, %test2 176 %res = or <16 x i1> %test1, %test2
147 %mask = sext <16 x i1> %res to <16 x i8> 177 %mask = sext <16 x i1> %res to <16 x i8>
148 ret <16 x i8> %mask 178 ret <16 x i8> %mask
149 ; SSE2-LABEL: test_setcc_constfold_vi1:
150 ; SSE2: pcmpeqd %xmm0, %xmm0
151
152 ; SSE41-LABEL: test_setcc_constfold_vi1:
153 ; SSE41: pcmpeqd %xmm0, %xmm0
154
155 ; AVX-LABEL: test_setcc_constfold_vi1:
156 ; AVX: vpcmpeqd %xmm0, %xmm0, %xmm0
157 } 179 }
158
159 180
160 ; 64-bit case is also particularly important, as the constant "-1" is probably 181 ; 64-bit case is also particularly important, as the constant "-1" is probably
161 ; just 32-bits wide. 182 ; just 32-bits wide.
162 define <2 x i64> @test_setcc_constfold_vi64(<2 x i64> %l, <2 x i64> %r) { 183 define <2 x i64> @test_setcc_constfold_vi64(<2 x i64> %l, <2 x i64> %r) {
184 ; SSE-LABEL: test_setcc_constfold_vi64:
185 ; SSE: # BB#0:
186 ; SSE-NEXT: pcmpeqd %xmm0, %xmm0
187 ; SSE-NEXT: retq
188 ;
189 ; AVX-LABEL: test_setcc_constfold_vi64:
190 ; AVX: # BB#0:
191 ; AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
192 ; AVX-NEXT: retq
163 %test1 = icmp eq <2 x i64> %l, %r 193 %test1 = icmp eq <2 x i64> %l, %r
164 %mask1 = sext <2 x i1> %test1 to <2 x i64> 194 %mask1 = sext <2 x i1> %test1 to <2 x i64>
165
166 %test2 = icmp ne <2 x i64> %l, %r 195 %test2 = icmp ne <2 x i64> %l, %r
167 %mask2 = sext <2 x i1> %test2 to <2 x i64> 196 %mask2 = sext <2 x i1> %test2 to <2 x i64>
168
169 %res = or <2 x i64> %mask1, %mask2 197 %res = or <2 x i64> %mask1, %mask2
170 ret <2 x i64> %res 198 ret <2 x i64> %res
171 ; SSE2-LABEL: test_setcc_constfold_vi64:
172 ; SSE2: pcmpeqd %xmm0, %xmm0
173
174 ; SSE41-LABEL: test_setcc_constfold_vi64:
175 ; SSE41: pcmpeqd %xmm0, %xmm0
176
177 ; AVX-LABEL: test_setcc_constfold_vi64:
178 ; AVX: vpcmpeqd %xmm0, %xmm0, %xmm0
179 } 199 }