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comparison test/Transforms/InstCombine/exact.ll @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents 95c75e76d11b
children 803732b1fca8
comparison
equal deleted inserted replaced
101:34baf5011add 120:1172e4bd9c6f
1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
1 ; RUN: opt < %s -instcombine -S | FileCheck %s 2 ; RUN: opt < %s -instcombine -S | FileCheck %s
2 3
4 define i32 @sdiv1(i32 %x) {
3 ; CHECK-LABEL: @sdiv1( 5 ; CHECK-LABEL: @sdiv1(
4 ; CHECK: sdiv i32 %x, 8 6 ; CHECK-NEXT: [[Y:%.*]] = sdiv i32 %x, 8
5 define i32 @sdiv1(i32 %x) { 7 ; CHECK-NEXT: ret i32 [[Y]]
8 ;
6 %y = sdiv i32 %x, 8 9 %y = sdiv i32 %x, 8
7 ret i32 %y 10 ret i32 %y
8 } 11 }
9 12
13 define i32 @sdiv2(i32 %x) {
10 ; CHECK-LABEL: @sdiv2( 14 ; CHECK-LABEL: @sdiv2(
11 ; CHECK: ashr exact i32 %x, 3 15 ; CHECK-NEXT: [[Y:%.*]] = ashr exact i32 %x, 3
12 define i32 @sdiv2(i32 %x) { 16 ; CHECK-NEXT: ret i32 [[Y]]
17 ;
13 %y = sdiv exact i32 %x, 8 18 %y = sdiv exact i32 %x, 8
14 ret i32 %y 19 ret i32 %y
15 } 20 }
16 21
22 define <2 x i32> @sdiv2_vec(<2 x i32> %x) {
23 ; CHECK-LABEL: @sdiv2_vec(
24 ; CHECK-NEXT: [[Y:%.*]] = ashr exact <2 x i32> %x, <i32 7, i32 7>
25 ; CHECK-NEXT: ret <2 x i32> [[Y]]
26 ;
27 %y = sdiv exact <2 x i32> %x, <i32 128, i32 128>
28 ret <2 x i32> %y
29 }
30
31 define i32 @sdiv3(i32 %x) {
17 ; CHECK-LABEL: @sdiv3( 32 ; CHECK-LABEL: @sdiv3(
18 ; CHECK: %y = srem i32 %x, 3 33 ; CHECK-NEXT: [[Y:%.*]] = srem i32 %x, 3
19 ; CHECK: %z = sub i32 %x, %y 34 ; CHECK-NEXT: [[Z:%.*]] = sub i32 %x, [[Y]]
20 ; CHECK: ret i32 %z 35 ; CHECK-NEXT: ret i32 [[Z]]
21 define i32 @sdiv3(i32 %x) { 36 ;
22 %y = sdiv i32 %x, 3 37 %y = sdiv i32 %x, 3
23 %z = mul i32 %y, 3 38 %z = mul i32 %y, 3
24 ret i32 %z 39 ret i32 %z
25 } 40 }
26 41
42 define i32 @sdiv4(i32 %x) {
27 ; CHECK-LABEL: @sdiv4( 43 ; CHECK-LABEL: @sdiv4(
28 ; CHECK: ret i32 %x 44 ; CHECK-NEXT: ret i32 %x
29 define i32 @sdiv4(i32 %x) { 45 ;
30 %y = sdiv exact i32 %x, 3 46 %y = sdiv exact i32 %x, 3
31 %z = mul i32 %y, 3 47 %z = mul i32 %y, 3
32 ret i32 %z 48 ret i32 %z
33 } 49 }
34 50
35 ; CHECK: i32 @sdiv5
36 ; CHECK: %y = srem i32 %x, 3
37 ; CHECK: %z = sub i32 %y, %x
38 ; CHECK: ret i32 %z
39 define i32 @sdiv5(i32 %x) { 51 define i32 @sdiv5(i32 %x) {
52 ; CHECK-LABEL: @sdiv5(
53 ; CHECK-NEXT: [[Y:%.*]] = srem i32 %x, 3
54 ; CHECK-NEXT: [[Z:%.*]] = sub i32 [[Y]], %x
55 ; CHECK-NEXT: ret i32 [[Z]]
56 ;
40 %y = sdiv i32 %x, 3 57 %y = sdiv i32 %x, 3
41 %z = mul i32 %y, -3 58 %z = mul i32 %y, -3
42 ret i32 %z 59 ret i32 %z
43 } 60 }
44 61
62 define i32 @sdiv6(i32 %x) {
45 ; CHECK-LABEL: @sdiv6( 63 ; CHECK-LABEL: @sdiv6(
46 ; CHECK: %z = sub i32 0, %x 64 ; CHECK-NEXT: [[Z:%.*]] = sub i32 0, %x
47 ; CHECK: ret i32 %z 65 ; CHECK-NEXT: ret i32 [[Z]]
48 define i32 @sdiv6(i32 %x) { 66 ;
49 %y = sdiv exact i32 %x, 3 67 %y = sdiv exact i32 %x, 3
50 %z = mul i32 %y, -3 68 %z = mul i32 %y, -3
51 ret i32 %z 69 ret i32 %z
52 } 70 }
53 71
72 define i32 @udiv1(i32 %x, i32 %w) {
54 ; CHECK-LABEL: @udiv1( 73 ; CHECK-LABEL: @udiv1(
55 ; CHECK: ret i32 %x 74 ; CHECK-NEXT: ret i32 %x
56 define i32 @udiv1(i32 %x, i32 %w) { 75 ;
57 %y = udiv exact i32 %x, %w 76 %y = udiv exact i32 %x, %w
58 %z = mul i32 %y, %w 77 %z = mul i32 %y, %w
59 ret i32 %z 78 ret i32 %z
60 } 79 }
61 80
81 define i32 @udiv2(i32 %x, i32 %w) {
62 ; CHECK-LABEL: @udiv2( 82 ; CHECK-LABEL: @udiv2(
63 ; CHECK: %z = lshr exact i32 %x, %w 83 ; CHECK-NEXT: [[Z:%.*]] = lshr exact i32 %x, %w
64 ; CHECK: ret i32 %z 84 ; CHECK-NEXT: ret i32 [[Z]]
65 define i32 @udiv2(i32 %x, i32 %w) { 85 ;
66 %y = shl i32 1, %w 86 %y = shl i32 1, %w
67 %z = udiv exact i32 %x, %y 87 %z = udiv exact i32 %x, %y
68 ret i32 %z 88 ret i32 %z
69 } 89 }
70 90
91 define i64 @ashr1(i64 %X) nounwind {
71 ; CHECK-LABEL: @ashr1( 92 ; CHECK-LABEL: @ashr1(
72 ; CHECK: %B = ashr exact i64 %A, 2 93 ; CHECK-NEXT: [[A:%.*]] = shl i64 %X, 8
73 ; CHECK: ret i64 %B 94 ; CHECK-NEXT: [[B:%.*]] = ashr exact i64 [[A]], 2
74 define i64 @ashr1(i64 %X) nounwind { 95 ; CHECK-NEXT: ret i64 [[B]]
96 ;
75 %A = shl i64 %X, 8 97 %A = shl i64 %X, 8
76 %B = ashr i64 %A, 2 ; X/4 98 %B = ashr i64 %A, 2 ; X/4
77 ret i64 %B 99 ret i64 %B
78 } 100 }
79 101
80 ; PR9120 102 ; PR9120
103 define i1 @ashr_icmp1(i64 %X) nounwind {
81 ; CHECK-LABEL: @ashr_icmp1( 104 ; CHECK-LABEL: @ashr_icmp1(
82 ; CHECK: %B = icmp eq i64 %X, 0 105 ; CHECK-NEXT: [[B:%.*]] = icmp eq i64 %X, 0
83 ; CHECK: ret i1 %B 106 ; CHECK-NEXT: ret i1 [[B]]
84 define i1 @ashr_icmp1(i64 %X) nounwind { 107 ;
85 %A = ashr exact i64 %X, 2 ; X/4 108 %A = ashr exact i64 %X, 2 ; X/4
86 %B = icmp eq i64 %A, 0 109 %B = icmp eq i64 %A, 0
87 ret i1 %B 110 ret i1 %B
88 } 111 }
89 112
113 define i1 @ashr_icmp2(i64 %X) {
90 ; CHECK-LABEL: @ashr_icmp2( 114 ; CHECK-LABEL: @ashr_icmp2(
91 ; CHECK: %Z = icmp slt i64 %X, 16 115 ; CHECK-NEXT: [[Z:%.*]] = icmp slt i64 %X, 16
92 ; CHECK: ret i1 %Z 116 ; CHECK-NEXT: ret i1 [[Z]]
93 define i1 @ashr_icmp2(i64 %X) nounwind { 117 ;
94 %Y = ashr exact i64 %X, 2 ; x / 4 118 %Y = ashr exact i64 %X, 2 ; x / 4
95 %Z = icmp slt i64 %Y, 4 ; x < 16 119 %Z = icmp slt i64 %Y, 4 ; x < 16
96 ret i1 %Z 120 ret i1 %Z
121 }
122
123 define <2 x i1> @ashr_icmp2_vec(<2 x i64> %X) {
124 ; CHECK-LABEL: @ashr_icmp2_vec(
125 ; CHECK-NEXT: [[Z:%.*]] = icmp slt <2 x i64> %X, <i64 16, i64 16>
126 ; CHECK-NEXT: ret <2 x i1> [[Z]]
127 ;
128 %Y = ashr exact <2 x i64> %X, <i64 2, i64 2>
129 %Z = icmp slt <2 x i64> %Y, <i64 4, i64 4>
130 ret <2 x i1> %Z
97 } 131 }
98 132
99 ; PR9998 133 ; PR9998
100 ; Make sure we don't transform the ashr here into an sdiv 134 ; Make sure we don't transform the ashr here into an sdiv
135 define i1 @pr9998(i32 %V) {
101 ; CHECK-LABEL: @pr9998( 136 ; CHECK-LABEL: @pr9998(
102 ; CHECK: [[BIT:%[A-Za-z0-9.]+]] = and i32 %V, 1 137 ; CHECK-NEXT: [[W_MASK:%.*]] = and i32 %V, 1
103 ; CHECK-NEXT: [[CMP:%[A-Za-z0-9.]+]] = icmp ne i32 [[BIT]], 0 138 ; CHECK-NEXT: [[Z:%.*]] = icmp ne i32 [[W_MASK]], 0
104 ; CHECK-NEXT: ret i1 [[CMP]] 139 ; CHECK-NEXT: ret i1 [[Z]]
105 define i1 @pr9998(i32 %V) nounwind { 140 ;
106 entry:
107 %W = shl i32 %V, 31 141 %W = shl i32 %V, 31
108 %X = ashr exact i32 %W, 31 142 %X = ashr exact i32 %W, 31
109 %Y = sext i32 %X to i64 143 %Y = sext i32 %X to i64
110 %Z = icmp ugt i64 %Y, 7297771788697658747 144 %Z = icmp ugt i64 %Y, 7297771788697658747
111 ret i1 %Z 145 ret i1 %Z
112 } 146 }
113 147
114 148 ; FIXME: Vectors should fold the same way.
115 149 define <2 x i1> @pr9998vec(<2 x i32> %V) {
150 ; CHECK-LABEL: @pr9998vec(
151 ; CHECK-NEXT: [[W:%.*]] = shl <2 x i32> %V, <i32 31, i32 31>
152 ; CHECK-NEXT: [[X:%.*]] = ashr exact <2 x i32> [[W]], <i32 31, i32 31>
153 ; CHECK-NEXT: [[Y:%.*]] = sext <2 x i32> [[X]] to <2 x i64>
154 ; CHECK-NEXT: [[Z:%.*]] = icmp ugt <2 x i64> [[Y]], <i64 7297771788697658747, i64 7297771788697658747>
155 ; CHECK-NEXT: ret <2 x i1> [[Z]]
156 ;
157 %W = shl <2 x i32> %V, <i32 31, i32 31>
158 %X = ashr exact <2 x i32> %W, <i32 31, i32 31>
159 %Y = sext <2 x i32> %X to <2 x i64>
160 %Z = icmp ugt <2 x i64> %Y, <i64 7297771788697658747, i64 7297771788697658747>
161 ret <2 x i1> %Z
162 }
163
164 define i1 @udiv_icmp1(i64 %X) {
116 ; CHECK-LABEL: @udiv_icmp1( 165 ; CHECK-LABEL: @udiv_icmp1(
117 ; CHECK: icmp ne i64 %X, 0 166 ; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 %X, 0
118 define i1 @udiv_icmp1(i64 %X) nounwind { 167 ; CHECK-NEXT: ret i1 [[TMP1]]
168 ;
119 %A = udiv exact i64 %X, 5 ; X/5 169 %A = udiv exact i64 %X, 5 ; X/5
120 %B = icmp ne i64 %A, 0 170 %B = icmp ne i64 %A, 0
121 ret i1 %B 171 ret i1 %B
122 } 172 }
123 173
174 define <2 x i1> @udiv_icmp1_vec(<2 x i64> %X) {
175 ; CHECK-LABEL: @udiv_icmp1_vec(
176 ; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <2 x i64> %X, zeroinitializer
177 ; CHECK-NEXT: ret <2 x i1> [[TMP1]]
178 ;
179 %A = udiv exact <2 x i64> %X, <i64 5, i64 5>
180 %B = icmp ne <2 x i64> %A, zeroinitializer
181 ret <2 x i1> %B
182 }
183
184 define i1 @udiv_icmp2(i64 %X) {
185 ; CHECK-LABEL: @udiv_icmp2(
186 ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 %X, 0
187 ; CHECK-NEXT: ret i1 [[TMP1]]
188 ;
189 %A = udiv exact i64 %X, 5 ; X/5 == 0 --> x == 0
190 %B = icmp eq i64 %A, 0
191 ret i1 %B
192 }
193
194 define <2 x i1> @udiv_icmp2_vec(<2 x i64> %X) {
195 ; CHECK-LABEL: @udiv_icmp2_vec(
196 ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i64> %X, zeroinitializer
197 ; CHECK-NEXT: ret <2 x i1> [[TMP1]]
198 ;
199 %A = udiv exact <2 x i64> %X, <i64 5, i64 5>
200 %B = icmp eq <2 x i64> %A, zeroinitializer
201 ret <2 x i1> %B
202 }
203
204 define i1 @sdiv_icmp1(i64 %X) {
124 ; CHECK-LABEL: @sdiv_icmp1( 205 ; CHECK-LABEL: @sdiv_icmp1(
125 ; CHECK: icmp eq i64 %X, 0 206 ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 %X, 0
126 define i1 @sdiv_icmp1(i64 %X) nounwind { 207 ; CHECK-NEXT: ret i1 [[TMP1]]
208 ;
127 %A = sdiv exact i64 %X, 5 ; X/5 == 0 --> x == 0 209 %A = sdiv exact i64 %X, 5 ; X/5 == 0 --> x == 0
128 %B = icmp eq i64 %A, 0 210 %B = icmp eq i64 %A, 0
129 ret i1 %B 211 ret i1 %B
130 } 212 }
131 213
214 define <2 x i1> @sdiv_icmp1_vec(<2 x i64> %X) {
215 ; CHECK-LABEL: @sdiv_icmp1_vec(
216 ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i64> %X, zeroinitializer
217 ; CHECK-NEXT: ret <2 x i1> [[TMP1]]
218 ;
219 %A = sdiv exact <2 x i64> %X, <i64 5, i64 5>
220 %B = icmp eq <2 x i64> %A, zeroinitializer
221 ret <2 x i1> %B
222 }
223
224 define i1 @sdiv_icmp2(i64 %X) {
132 ; CHECK-LABEL: @sdiv_icmp2( 225 ; CHECK-LABEL: @sdiv_icmp2(
133 ; CHECK: icmp eq i64 %X, 5 226 ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 %X, 5
134 define i1 @sdiv_icmp2(i64 %X) nounwind { 227 ; CHECK-NEXT: ret i1 [[TMP1]]
228 ;
135 %A = sdiv exact i64 %X, 5 ; X/5 == 1 --> x == 5 229 %A = sdiv exact i64 %X, 5 ; X/5 == 1 --> x == 5
136 %B = icmp eq i64 %A, 1 230 %B = icmp eq i64 %A, 1
137 ret i1 %B 231 ret i1 %B
138 } 232 }
139 233
234 define <2 x i1> @sdiv_icmp2_vec(<2 x i64> %X) {
235 ; CHECK-LABEL: @sdiv_icmp2_vec(
236 ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i64> %X, <i64 5, i64 5>
237 ; CHECK-NEXT: ret <2 x i1> [[TMP1]]
238 ;
239 %A = sdiv exact <2 x i64> %X, <i64 5, i64 5>
240 %B = icmp eq <2 x i64> %A, <i64 1, i64 1>
241 ret <2 x i1> %B
242 }
243
244 define i1 @sdiv_icmp3(i64 %X) {
140 ; CHECK-LABEL: @sdiv_icmp3( 245 ; CHECK-LABEL: @sdiv_icmp3(
141 ; CHECK: icmp eq i64 %X, -5 246 ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 %X, -5
142 define i1 @sdiv_icmp3(i64 %X) nounwind { 247 ; CHECK-NEXT: ret i1 [[TMP1]]
248 ;
143 %A = sdiv exact i64 %X, 5 ; X/5 == -1 --> x == -5 249 %A = sdiv exact i64 %X, 5 ; X/5 == -1 --> x == -5
144 %B = icmp eq i64 %A, -1 250 %B = icmp eq i64 %A, -1
145 ret i1 %B 251 ret i1 %B
146 } 252 }
147 253
254 define <2 x i1> @sdiv_icmp3_vec(<2 x i64> %X) {
255 ; CHECK-LABEL: @sdiv_icmp3_vec(
256 ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i64> %X, <i64 -5, i64 -5>
257 ; CHECK-NEXT: ret <2 x i1> [[TMP1]]
258 ;
259 %A = sdiv exact <2 x i64> %X, <i64 5, i64 5>
260 %B = icmp eq <2 x i64> %A, <i64 -1, i64 -1>
261 ret <2 x i1> %B
262 }
263
264 define i1 @sdiv_icmp4(i64 %X) {
148 ; CHECK-LABEL: @sdiv_icmp4( 265 ; CHECK-LABEL: @sdiv_icmp4(
149 ; CHECK: icmp eq i64 %X, 0 266 ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 %X, 0
150 define i1 @sdiv_icmp4(i64 %X) nounwind { 267 ; CHECK-NEXT: ret i1 [[TMP1]]
268 ;
151 %A = sdiv exact i64 %X, -5 ; X/-5 == 0 --> x == 0 269 %A = sdiv exact i64 %X, -5 ; X/-5 == 0 --> x == 0
152 %B = icmp eq i64 %A, 0 270 %B = icmp eq i64 %A, 0
153 ret i1 %B 271 ret i1 %B
154 } 272 }
155 273
274 define <2 x i1> @sdiv_icmp4_vec(<2 x i64> %X) {
275 ; CHECK-LABEL: @sdiv_icmp4_vec(
276 ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i64> %X, zeroinitializer
277 ; CHECK-NEXT: ret <2 x i1> [[TMP1]]
278 ;
279 %A = sdiv exact <2 x i64> %X, <i64 -5, i64 -5>
280 %B = icmp eq <2 x i64> %A, zeroinitializer
281 ret <2 x i1> %B
282 }
283
284 define i1 @sdiv_icmp5(i64 %X) {
156 ; CHECK-LABEL: @sdiv_icmp5( 285 ; CHECK-LABEL: @sdiv_icmp5(
157 ; CHECK: icmp eq i64 %X, -5 286 ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 %X, -5
158 define i1 @sdiv_icmp5(i64 %X) nounwind { 287 ; CHECK-NEXT: ret i1 [[TMP1]]
288 ;
159 %A = sdiv exact i64 %X, -5 ; X/-5 == 1 --> x == -5 289 %A = sdiv exact i64 %X, -5 ; X/-5 == 1 --> x == -5
160 %B = icmp eq i64 %A, 1 290 %B = icmp eq i64 %A, 1
161 ret i1 %B 291 ret i1 %B
162 } 292 }
163 293
294 define <2 x i1> @sdiv_icmp5_vec(<2 x i64> %X) {
295 ; CHECK-LABEL: @sdiv_icmp5_vec(
296 ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i64> %X, <i64 -5, i64 -5>
297 ; CHECK-NEXT: ret <2 x i1> [[TMP1]]
298 ;
299 %A = sdiv exact <2 x i64> %X, <i64 -5, i64 -5>
300 %B = icmp eq <2 x i64> %A, <i64 1, i64 1>
301 ret <2 x i1> %B
302 }
303
304 define i1 @sdiv_icmp6(i64 %X) {
164 ; CHECK-LABEL: @sdiv_icmp6( 305 ; CHECK-LABEL: @sdiv_icmp6(
165 ; CHECK: icmp eq i64 %X, 5 306 ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 %X, 5
166 define i1 @sdiv_icmp6(i64 %X) nounwind { 307 ; CHECK-NEXT: ret i1 [[TMP1]]
167 %A = sdiv exact i64 %X, -5 ; X/-5 == 1 --> x == 5 308 ;
309 %A = sdiv exact i64 %X, -5 ; X/-5 == -1 --> x == 5
168 %B = icmp eq i64 %A, -1 310 %B = icmp eq i64 %A, -1
169 ret i1 %B 311 ret i1 %B
170 } 312 }
171 313
314 define <2 x i1> @sdiv_icmp6_vec(<2 x i64> %X) {
315 ; CHECK-LABEL: @sdiv_icmp6_vec(
316 ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i64> %X, <i64 5, i64 5>
317 ; CHECK-NEXT: ret <2 x i1> [[TMP1]]
318 ;
319 %A = sdiv exact <2 x i64> %X, <i64 -5, i64 -5>
320 %B = icmp eq <2 x i64> %A, <i64 -1, i64 -1>
321 ret <2 x i1> %B
322 }
323