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comparison llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.ll @ 150:1d019706d866

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LLVM10
author anatofuz
date Thu, 13 Feb 2020 15:10:13 +0900
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children 2e18cbf3894f
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147:c2174574ed3a 150:1d019706d866
1 ;RUN: llc < %s -march=amdgcn -mcpu=verde -amdgpu-atomic-optimizations=false -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=SICI
2 ;RUN: llc < %s -march=amdgcn -mcpu=tonga -amdgpu-atomic-optimizations=false -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=VI
3
4 ;CHECK-LABEL: {{^}}test1:
5 ;CHECK-NOT: s_waitcnt
6 ;CHECK: buffer_atomic_swap v0, off, s[0:3], 0 glc
7 ;CHECK: s_movk_i32 [[SOFS:s[0-9]+]], 0x1ffc
8 ;CHECK: s_waitcnt vmcnt(0)
9 ;CHECK: buffer_atomic_swap v0, v1, s[0:3], 0 offen glc
10 ;CHECK: s_waitcnt vmcnt(0)
11 ;CHECK: buffer_atomic_swap v0, v1, s[0:3], 0 offen offset:42 glc
12 ;CHECK-DAG: s_waitcnt vmcnt(0)
13 ;CHECK: buffer_atomic_swap v0, off, s[0:3], [[SOFS]] offset:4 glc
14 ;CHECK: s_waitcnt vmcnt(0)
15 ;CHECK: buffer_atomic_swap v0, off, s[0:3], 0{{$}}
16 define amdgpu_ps float @test1(<4 x i32> inreg %rsrc, i32 %data, i32 %voffset) {
17 main_body:
18 %o1 = call i32 @llvm.amdgcn.raw.buffer.atomic.swap.i32(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i32 0)
19 %o3 = call i32 @llvm.amdgcn.raw.buffer.atomic.swap.i32(i32 %o1, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 0)
20 %off5 = add i32 %voffset, 42
21 %o5 = call i32 @llvm.amdgcn.raw.buffer.atomic.swap.i32(i32 %o3, <4 x i32> %rsrc, i32 %off5, i32 0, i32 0)
22 %o6 = call i32 @llvm.amdgcn.raw.buffer.atomic.swap.i32(i32 %o5, <4 x i32> %rsrc, i32 4, i32 8188, i32 0)
23 %unused = call i32 @llvm.amdgcn.raw.buffer.atomic.swap.i32(i32 %o6, <4 x i32> %rsrc, i32 0, i32 0, i32 0)
24 %out = bitcast i32 %o6 to float
25 ret float %out
26 }
27
28 ;CHECK-LABEL: {{^}}test2:
29 ;CHECK-NOT: s_waitcnt
30 ;CHECK: buffer_atomic_add v0, v1, s[0:3], 0 offen glc{{$}}
31 ;CHECK: s_waitcnt vmcnt(0)
32 ;CHECK: buffer_atomic_sub v0, v1, s[0:3], 0 offen glc slc
33 ;CHECK: s_waitcnt vmcnt(0)
34 ;CHECK: buffer_atomic_smin v0, v1, s[0:3], 0 offen glc{{$}}
35 ;CHECK: s_waitcnt vmcnt(0)
36 ;CHECK: buffer_atomic_umin v0, v1, s[0:3], 0 offen glc slc
37 ;CHECK: s_waitcnt vmcnt(0)
38 ;CHECK: buffer_atomic_smax v0, v1, s[0:3], 0 offen glc{{$}}
39 ;CHECK: s_waitcnt vmcnt(0)
40 ;CHECK: buffer_atomic_umax v0, v1, s[0:3], 0 offen glc slc
41 ;CHECK: s_waitcnt vmcnt(0)
42 ;CHECK: buffer_atomic_and v0, v1, s[0:3], 0 offen glc{{$}}
43 ;CHECK: s_waitcnt vmcnt(0)
44 ;CHECK: buffer_atomic_or v0, v1, s[0:3], 0 offen glc slc
45 ;CHECK: s_waitcnt vmcnt(0)
46 ;CHECK: buffer_atomic_xor v0, v1, s[0:3], 0 offen glc
47 ;CHECK: s_waitcnt vmcnt(0)
48 ;CHECK: buffer_atomic_inc v0, v1, s[0:3], 0 offen glc
49 ;CHECK: s_waitcnt vmcnt(0)
50 ;CHECK: buffer_atomic_dec v0, v1, s[0:3], 0 offen glc
51 define amdgpu_ps float @test2(<4 x i32> inreg %rsrc, i32 %data, i32 %voffset) {
52 main_body:
53 %t1 = call i32 @llvm.amdgcn.raw.buffer.atomic.add.i32(i32 %data, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 0)
54 %t2 = call i32 @llvm.amdgcn.raw.buffer.atomic.sub.i32(i32 %t1, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 2)
55 %t3 = call i32 @llvm.amdgcn.raw.buffer.atomic.smin.i32(i32 %t2, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 0)
56 %t4 = call i32 @llvm.amdgcn.raw.buffer.atomic.umin.i32(i32 %t3, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 2)
57 %t5 = call i32 @llvm.amdgcn.raw.buffer.atomic.smax.i32(i32 %t4, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 0)
58 %t6 = call i32 @llvm.amdgcn.raw.buffer.atomic.umax.i32(i32 %t5, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 2)
59 %t7 = call i32 @llvm.amdgcn.raw.buffer.atomic.and.i32(i32 %t6, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 0)
60 %t8 = call i32 @llvm.amdgcn.raw.buffer.atomic.or.i32(i32 %t7, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 2)
61 %t9 = call i32 @llvm.amdgcn.raw.buffer.atomic.xor.i32(i32 %t8, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 0)
62 %t10 = call i32 @llvm.amdgcn.raw.buffer.atomic.inc.i32(i32 %t9, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 0)
63 %t11 = call i32 @llvm.amdgcn.raw.buffer.atomic.dec.i32(i32 %t10, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 0)
64 %out = bitcast i32 %t11 to float
65 ret float %out
66 }
67
68 ; Ideally, we would teach tablegen & friends that cmpswap only modifies the
69 ; first vgpr. Since we don't do that yet, the register allocator will have to
70 ; create copies which we don't bother to track here.
71 ;
72 ;CHECK-LABEL: {{^}}test3:
73 ;CHECK-NOT: s_waitcnt
74 ;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], 0 glc
75 ;CHECK: s_waitcnt vmcnt(0)
76 ;CHECK: s_movk_i32 [[SOFS:s[0-9]+]], 0x1ffc
77 ;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, v2, s[0:3], 0 offen glc
78 ;CHECK: s_waitcnt vmcnt(0)
79 ;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, v2, s[0:3], 0 offen offset:44 glc
80 ;CHECK-DAG: s_waitcnt vmcnt(0)
81 ;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], [[SOFS]] offset:4 glc
82 define amdgpu_ps float @test3(<4 x i32> inreg %rsrc, i32 %data, i32 %cmp, i32 %vindex, i32 %voffset) {
83 main_body:
84 %o1 = call i32 @llvm.amdgcn.raw.buffer.atomic.cmpswap.i32(i32 %data, i32 %cmp, <4 x i32> %rsrc, i32 0, i32 0, i32 0)
85 %o3 = call i32 @llvm.amdgcn.raw.buffer.atomic.cmpswap.i32(i32 %o1, i32 %cmp, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 0)
86 %ofs.5 = add i32 %voffset, 44
87 %o5 = call i32 @llvm.amdgcn.raw.buffer.atomic.cmpswap.i32(i32 %o3, i32 %cmp, <4 x i32> %rsrc, i32 %ofs.5, i32 0, i32 0)
88 %o6 = call i32 @llvm.amdgcn.raw.buffer.atomic.cmpswap.i32(i32 %o5, i32 %cmp, <4 x i32> %rsrc, i32 4, i32 8188, i32 0)
89
90 ; Detecting the no-return variant doesn't work right now because of how the
91 ; intrinsic is replaced by an instruction that feeds into an EXTRACT_SUBREG.
92 ; Since there probably isn't a reasonable use-case of cmpswap that discards
93 ; the return value, that seems okay.
94 ;
95 ; %unused = call i32 @llvm.amdgcn.raw.buffer.atomic.cmpswap.i32(i32 %o6, i32 %cmp, <4 x i32> %rsrc, i32 0, i32 0, i32 0)
96 %out = bitcast i32 %o6 to float
97 ret float %out
98 }
99
100 ;CHECK-LABEL: {{^}}test4:
101 ;CHECK: buffer_atomic_add v0,
102 define amdgpu_ps float @test4() {
103 main_body:
104 %v = call i32 @llvm.amdgcn.raw.buffer.atomic.add.i32(i32 1, <4 x i32> undef, i32 4, i32 0, i32 0)
105 %v.float = bitcast i32 %v to float
106 ret float %v.float
107 }
108
109 declare i32 @llvm.amdgcn.raw.buffer.atomic.swap.i32(i32, <4 x i32>, i32, i32, i32) #0
110 declare i32 @llvm.amdgcn.raw.buffer.atomic.add.i32(i32, <4 x i32>, i32, i32, i32) #0
111 declare i32 @llvm.amdgcn.raw.buffer.atomic.sub.i32(i32, <4 x i32>, i32, i32, i32) #0
112 declare i32 @llvm.amdgcn.raw.buffer.atomic.smin.i32(i32, <4 x i32>, i32, i32, i32) #0
113 declare i32 @llvm.amdgcn.raw.buffer.atomic.umin.i32(i32, <4 x i32>, i32, i32, i32) #0
114 declare i32 @llvm.amdgcn.raw.buffer.atomic.smax.i32(i32, <4 x i32>, i32, i32, i32) #0
115 declare i32 @llvm.amdgcn.raw.buffer.atomic.umax.i32(i32, <4 x i32>, i32, i32, i32) #0
116 declare i32 @llvm.amdgcn.raw.buffer.atomic.and.i32(i32, <4 x i32>, i32, i32, i32) #0
117 declare i32 @llvm.amdgcn.raw.buffer.atomic.or.i32(i32, <4 x i32>, i32, i32, i32) #0
118 declare i32 @llvm.amdgcn.raw.buffer.atomic.xor.i32(i32, <4 x i32>, i32, i32, i32) #0
119 declare i32 @llvm.amdgcn.raw.buffer.atomic.inc.i32(i32, <4 x i32>, i32, i32, i32) #0
120 declare i32 @llvm.amdgcn.raw.buffer.atomic.dec.i32(i32, <4 x i32>, i32, i32, i32) #0
121 declare i32 @llvm.amdgcn.raw.buffer.atomic.cmpswap.i32(i32, i32, <4 x i32>, i32, i32, i32) #0
122
123 attributes #0 = { nounwind }