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comparison llvm/test/TableGen/InvalidMCSchedClassDesc.td @ 150:1d019706d866

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LLVM10
author anatofuz
date Thu, 13 Feb 2020 15:10:13 +0900
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children 2e18cbf3894f
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147:c2174574ed3a 150:1d019706d866
1 // RUN: llvm-tblgen -gen-subtarget -I %p/../../include %s 2>&1 | FileCheck %s
2 // Check if it is valid MCSchedClassDesc if didn't have the resources.
3
4 include "llvm/Target/Target.td"
5
6 def MyTarget : Target;
7
8 let OutOperandList = (outs), InOperandList = (ins) in {
9 def Inst_A : Instruction;
10 def Inst_B : Instruction;
11 }
12
13 let CompleteModel = 0 in {
14 def SchedModel_A: SchedMachineModel;
15 def SchedModel_B: SchedMachineModel;
16 def SchedModel_C: SchedMachineModel;
17 }
18
19 // Inst_B didn't have the resoures, and it is invalid.
20 // CHECK: SchedModel_ASchedClasses[] = {
21 // CHECK: {DBGFIELD("Inst_A") 1
22 // CHECK-NEXT: {DBGFIELD("Inst_B") 16383
23 let SchedModel = SchedModel_A in {
24 def Write_A : SchedWriteRes<[]>;
25 def : InstRW<[Write_A], (instrs Inst_A)>;
26 }
27
28 // Inst_A didn't have the resoures, and it is invalid.
29 // CHECK: SchedModel_BSchedClasses[] = {
30 // CHECK: {DBGFIELD("Inst_A") 16383
31 // CHECK-NEXT: {DBGFIELD("Inst_B") 1
32 let SchedModel = SchedModel_B in {
33 def Write_B: SchedWriteRes<[]>;
34 def : InstRW<[Write_B], (instrs Inst_B)>;
35 }
36
37 // CHECK: SchedModel_CSchedClasses[] = {
38 // CHECK: {DBGFIELD("Inst_A") 1
39 // CHECK-NEXT: {DBGFIELD("Inst_B") 1
40 let SchedModel = SchedModel_C in {
41 def Write_C: SchedWriteRes<[]>;
42 def : InstRW<[Write_C], (instrs Inst_A, Inst_B)>;
43 }
44
45 def ProcessorA: ProcessorModel<"ProcessorA", SchedModel_A, []>;
46 def ProcessorB: ProcessorModel<"ProcessorB", SchedModel_B, []>;
47 def ProcessorC: ProcessorModel<"ProcessorC", SchedModel_C, []>;