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comparison llvm/test/TableGen/dag-isel-res-order.td @ 150:1d019706d866

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LLVM10
author anatofuz
date Thu, 13 Feb 2020 15:10:13 +0900
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147:c2174574ed3a 150:1d019706d866
1 // RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s | FileCheck %s
2
3 include "llvm/Target/Target.td"
4
5 def TestTargetInstrInfo : InstrInfo;
6
7 def TestTarget : Target {
8 let InstructionSet = TestTargetInstrInfo;
9 }
10
11 def REG : Register<"REG">;
12 def GPR : RegisterClass<"TestTarget", [i32], 32, (add REG)>;
13
14 // CHECK-LABEL: OPC_CheckOpcode, TARGET_VAL(ISD::UDIVREM)
15 // CHECK: OPC_EmitNode2, TARGET_VAL(::INSTR)
16 // CHECK: Results = #2 #3
17 // CHECK: OPC_CompleteMatch, 2, 3, 2
18 def INSTR : Instruction {
19 let OutOperandList = (outs GPR:$r1, GPR:$r0);
20 let InOperandList = (ins GPR:$t0, GPR:$t1);
21 let Pattern = [(set i32:$r0, i32:$r1, (udivrem i32:$t0, i32:$t1))];
22 }