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comparison llvm/test/TableGen/gisel-physreg-input.td @ 150:1d019706d866

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LLVM10
author anatofuz
date Thu, 13 Feb 2020 15:10:13 +0900
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147:c2174574ed3a 150:1d019706d866
1 // RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
2
3 include "llvm/Target/Target.td"
4
5 def TestTargetInstrInfo : InstrInfo;
6
7 def TestTarget : Target {
8 let InstructionSet = TestTargetInstrInfo;
9 }
10
11 def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
12 def SPECIAL : Register<"special"> { let Namespace = "MyTarget"; }
13 def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
14 def Special32 : RegisterClass<"MyTarget", [i32], 32, (add SPECIAL)>;
15
16
17 class I<dag OOps, dag IOps, list<dag> Pat>
18 : Instruction {
19 let Namespace = "MyTarget";
20 let OutOperandList = OOps;
21 let InOperandList = IOps;
22 let Pattern = Pat;
23 }
24
25 // Try a normal physical register use.
26
27 // GISEL: GIM_Try,
28 // GISEL-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
29 // GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD,
30 // GISEL-NEXT: // MIs[0] dst
31 // GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
32 // GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
33 // GISEL-NEXT: // MIs[0] src0
34 // GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
35 // GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
36 // GISEL-NEXT: // MIs[0] Operand 2
37 // GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
38 // GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::Special32RegClassID,
39 // GISEL-NEXT: // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src0, SPECIAL:{ *:[i32] }) => (ADD_PHYS:{ *:[i32] } GPR32:{ *:[i32] }:$src0)
40 // GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
41 // GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, MyTarget::SPECIAL, /*AddRegisterRegFlags*/RegState::Define,
42 // GISEL-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // SPECIAL
43 // GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::ADD_PHYS,
44 // GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
45 // GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
46 // GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0,
47 // GISEL-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48 def ADD_PHYS : I<(outs GPR32:$dst), (ins GPR32:$src0),
49 [(set GPR32:$dst, (add GPR32:$src0, SPECIAL))]> {
50 let Uses = [SPECIAL];
51 }
52
53 // Try using the name of the physreg in another operand.
54
55 // GISEL: GIM_Try,
56 // GISEL-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
57 // GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_MUL,
58 // GISEL-NEXT: // MIs[0] dst
59 // GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
60 // GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
61 // GISEL-NEXT: // MIs[0] SPECIAL
62 // GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
63 // GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
64 // GISEL-NEXT: // MIs[0] Operand 2
65 // GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
66 // GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::Special32RegClassID,
67 // GISEL-NEXT: // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$SPECIAL, SPECIAL:{ *:[i32] }) => (MUL_PHYS:{ *:[i32] } GPR32:{ *:[i32] }:$SPECIAL)
68 // GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
69 // GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, MyTarget::SPECIAL, /*AddRegisterRegFlags*/RegState::Define,
70 // GISEL-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // SPECIAL
71 // GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MUL_PHYS,
72 // GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
73 // GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // SPECIAL
74 // GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0,
75 // GISEL-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
76 def MUL_PHYS : I<(outs GPR32:$dst), (ins GPR32:$SPECIAL),
77 [(set GPR32:$dst, (mul GPR32:$SPECIAL, SPECIAL))]> {
78 let Uses = [SPECIAL];
79 }
80
81 // Try giving the physical operand a name
82 // def ADD_PHYS : I<(outs GPR32:$dst), (ins GPR32:$src0),
83 // [(set GPR32:$dst, (add GPR32:$src0, SPECIAL:$special))]> {
84 // let Uses = [SPECIAL];
85 // }