Mercurial > hg > CbC > CbC_llvm

comparison llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @ 252:1f2b6ac9f198 llvm-original

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
LLVM16-1
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Fri, 18 Aug 2023 09:04:13 +0900
parents c4bab56944e8
children
comparison
equal deleted inserted replaced
237:c80f45b162ad 252:1f2b6ac9f198
17 #include "HexagonRegisterInfo.h" 17 #include "HexagonRegisterInfo.h"
18 #include "HexagonSubtarget.h" 18 #include "HexagonSubtarget.h"
19 #include "llvm/ADT/ArrayRef.h" 19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/SmallPtrSet.h" 20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/SmallVector.h" 21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/ADT/StringRef.h" 23 #include "llvm/ADT/StringRef.h"
23 #include "llvm/CodeGen/DFAPacketizer.h" 24 #include "llvm/CodeGen/DFAPacketizer.h"
24 #include "llvm/CodeGen/LivePhysRegs.h" 25 #include "llvm/CodeGen/LivePhysRegs.h"
25 #include "llvm/CodeGen/MachineBasicBlock.h" 26 #include "llvm/CodeGen/MachineBasicBlock.h"
26 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h" 27 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
31 #include "llvm/CodeGen/MachineInstrBundle.h" 32 #include "llvm/CodeGen/MachineInstrBundle.h"
32 #include "llvm/CodeGen/MachineLoopInfo.h" 33 #include "llvm/CodeGen/MachineLoopInfo.h"
33 #include "llvm/CodeGen/MachineMemOperand.h" 34 #include "llvm/CodeGen/MachineMemOperand.h"
34 #include "llvm/CodeGen/MachineOperand.h" 35 #include "llvm/CodeGen/MachineOperand.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h" 36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/MachineValueType.h"
36 #include "llvm/CodeGen/ScheduleDAG.h" 38 #include "llvm/CodeGen/ScheduleDAG.h"
37 #include "llvm/CodeGen/TargetInstrInfo.h" 39 #include "llvm/CodeGen/TargetInstrInfo.h"
38 #include "llvm/CodeGen/TargetOpcodes.h" 40 #include "llvm/CodeGen/TargetOpcodes.h"
39 #include "llvm/CodeGen/TargetRegisterInfo.h" 41 #include "llvm/CodeGen/TargetRegisterInfo.h"
40 #include "llvm/CodeGen/TargetSubtargetInfo.h" 42 #include "llvm/CodeGen/TargetSubtargetInfo.h"
46 #include "llvm/MC/MCRegisterInfo.h" 48 #include "llvm/MC/MCRegisterInfo.h"
47 #include "llvm/Support/BranchProbability.h" 49 #include "llvm/Support/BranchProbability.h"
48 #include "llvm/Support/CommandLine.h" 50 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h" 51 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h" 52 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MachineValueType.h"
52 #include "llvm/Support/MathExtras.h" 53 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h" 54 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetMachine.h" 55 #include "llvm/Target/TargetMachine.h"
55 #include <cassert> 56 #include <cassert>
56 #include <cctype> 57 #include <cctype>
57 #include <cstdint> 58 #include <cstdint>
58 #include <cstring> 59 #include <cstring>
59 #include <iterator> 60 #include <iterator>
61 #include <optional>
60 #include <string> 62 #include <string>
61 #include <utility> 63 #include <utility>
62 64
63 using namespace llvm; 65 using namespace llvm;
64 66
124 namespace HexagonFUnits { 126 namespace HexagonFUnits {
125 bool isSlot0Only(unsigned units); 127 bool isSlot0Only(unsigned units);
126 } 128 }
127 } 129 }
128 130
129 static bool isIntRegForSubInst(unsigned Reg) { 131 static bool isIntRegForSubInst(Register Reg) {
130 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) || 132 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
131 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23); 133 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23);
132 } 134 }
133 135
134 static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) { 136 static bool isDblRegForSubInst(Register Reg, const HexagonRegisterInfo &HRI) {
135 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) && 137 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) &&
136 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi)); 138 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi));
137 } 139 }
138 140
139 /// Calculate number of instructions excluding the debug instructions. 141 /// Calculate number of instructions excluding the debug instructions.
231 233
232 /// Gather register def/uses from MI. 234 /// Gather register def/uses from MI.
233 /// This treats possible (predicated) defs as actually happening ones 235 /// This treats possible (predicated) defs as actually happening ones
234 /// (conservatively). 236 /// (conservatively).
235 static inline void parseOperands(const MachineInstr &MI, 237 static inline void parseOperands(const MachineInstr &MI,
236 SmallVector<unsigned, 4> &Defs, SmallVector<unsigned, 8> &Uses) { 238 SmallVectorImpl<Register> &Defs, SmallVectorImpl<Register> &Uses) {
237 Defs.clear(); 239 Defs.clear();
238 Uses.clear(); 240 Uses.clear();
239 241
240 for (const MachineOperand &MO : MI.operands()) { 242 for (const MachineOperand &MO : MI.operands()) {
241 if (!MO.isReg()) 243 if (!MO.isReg())
748 bool shouldIgnoreForPipelining(const MachineInstr *MI) const override { 750 bool shouldIgnoreForPipelining(const MachineInstr *MI) const override {
749 // Only ignore the terminator. 751 // Only ignore the terminator.
750 return MI == EndLoop; 752 return MI == EndLoop;
751 } 753 }
752 754
753 Optional<bool> 755 std::optional<bool> createTripCountGreaterCondition(
754 createTripCountGreaterCondition(int TC, MachineBasicBlock &MBB, 756 int TC, MachineBasicBlock &MBB,
755 SmallVectorImpl<MachineOperand> &Cond) override { 757 SmallVectorImpl<MachineOperand> &Cond) override {
756 if (TripCount == -1) { 758 if (TripCount == -1) {
757 // Check if we're done with the loop. 759 // Check if we're done with the loop.
758 unsigned Done = TII->createVR(MF, MVT::i1); 760 Register Done = TII->createVR(MF, MVT::i1);
759 MachineInstr *NewCmp = BuildMI(&MBB, DL, 761 MachineInstr *NewCmp = BuildMI(&MBB, DL,
760 TII->get(Hexagon::C2_cmpgtui), Done) 762 TII->get(Hexagon::C2_cmpgtui), Done)
761 .addReg(LoopCount) 763 .addReg(LoopCount)
762 .addImm(TC); 764 .addImm(TC);
763 Cond.push_back(MachineOperand::CreateImm(Hexagon::J2_jumpf)); 765 Cond.push_back(MachineOperand::CreateImm(Hexagon::J2_jumpf));
951 #endif 953 #endif
952 llvm_unreachable("Unimplemented"); 954 llvm_unreachable("Unimplemented");
953 } 955 }
954 956
955 void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 957 void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
956 MachineBasicBlock::iterator I, Register SrcReg, bool isKill, int FI, 958 MachineBasicBlock::iterator I,
957 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { 959 Register SrcReg, bool isKill, int FI,
960 const TargetRegisterClass *RC,
961 const TargetRegisterInfo *TRI,
962 Register VReg) const {
958 DebugLoc DL = MBB.findDebugLoc(I); 963 DebugLoc DL = MBB.findDebugLoc(I);
959 MachineFunction &MF = *MBB.getParent(); 964 MachineFunction &MF = *MBB.getParent();
960 MachineFrameInfo &MFI = MF.getFrameInfo(); 965 MachineFrameInfo &MFI = MF.getFrameInfo();
961 unsigned KillFlag = getKillRegState(isKill); 966 unsigned KillFlag = getKillRegState(isKill);
962 967
995 } else { 1000 } else {
996 llvm_unreachable("Unimplemented"); 1001 llvm_unreachable("Unimplemented");
997 } 1002 }
998 } 1003 }
999 1004
1000 void HexagonInstrInfo::loadRegFromStackSlot( 1005 void HexagonInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
1001 MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg, 1006 MachineBasicBlock::iterator I,
1002 int FI, const TargetRegisterClass *RC, 1007 Register DestReg, int FI,
1003 const TargetRegisterInfo *TRI) const { 1008 const TargetRegisterClass *RC,
1009 const TargetRegisterInfo *TRI,
1010 Register VReg) const {
1004 DebugLoc DL = MBB.findDebugLoc(I); 1011 DebugLoc DL = MBB.findDebugLoc(I);
1005 MachineFunction &MF = *MBB.getParent(); 1012 MachineFunction &MF = *MBB.getParent();
1006 MachineFrameInfo &MFI = MF.getFrameInfo(); 1013 MachineFrameInfo &MFI = MF.getFrameInfo();
1007 1014
1008 MachineMemOperand *MMO = MF.getMachineMemOperand( 1015 MachineMemOperand *MMO = MF.getMachineMemOperand(
1050 DebugLoc DL = MI.getDebugLoc(); 1057 DebugLoc DL = MI.getDebugLoc();
1051 unsigned Opc = MI.getOpcode(); 1058 unsigned Opc = MI.getOpcode();
1052 1059
1053 auto RealCirc = [&](unsigned Opc, bool HasImm, unsigned MxOp) { 1060 auto RealCirc = [&](unsigned Opc, bool HasImm, unsigned MxOp) {
1054 Register Mx = MI.getOperand(MxOp).getReg(); 1061 Register Mx = MI.getOperand(MxOp).getReg();
1055 unsigned CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1); 1062 Register CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1);
1056 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrrcr), CSx) 1063 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrrcr), CSx)
1057 .add(MI.getOperand((HasImm ? 5 : 4))); 1064 .add(MI.getOperand((HasImm ? 5 : 4)));
1058 auto MIB = BuildMI(MBB, MI, DL, get(Opc)).add(MI.getOperand(0)) 1065 auto MIB = BuildMI(MBB, MI, DL, get(Opc)).add(MI.getOperand(0))
1059 .add(MI.getOperand(1)).add(MI.getOperand(2)).add(MI.getOperand(3)); 1066 .add(MI.getOperand(1)).add(MI.getOperand(2)).add(MI.getOperand(3));
1060 if (HasImm) 1067 if (HasImm)
1688 break; 1695 break;
1689 T.add(Op); 1696 T.add(Op);
1690 NOp++; 1697 NOp++;
1691 } 1698 }
1692 1699
1693 unsigned PredReg, PredRegPos, PredRegFlags; 1700 Register PredReg;
1701 unsigned PredRegPos, PredRegFlags;
1694 bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags); 1702 bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1695 (void)GotPredReg; 1703 (void)GotPredReg;
1696 assert(GotPredReg); 1704 assert(GotPredReg);
1697 T.addReg(PredReg, PredRegFlags); 1705 T.addReg(PredReg, PredRegFlags);
1698 while (NOp < NumOps) 1706 while (NOp < NumOps)
1732 Pred.push_back(MO); 1740 Pred.push_back(MO);
1733 return true; 1741 return true;
1734 } 1742 }
1735 continue; 1743 continue;
1736 } else if (MO.isRegMask()) { 1744 } else if (MO.isRegMask()) {
1737 for (unsigned PR : Hexagon::PredRegsRegClass) { 1745 for (Register PR : Hexagon::PredRegsRegClass) {
1738 if (!MI.modifiesRegister(PR, &HRI)) 1746 if (!MI.modifiesRegister(PR, &HRI))
1739 continue; 1747 continue;
1740 Pred.push_back(MO); 1748 Pred.push_back(MO);
1741 return true; 1749 return true;
1742 } 1750 }
2074 {MO_GDPLT, "hexagon-gdplt"}, 2082 {MO_GDPLT, "hexagon-gdplt"},
2075 {MO_IE, "hexagon-ie"}, 2083 {MO_IE, "hexagon-ie"},
2076 {MO_IEGOT, "hexagon-iegot"}, 2084 {MO_IEGOT, "hexagon-iegot"},
2077 {MO_TPREL, "hexagon-tprel"} 2085 {MO_TPREL, "hexagon-tprel"}
2078 }; 2086 };
2079 return makeArrayRef(Flags); 2087 return ArrayRef(Flags);
2080 } 2088 }
2081 2089
2082 ArrayRef<std::pair<unsigned, const char*>> 2090 ArrayRef<std::pair<unsigned, const char*>>
2083 HexagonInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const { 2091 HexagonInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
2084 using namespace HexagonII; 2092 using namespace HexagonII;
2085 2093
2086 static const std::pair<unsigned, const char*> Flags[] = { 2094 static const std::pair<unsigned, const char*> Flags[] = {
2087 {HMOTF_ConstExtended, "hexagon-ext"} 2095 {HMOTF_ConstExtended, "hexagon-ext"}
2088 }; 2096 };
2089 return makeArrayRef(Flags); 2097 return ArrayRef(Flags);
2090 } 2098 }
2091 2099
2092 unsigned HexagonInstrInfo::createVR(MachineFunction *MF, MVT VT) const { 2100 Register HexagonInstrInfo::createVR(MachineFunction *MF, MVT VT) const {
2093 MachineRegisterInfo &MRI = MF->getRegInfo(); 2101 MachineRegisterInfo &MRI = MF->getRegInfo();
2094 const TargetRegisterClass *TRC; 2102 const TargetRegisterClass *TRC;
2095 if (VT == MVT::i1) { 2103 if (VT == MVT::i1) {
2096 TRC = &Hexagon::PredRegsRegClass; 2104 TRC = &Hexagon::PredRegsRegClass;
2097 } else if (VT == MVT::i32 || VT == MVT::f32) { 2105 } else if (VT == MVT::i32 || VT == MVT::f32) {
2168 2176
2169 // If the extendable operand is not 'Immediate' type, the instruction should 2177 // If the extendable operand is not 'Immediate' type, the instruction should
2170 // have 'isExtended' flag set. 2178 // have 'isExtended' flag set.
2171 assert(MO.isImm() && "Extendable operand must be Immediate type"); 2179 assert(MO.isImm() && "Extendable operand must be Immediate type");
2172 2180
2173 int MinValue = getMinValue(MI); 2181 int64_t Value = MO.getImm();
2174 int MaxValue = getMaxValue(MI); 2182 if ((F >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask) {
2175 int ImmValue = MO.getImm(); 2183 int32_t SValue = Value;
2176 2184 int32_t MinValue = getMinValue(MI);
2177 return (ImmValue < MinValue || ImmValue > MaxValue); 2185 int32_t MaxValue = getMaxValue(MI);
2186 return SValue < MinValue || SValue > MaxValue;
2187 }
2188 uint32_t UValue = Value;
2189 uint32_t MinValue = getMinValue(MI);
2190 uint32_t MaxValue = getMaxValue(MI);
2191 return UValue < MinValue || UValue > MaxValue;
2178 } 2192 }
2179 2193
2180 bool HexagonInstrInfo::isDeallocRet(const MachineInstr &MI) const { 2194 bool HexagonInstrInfo::isDeallocRet(const MachineInstr &MI) const {
2181 switch (MI.getOpcode()) { 2195 switch (MI.getOpcode()) {
2182 case Hexagon::L4_return: 2196 case Hexagon::L4_return:
2196 const MachineInstr &ConsMI) const { 2210 const MachineInstr &ConsMI) const {
2197 if (!ProdMI.getDesc().getNumDefs()) 2211 if (!ProdMI.getDesc().getNumDefs())
2198 return false; 2212 return false;
2199 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); 2213 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
2200 2214
2201 SmallVector<unsigned, 4> DefsA; 2215 SmallVector<Register, 4> DefsA;
2202 SmallVector<unsigned, 4> DefsB; 2216 SmallVector<Register, 4> DefsB;
2203 SmallVector<unsigned, 8> UsesA; 2217 SmallVector<Register, 8> UsesA;
2204 SmallVector<unsigned, 8> UsesB; 2218 SmallVector<Register, 8> UsesB;
2205 2219
2206 parseOperands(ProdMI, DefsA, UsesA); 2220 parseOperands(ProdMI, DefsA, UsesA);
2207 parseOperands(ConsMI, DefsB, UsesB); 2221 parseOperands(ConsMI, DefsB, UsesB);
2208 2222
2209 for (auto &RegA : DefsA) 2223 for (auto &RegA : DefsA)
2210 for (auto &RegB : UsesB) { 2224 for (auto &RegB : UsesB) {
2211 // True data dependency. 2225 // True data dependency.
2212 if (RegA == RegB) 2226 if (RegA == RegB)
2213 return true; 2227 return true;
2214 2228
2215 if (Register::isPhysicalRegister(RegA)) 2229 if (RegA.isPhysical() && llvm::is_contained(HRI.subregs(RegA), RegB))
2216 for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs) 2230 return true;
2217 if (RegB == *SubRegs) 2231
2218 return true; 2232 if (RegB.isPhysical() && llvm::is_contained(HRI.subregs(RegB), RegA))
2219 2233 return true;
2220 if (Register::isPhysicalRegister(RegB))
2221 for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs)
2222 if (RegA == *SubRegs)
2223 return true;
2224 } 2234 }
2225 2235
2226 return false; 2236 return false;
2227 } 2237 }
2228 2238
3186 } 3196 }
3187 return false; 3197 return false;
3188 } 3198 }
3189 3199
3190 bool HexagonInstrInfo::predCanBeUsedAsDotNew(const MachineInstr &MI, 3200 bool HexagonInstrInfo::predCanBeUsedAsDotNew(const MachineInstr &MI,
3191 unsigned PredReg) const { 3201 Register PredReg) const {
3192 for (const MachineOperand &MO : MI.operands()) { 3202 for (const MachineOperand &MO : MI.operands()) {
3193 // Predicate register must be explicitly defined. 3203 // Predicate register must be explicitly defined.
3194 if (MO.isRegMask() && MO.clobbersPhysReg(PredReg)) 3204 if (MO.isRegMask() && MO.clobbersPhysReg(PredReg))
3195 return false; 3205 return false;
3196 if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg)) 3206 if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
3383 3393
3384 // See if instruction could potentially be a duplex candidate. 3394 // See if instruction could potentially be a duplex candidate.
3385 // If so, return its group. Zero otherwise. 3395 // If so, return its group. Zero otherwise.
3386 HexagonII::CompoundGroup HexagonInstrInfo::getCompoundCandidateGroup( 3396 HexagonII::CompoundGroup HexagonInstrInfo::getCompoundCandidateGroup(
3387 const MachineInstr &MI) const { 3397 const MachineInstr &MI) const {
3388 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; 3398 Register DstReg, SrcReg, Src1Reg, Src2Reg;
3389 3399
3390 switch (MI.getOpcode()) { 3400 switch (MI.getOpcode()) {
3391 default: 3401 default:
3392 return HexagonII::HCG_None; 3402 return HexagonII::HCG_None;
3393 // 3403 //
3835 if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form 3845 if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
3836 NewOp = Hexagon::getPredOldOpcode(NewOp); 3846 NewOp = Hexagon::getPredOldOpcode(NewOp);
3837 // All Hexagon architectures have prediction bits on dot-new branches, 3847 // All Hexagon architectures have prediction bits on dot-new branches,
3838 // but only Hexagon V60+ has prediction bits on dot-old ones. Make sure 3848 // but only Hexagon V60+ has prediction bits on dot-old ones. Make sure
3839 // to pick the right opcode when converting back to dot-old. 3849 // to pick the right opcode when converting back to dot-old.
3840 if (!Subtarget.getFeatureBits()[Hexagon::ArchV60]) { 3850 if (!Subtarget.hasFeature(Hexagon::ArchV60)) {
3841 switch (NewOp) { 3851 switch (NewOp) {
3842 case Hexagon::J2_jumptpt: 3852 case Hexagon::J2_jumptpt:
3843 NewOp = Hexagon::J2_jumpt; 3853 NewOp = Hexagon::J2_jumpt;
3844 break; 3854 break;
3845 case Hexagon::J2_jumpfpt: 3855 case Hexagon::J2_jumpfpt:
3881 3891
3882 // See if instruction could potentially be a duplex candidate. 3892 // See if instruction could potentially be a duplex candidate.
3883 // If so, return its group. Zero otherwise. 3893 // If so, return its group. Zero otherwise.
3884 HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( 3894 HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup(
3885 const MachineInstr &MI) const { 3895 const MachineInstr &MI) const {
3886 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; 3896 Register DstReg, SrcReg, Src1Reg, Src2Reg;
3887 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); 3897 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
3888 3898
3889 switch (MI.getOpcode()) { 3899 switch (MI.getOpcode()) {
3890 default: 3900 default:
3891 return HexagonII::HSIG_None; 3901 return HexagonII::HSIG_None;
4293 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); 4303 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4294 4304
4295 // Get DefIdx and UseIdx for super registers. 4305 // Get DefIdx and UseIdx for super registers.
4296 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); 4306 const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
4297 4307
4298 if (DefMO.isReg() && Register::isPhysicalRegister(DefMO.getReg())) { 4308 if (DefMO.isReg() && DefMO.getReg().isPhysical()) {
4299 if (DefMO.isImplicit()) { 4309 if (DefMO.isImplicit()) {
4300 for (MCSuperRegIterator SR(DefMO.getReg(), &HRI); SR.isValid(); ++SR) { 4310 for (MCPhysReg SR : HRI.superregs(DefMO.getReg())) {
4301 int Idx = DefMI.findRegisterDefOperandIdx(*SR, false, false, &HRI); 4311 int Idx = DefMI.findRegisterDefOperandIdx(SR, false, false, &HRI);
4302 if (Idx != -1) { 4312 if (Idx != -1) {
4303 DefIdx = Idx; 4313 DefIdx = Idx;
4304 break; 4314 break;
4305 } 4315 }
4306 } 4316 }
4307 } 4317 }
4308 4318
4309 const MachineOperand &UseMO = UseMI.getOperand(UseIdx); 4319 const MachineOperand &UseMO = UseMI.getOperand(UseIdx);
4310 if (UseMO.isImplicit()) { 4320 if (UseMO.isImplicit()) {
4311 for (MCSuperRegIterator SR(UseMO.getReg(), &HRI); SR.isValid(); ++SR) { 4321 for (MCPhysReg SR : HRI.superregs(UseMO.getReg())) {
4312 int Idx = UseMI.findRegisterUseOperandIdx(*SR, false, &HRI); 4322 int Idx = UseMI.findRegisterUseOperandIdx(SR, false, &HRI);
4313 if (Idx != -1) { 4323 if (Idx != -1) {
4314 UseIdx = Idx; 4324 UseIdx = Idx;
4315 break; 4325 break;
4316 } 4326 }
4317 } 4327 }
4508 } 4518 }
4509 return -1; 4519 return -1;
4510 } 4520 }
4511 4521
4512 bool HexagonInstrInfo::getPredReg(ArrayRef<MachineOperand> Cond, 4522 bool HexagonInstrInfo::getPredReg(ArrayRef<MachineOperand> Cond,
4513 unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const { 4523 Register &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const {
4514 if (Cond.empty()) 4524 if (Cond.empty())
4515 return false; 4525 return false;
4516 assert(Cond.size() == 2); 4526 assert(Cond.size() == 2);
4517 if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) { 4527 if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) {
4518 LLVM_DEBUG(dbgs() << "No predregs for new-value jumps/endloop"); 4528 LLVM_DEBUG(dbgs() << "No predregs for new-value jumps/endloop");