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comparison llvm/test/CodeGen/AMDGPU/llvm.amdgcn.queue.ptr.ll @ 252:1f2b6ac9f198 llvm-original

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LLVM16-1
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Fri, 18 Aug 2023 09:04:13 +0900
parents 79ff65ed7e25
children
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237:c80f45b162ad 252:1f2b6ac9f198
1 ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s 1 ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
2 ; RUN: not llc -mtriple=amdgcn-unknown-unknown -mcpu=kaveri -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR %s 2 ; RUN: not llc -mtriple=amdgcn-unknown-unknown -mcpu=kaveri -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR %s
3 3
4 ; ERROR: in function test{{.*}}: unsupported hsa intrinsic without hsa target 4 ; ERROR: in function test{{.*}}: unsupported hsa intrinsic without hsa target
5 5
6 ; GCN-LABEL: {{^}}test: 6 ; GCN-LABEL: {{^}}test:
7 ; GCN: enable_sgpr_queue_ptr = 1 7 ; GCN: enable_sgpr_queue_ptr = 1
8 ; GCN: s_load_dword s{{[0-9]+}}, s[4:5], 0x0 8 ; GCN: s_load_dword s{{[0-9]+}}, s[4:5], 0x0
9 define amdgpu_kernel void @test(i32 addrspace(1)* %out) { 9 define amdgpu_kernel void @test(ptr addrspace(1) %out) {
10 %queue_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0 10 %queue_ptr = call noalias ptr addrspace(4) @llvm.amdgcn.queue.ptr() #0
11 %header_ptr = bitcast i8 addrspace(4)* %queue_ptr to i32 addrspace(4)* 11 %value = load i32, ptr addrspace(4) %queue_ptr
12 %value = load i32, i32 addrspace(4)* %header_ptr 12 store i32 %value, ptr addrspace(1) %out
13 store i32 %value, i32 addrspace(1)* %out
14 ret void 13 ret void
15 } 14 }
16 15
17 declare noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0 16 declare noalias ptr addrspace(4) @llvm.amdgcn.queue.ptr() #0
18 17
19 attributes #0 = { nounwind readnone } 18 attributes #0 = { nounwind readnone }
19
20 !llvm.module.flags = !{!0}
21 !0 = !{i32 1, !"amdgpu_code_object_version", i32 200}