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comparison clang/test/CodeGen/arm-neon-vld.c @ 207:2e18cbf3894f

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LLVM12
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Tue, 08 Jun 2021 06:07:14 +0900
parents 0572611fdcc8
children c4bab56944e8
comparison
equal deleted inserted replaced
173:0572611fdcc8 207:2e18cbf3894f
7 7
8 #include <arm_neon.h> 8 #include <arm_neon.h>
9 9
10 // CHECK-LABEL: @test_vld1_f16_x2( 10 // CHECK-LABEL: @test_vld1_f16_x2(
11 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float16x4x2_t, align 8 11 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float16x4x2_t, align 8
12 // CHECK-A32: %struct.float16x4x2_t* noalias sret align 8 [[RETVAL:%.*]], 12 // CHECK-A32: %struct.float16x4x2_t* noalias sret(%struct.float16x4x2_t) align 8 [[RETVAL:%.*]],
13 // CHECK: [[__RET:%.*]] = alloca %struct.float16x4x2_t, align 8 13 // CHECK: [[__RET:%.*]] = alloca %struct.float16x4x2_t, align 8
14 // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x4x2_t* [[__RET]] to i8* 14 // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x4x2_t* [[__RET]] to i8*
15 // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8* 15 // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*
16 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to [[HALF:(half|i16)]]* 16 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to [[HALF:(half|i16)]]*
17 // CHECK: [[VLD1XN:%.*]] = call { <4 x [[HALF]]>, <4 x [[HALF]]> } @llvm.{{aarch64.neon.ld1x2.v4f16.p0f16|arm.neon.vld1x2.v4i16.p0i16}}([[HALF]]* [[TMP2]]) 17 // CHECK: [[VLD1XN:%.*]] = call { <4 x [[HALF]]>, <4 x [[HALF]]> } @llvm.{{aarch64.neon.ld1x2.v4f16.p0f16|arm.neon.vld1x2.v4i16.p0i16}}([[HALF]]* [[TMP2]])
27 return vld1_f16_x2(a); 27 return vld1_f16_x2(a);
28 } 28 }
29 29
30 // CHECK-LABEL: @test_vld1_f16_x3( 30 // CHECK-LABEL: @test_vld1_f16_x3(
31 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float16x4x3_t, align 8 31 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float16x4x3_t, align 8
32 // CHECK-A32: %struct.float16x4x3_t* noalias sret align 8 [[RETVAL:%.*]], 32 // CHECK-A32: %struct.float16x4x3_t* noalias sret(%struct.float16x4x3_t) align 8 [[RETVAL:%.*]],
33 // CHECK: [[__RET:%.*]] = alloca %struct.float16x4x3_t, align 8 33 // CHECK: [[__RET:%.*]] = alloca %struct.float16x4x3_t, align 8
34 // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x4x3_t* [[__RET]] to i8* 34 // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x4x3_t* [[__RET]] to i8*
35 // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8* 35 // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*
36 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to [[HALF]]* 36 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to [[HALF]]*
37 // CHECK: [[VLD1XN:%.*]] = call { <4 x [[HALF]]>, <4 x [[HALF]]>, <4 x [[HALF]]> } @llvm.{{aarch64.neon.ld1x3.v4f16.p0f16|arm.neon.vld1x3.v4i16.p0i16}}([[HALF]]* [[TMP2]]) 37 // CHECK: [[VLD1XN:%.*]] = call { <4 x [[HALF]]>, <4 x [[HALF]]>, <4 x [[HALF]]> } @llvm.{{aarch64.neon.ld1x3.v4f16.p0f16|arm.neon.vld1x3.v4i16.p0i16}}([[HALF]]* [[TMP2]])
47 return vld1_f16_x3(a); 47 return vld1_f16_x3(a);
48 } 48 }
49 49
50 // CHECK-LABEL: @test_vld1_f16_x4( 50 // CHECK-LABEL: @test_vld1_f16_x4(
51 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float16x4x4_t, align 8 51 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float16x4x4_t, align 8
52 // CHECK-A32: %struct.float16x4x4_t* noalias sret align 8 [[RETVAL:%.*]], 52 // CHECK-A32: %struct.float16x4x4_t* noalias sret(%struct.float16x4x4_t) align 8 [[RETVAL:%.*]],
53 // CHECK: [[__RET:%.*]] = alloca %struct.float16x4x4_t, align 8 53 // CHECK: [[__RET:%.*]] = alloca %struct.float16x4x4_t, align 8
54 // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x4x4_t* [[__RET]] to i8* 54 // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x4x4_t* [[__RET]] to i8*
55 // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8* 55 // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*
56 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to [[HALF]]* 56 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to [[HALF]]*
57 // CHECK: [[VLD1XN:%.*]] = call { <4 x [[HALF]]>, <4 x [[HALF]]>, <4 x [[HALF]]>, <4 x [[HALF]]> } @llvm.{{aarch64.neon.ld1x4.v4f16.p0f16|arm.neon.vld1x4.v4i16.p0i16}}([[HALF]]* [[TMP2]]) 57 // CHECK: [[VLD1XN:%.*]] = call { <4 x [[HALF]]>, <4 x [[HALF]]>, <4 x [[HALF]]>, <4 x [[HALF]]> } @llvm.{{aarch64.neon.ld1x4.v4f16.p0f16|arm.neon.vld1x4.v4i16.p0i16}}([[HALF]]* [[TMP2]])
67 return vld1_f16_x4(a); 67 return vld1_f16_x4(a);
68 } 68 }
69 69
70 // CHECK-LABEL: @test_vld1_f32_x2( 70 // CHECK-LABEL: @test_vld1_f32_x2(
71 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float32x2x2_t, align 8 71 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float32x2x2_t, align 8
72 // CHECK-A32: %struct.float32x2x2_t* noalias sret align 8 [[RETVAL:%.*]], 72 // CHECK-A32: %struct.float32x2x2_t* noalias sret(%struct.float32x2x2_t) align 8 [[RETVAL:%.*]],
73 // CHECK: [[__RET:%.*]] = alloca %struct.float32x2x2_t, align 8 73 // CHECK: [[__RET:%.*]] = alloca %struct.float32x2x2_t, align 8
74 // CHECK: [[TMP0:%.*]] = bitcast %struct.float32x2x2_t* [[__RET]] to i8* 74 // CHECK: [[TMP0:%.*]] = bitcast %struct.float32x2x2_t* [[__RET]] to i8*
75 // CHECK: [[TMP1:%.*]] = bitcast float* %a to i8* 75 // CHECK: [[TMP1:%.*]] = bitcast float* %a to i8*
76 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to float* 76 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to float*
77 // CHECK: [[VLD1XN:%.*]] = call { <2 x float>, <2 x float> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v2f32.p0f32(float* [[TMP2]]) 77 // CHECK: [[VLD1XN:%.*]] = call { <2 x float>, <2 x float> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v2f32.p0f32(float* [[TMP2]])
87 return vld1_f32_x2(a); 87 return vld1_f32_x2(a);
88 } 88 }
89 89
90 // CHECK-LABEL: @test_vld1_f32_x3( 90 // CHECK-LABEL: @test_vld1_f32_x3(
91 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float32x2x3_t, align 8 91 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float32x2x3_t, align 8
92 // CHECK-A32: %struct.float32x2x3_t* noalias sret align 8 [[RETVAL:%.*]], 92 // CHECK-A32: %struct.float32x2x3_t* noalias sret(%struct.float32x2x3_t) align 8 [[RETVAL:%.*]],
93 // CHECK: [[__RET:%.*]] = alloca %struct.float32x2x3_t, align 8 93 // CHECK: [[__RET:%.*]] = alloca %struct.float32x2x3_t, align 8
94 // CHECK: [[TMP0:%.*]] = bitcast %struct.float32x2x3_t* [[__RET]] to i8* 94 // CHECK: [[TMP0:%.*]] = bitcast %struct.float32x2x3_t* [[__RET]] to i8*
95 // CHECK: [[TMP1:%.*]] = bitcast float* %a to i8* 95 // CHECK: [[TMP1:%.*]] = bitcast float* %a to i8*
96 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to float* 96 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to float*
97 // CHECK: [[VLD1XN:%.*]] = call { <2 x float>, <2 x float>, <2 x float> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v2f32.p0f32(float* [[TMP2]]) 97 // CHECK: [[VLD1XN:%.*]] = call { <2 x float>, <2 x float>, <2 x float> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v2f32.p0f32(float* [[TMP2]])
106 return vld1_f32_x3(a); 106 return vld1_f32_x3(a);
107 } 107 }
108 108
109 // CHECK-LABEL: @test_vld1_f32_x4( 109 // CHECK-LABEL: @test_vld1_f32_x4(
110 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float32x2x4_t, align 8 110 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float32x2x4_t, align 8
111 // CHECK-A32: %struct.float32x2x4_t* noalias sret align 8 [[RETVAL:%.*]], 111 // CHECK-A32: %struct.float32x2x4_t* noalias sret(%struct.float32x2x4_t) align 8 [[RETVAL:%.*]],
112 // CHECK: [[__RET:%.*]] = alloca %struct.float32x2x4_t, align 8 112 // CHECK: [[__RET:%.*]] = alloca %struct.float32x2x4_t, align 8
113 // CHECK: [[TMP0:%.*]] = bitcast %struct.float32x2x4_t* [[__RET]] to i8* 113 // CHECK: [[TMP0:%.*]] = bitcast %struct.float32x2x4_t* [[__RET]] to i8*
114 // CHECK: [[TMP1:%.*]] = bitcast float* %a to i8* 114 // CHECK: [[TMP1:%.*]] = bitcast float* %a to i8*
115 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to float* 115 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to float*
116 // CHECK: [[VLD1XN:%.*]] = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v2f32.p0f32(float* [[TMP2]]) 116 // CHECK: [[VLD1XN:%.*]] = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v2f32.p0f32(float* [[TMP2]])
126 return vld1_f32_x4(a); 126 return vld1_f32_x4(a);
127 } 127 }
128 128
129 // CHECK-LABEL: @test_vld1_p16_x2( 129 // CHECK-LABEL: @test_vld1_p16_x2(
130 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly16x4x2_t, align 8 130 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly16x4x2_t, align 8
131 // CHECK-A32: %struct.poly16x4x2_t* noalias sret align 8 [[RETVAL:%.*]], 131 // CHECK-A32: %struct.poly16x4x2_t* noalias sret(%struct.poly16x4x2_t) align 8 [[RETVAL:%.*]],
132 // CHECK: [[__RET:%.*]] = alloca %struct.poly16x4x2_t, align 8 132 // CHECK: [[__RET:%.*]] = alloca %struct.poly16x4x2_t, align 8
133 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly16x4x2_t* [[__RET]] to i8* 133 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly16x4x2_t* [[__RET]] to i8*
134 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8* 134 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8*
135 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16* 135 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*
136 // CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v4i16.p0i16(i16* [[TMP2]]) 136 // CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v4i16.p0i16(i16* [[TMP2]])
146 return vld1_p16_x2(a); 146 return vld1_p16_x2(a);
147 } 147 }
148 148
149 // CHECK-LABEL: @test_vld1_p16_x3( 149 // CHECK-LABEL: @test_vld1_p16_x3(
150 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly16x4x3_t, align 8 150 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly16x4x3_t, align 8
151 // CHECK-A32: %struct.poly16x4x3_t* noalias sret align 8 [[RETVAL:%.*]], 151 // CHECK-A32: %struct.poly16x4x3_t* noalias sret(%struct.poly16x4x3_t) align 8 [[RETVAL:%.*]],
152 // CHECK: [[__RET:%.*]] = alloca %struct.poly16x4x3_t, align 8 152 // CHECK: [[__RET:%.*]] = alloca %struct.poly16x4x3_t, align 8
153 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly16x4x3_t* [[__RET]] to i8* 153 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly16x4x3_t* [[__RET]] to i8*
154 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8* 154 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8*
155 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16* 155 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*
156 // CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v4i16.p0i16(i16* [[TMP2]]) 156 // CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v4i16.p0i16(i16* [[TMP2]])
166 return vld1_p16_x3(a); 166 return vld1_p16_x3(a);
167 } 167 }
168 168
169 // CHECK-LABEL: @test_vld1_p16_x4( 169 // CHECK-LABEL: @test_vld1_p16_x4(
170 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly16x4x4_t, align 8 170 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly16x4x4_t, align 8
171 // CHECK-A32: %struct.poly16x4x4_t* noalias sret align 8 [[RETVAL:%.*]], 171 // CHECK-A32: %struct.poly16x4x4_t* noalias sret(%struct.poly16x4x4_t) align 8 [[RETVAL:%.*]],
172 // CHECK: [[__RET:%.*]] = alloca %struct.poly16x4x4_t, align 8 172 // CHECK: [[__RET:%.*]] = alloca %struct.poly16x4x4_t, align 8
173 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly16x4x4_t* [[__RET]] to i8* 173 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly16x4x4_t* [[__RET]] to i8*
174 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8* 174 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8*
175 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16* 175 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*
176 // CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v4i16.p0i16(i16* [[TMP2]]) 176 // CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v4i16.p0i16(i16* [[TMP2]])
186 return vld1_p16_x4(a); 186 return vld1_p16_x4(a);
187 } 187 }
188 188
189 // CHECK-LABEL: @test_vld1_p8_x2( 189 // CHECK-LABEL: @test_vld1_p8_x2(
190 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly8x8x2_t, align 8 190 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly8x8x2_t, align 8
191 // CHECK-A32: %struct.poly8x8x2_t* noalias sret align 8 [[RETVAL:%.*]], 191 // CHECK-A32: %struct.poly8x8x2_t* noalias sret(%struct.poly8x8x2_t) align 8 [[RETVAL:%.*]],
192 // CHECK: [[__RET:%.*]] = alloca %struct.poly8x8x2_t, align 8 192 // CHECK: [[__RET:%.*]] = alloca %struct.poly8x8x2_t, align 8
193 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly8x8x2_t* [[__RET]] to i8* 193 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly8x8x2_t* [[__RET]] to i8*
194 // CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v8i8.p0i8(i8* %a) 194 // CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v8i8.p0i8(i8* %a)
195 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <8 x i8>, <8 x i8> }* 195 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <8 x i8>, <8 x i8> }*
196 // CHECK: store { <8 x i8>, <8 x i8> } [[VLD1XN]], { <8 x i8>, <8 x i8> }* [[TMP1]] 196 // CHECK: store { <8 x i8>, <8 x i8> } [[VLD1XN]], { <8 x i8>, <8 x i8> }* [[TMP1]]
204 return vld1_p8_x2(a); 204 return vld1_p8_x2(a);
205 } 205 }
206 206
207 // CHECK-LABEL: @test_vld1_p8_x3( 207 // CHECK-LABEL: @test_vld1_p8_x3(
208 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly8x8x3_t, align 8 208 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly8x8x3_t, align 8
209 // CHECK-A32: %struct.poly8x8x3_t* noalias sret align 8 [[RETVAL:%.*]], 209 // CHECK-A32: %struct.poly8x8x3_t* noalias sret(%struct.poly8x8x3_t) align 8 [[RETVAL:%.*]],
210 // CHECK: [[__RET:%.*]] = alloca %struct.poly8x8x3_t, align 8 210 // CHECK: [[__RET:%.*]] = alloca %struct.poly8x8x3_t, align 8
211 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly8x8x3_t* [[__RET]] to i8* 211 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly8x8x3_t* [[__RET]] to i8*
212 // CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v8i8.p0i8(i8* %a) 212 // CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v8i8.p0i8(i8* %a)
213 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <8 x i8>, <8 x i8>, <8 x i8> }* 213 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <8 x i8>, <8 x i8>, <8 x i8> }*
214 // CHECK: store { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], { <8 x i8>, <8 x i8>, <8 x i8> }* [[TMP1]] 214 // CHECK: store { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], { <8 x i8>, <8 x i8>, <8 x i8> }* [[TMP1]]
222 return vld1_p8_x3(a); 222 return vld1_p8_x3(a);
223 } 223 }
224 224
225 // CHECK-LABEL: @test_vld1_p8_x4( 225 // CHECK-LABEL: @test_vld1_p8_x4(
226 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly8x8x4_t, align 8 226 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly8x8x4_t, align 8
227 // CHECK-A32: %struct.poly8x8x4_t* noalias sret align 8 [[RETVAL:%.*]], 227 // CHECK-A32: %struct.poly8x8x4_t* noalias sret(%struct.poly8x8x4_t) align 8 [[RETVAL:%.*]],
228 // CHECK: [[__RET:%.*]] = alloca %struct.poly8x8x4_t, align 8 228 // CHECK: [[__RET:%.*]] = alloca %struct.poly8x8x4_t, align 8
229 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly8x8x4_t* [[__RET]] to i8* 229 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly8x8x4_t* [[__RET]] to i8*
230 // CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v8i8.p0i8(i8* %a) 230 // CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v8i8.p0i8(i8* %a)
231 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }* 231 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }*
232 // CHECK: store { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }* [[TMP1]] 232 // CHECK: store { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }* [[TMP1]]
240 return vld1_p8_x4(a); 240 return vld1_p8_x4(a);
241 } 241 }
242 242
243 // CHECK-LABEL: @test_vld1_s16_x2( 243 // CHECK-LABEL: @test_vld1_s16_x2(
244 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int16x4x2_t, align 8 244 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int16x4x2_t, align 8
245 // CHECK-A32: %struct.int16x4x2_t* noalias sret align 8 [[RETVAL:%.*]], 245 // CHECK-A32: %struct.int16x4x2_t* noalias sret(%struct.int16x4x2_t) align 8 [[RETVAL:%.*]],
246 // CHECK: [[__RET:%.*]] = alloca %struct.int16x4x2_t, align 8 246 // CHECK: [[__RET:%.*]] = alloca %struct.int16x4x2_t, align 8
247 // CHECK: [[TMP0:%.*]] = bitcast %struct.int16x4x2_t* [[__RET]] to i8* 247 // CHECK: [[TMP0:%.*]] = bitcast %struct.int16x4x2_t* [[__RET]] to i8*
248 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8* 248 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8*
249 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16* 249 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*
250 // CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v4i16.p0i16(i16* [[TMP2]]) 250 // CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v4i16.p0i16(i16* [[TMP2]])
260 return vld1_s16_x2(a); 260 return vld1_s16_x2(a);
261 } 261 }
262 262
263 // CHECK-LABEL: @test_vld1_s16_x3( 263 // CHECK-LABEL: @test_vld1_s16_x3(
264 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int16x4x3_t, align 8 264 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int16x4x3_t, align 8
265 // CHECK-A32: %struct.int16x4x3_t* noalias sret align 8 [[RETVAL:%.*]], 265 // CHECK-A32: %struct.int16x4x3_t* noalias sret(%struct.int16x4x3_t) align 8 [[RETVAL:%.*]],
266 // CHECK: [[__RET:%.*]] = alloca %struct.int16x4x3_t, align 8 266 // CHECK: [[__RET:%.*]] = alloca %struct.int16x4x3_t, align 8
267 // CHECK: [[TMP0:%.*]] = bitcast %struct.int16x4x3_t* [[__RET]] to i8* 267 // CHECK: [[TMP0:%.*]] = bitcast %struct.int16x4x3_t* [[__RET]] to i8*
268 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8* 268 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8*
269 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16* 269 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*
270 // CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v4i16.p0i16(i16* [[TMP2]]) 270 // CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v4i16.p0i16(i16* [[TMP2]])
280 return vld1_s16_x3(a); 280 return vld1_s16_x3(a);
281 } 281 }
282 282
283 // CHECK-LABEL: @test_vld1_s16_x4( 283 // CHECK-LABEL: @test_vld1_s16_x4(
284 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int16x4x4_t, align 8 284 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int16x4x4_t, align 8
285 // CHECK-A32: %struct.int16x4x4_t* noalias sret align 8 [[RETVAL:%.*]], 285 // CHECK-A32: %struct.int16x4x4_t* noalias sret(%struct.int16x4x4_t) align 8 [[RETVAL:%.*]],
286 // CHECK: [[__RET:%.*]] = alloca %struct.int16x4x4_t, align 8 286 // CHECK: [[__RET:%.*]] = alloca %struct.int16x4x4_t, align 8
287 // CHECK: [[TMP0:%.*]] = bitcast %struct.int16x4x4_t* [[__RET]] to i8* 287 // CHECK: [[TMP0:%.*]] = bitcast %struct.int16x4x4_t* [[__RET]] to i8*
288 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8* 288 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8*
289 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16* 289 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*
290 // CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v4i16.p0i16(i16* [[TMP2]]) 290 // CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v4i16.p0i16(i16* [[TMP2]])
300 return vld1_s16_x4(a); 300 return vld1_s16_x4(a);
301 } 301 }
302 302
303 // CHECK-LABEL: @test_vld1_s32_x2( 303 // CHECK-LABEL: @test_vld1_s32_x2(
304 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int32x2x2_t, align 8 304 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int32x2x2_t, align 8
305 // CHECK-A32: %struct.int32x2x2_t* noalias sret align 8 [[RETVAL:%.*]], 305 // CHECK-A32: %struct.int32x2x2_t* noalias sret(%struct.int32x2x2_t) align 8 [[RETVAL:%.*]],
306 // CHECK: [[__RET:%.*]] = alloca %struct.int32x2x2_t, align 8 306 // CHECK: [[__RET:%.*]] = alloca %struct.int32x2x2_t, align 8
307 // CHECK: [[TMP0:%.*]] = bitcast %struct.int32x2x2_t* [[__RET]] to i8* 307 // CHECK: [[TMP0:%.*]] = bitcast %struct.int32x2x2_t* [[__RET]] to i8*
308 // CHECK: [[TMP1:%.*]] = bitcast i32* %a to i8* 308 // CHECK: [[TMP1:%.*]] = bitcast i32* %a to i8*
309 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32* 309 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32*
310 // CHECK: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v2i32.p0i32(i32* [[TMP2]]) 310 // CHECK: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v2i32.p0i32(i32* [[TMP2]])
320 return vld1_s32_x2(a); 320 return vld1_s32_x2(a);
321 } 321 }
322 322
323 // CHECK-LABEL: @test_vld1_s32_x3( 323 // CHECK-LABEL: @test_vld1_s32_x3(
324 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int32x2x3_t, align 8 324 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int32x2x3_t, align 8
325 // CHECK-A32: %struct.int32x2x3_t* noalias sret align 8 [[RETVAL:%.*]], 325 // CHECK-A32: %struct.int32x2x3_t* noalias sret(%struct.int32x2x3_t) align 8 [[RETVAL:%.*]],
326 // CHECK: [[__RET:%.*]] = alloca %struct.int32x2x3_t, align 8 326 // CHECK: [[__RET:%.*]] = alloca %struct.int32x2x3_t, align 8
327 // CHECK: [[TMP0:%.*]] = bitcast %struct.int32x2x3_t* [[__RET]] to i8* 327 // CHECK: [[TMP0:%.*]] = bitcast %struct.int32x2x3_t* [[__RET]] to i8*
328 // CHECK: [[TMP1:%.*]] = bitcast i32* %a to i8* 328 // CHECK: [[TMP1:%.*]] = bitcast i32* %a to i8*
329 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32* 329 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32*
330 // CHECK: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v2i32.p0i32(i32* [[TMP2]]) 330 // CHECK: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v2i32.p0i32(i32* [[TMP2]])
340 return vld1_s32_x3(a); 340 return vld1_s32_x3(a);
341 } 341 }
342 342
343 // CHECK-LABEL: @test_vld1_s32_x4( 343 // CHECK-LABEL: @test_vld1_s32_x4(
344 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int32x2x4_t, align 8 344 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int32x2x4_t, align 8
345 // CHECK-A32: %struct.int32x2x4_t* noalias sret align 8 [[RETVAL:%.*]], 345 // CHECK-A32: %struct.int32x2x4_t* noalias sret(%struct.int32x2x4_t) align 8 [[RETVAL:%.*]],
346 // CHECK: [[__RET:%.*]] = alloca %struct.int32x2x4_t, align 8 346 // CHECK: [[__RET:%.*]] = alloca %struct.int32x2x4_t, align 8
347 // CHECK: [[TMP0:%.*]] = bitcast %struct.int32x2x4_t* [[__RET]] to i8* 347 // CHECK: [[TMP0:%.*]] = bitcast %struct.int32x2x4_t* [[__RET]] to i8*
348 // CHECK: [[TMP1:%.*]] = bitcast i32* %a to i8* 348 // CHECK: [[TMP1:%.*]] = bitcast i32* %a to i8*
349 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32* 349 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32*
350 // CHECK: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v2i32.p0i32(i32* [[TMP2]]) 350 // CHECK: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v2i32.p0i32(i32* [[TMP2]])
360 return vld1_s32_x4(a); 360 return vld1_s32_x4(a);
361 } 361 }
362 362
363 // CHECK-LABEL: @test_vld1_s64_x2( 363 // CHECK-LABEL: @test_vld1_s64_x2(
364 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int64x1x2_t, align 8 364 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int64x1x2_t, align 8
365 // CHECK-A32: %struct.int64x1x2_t* noalias sret align 8 [[RETVAL:%.*]], 365 // CHECK-A32: %struct.int64x1x2_t* noalias sret(%struct.int64x1x2_t) align 8 [[RETVAL:%.*]],
366 // CHECK: [[__RET:%.*]] = alloca %struct.int64x1x2_t, align 8 366 // CHECK: [[__RET:%.*]] = alloca %struct.int64x1x2_t, align 8
367 // CHECK: [[TMP0:%.*]] = bitcast %struct.int64x1x2_t* [[__RET]] to i8* 367 // CHECK: [[TMP0:%.*]] = bitcast %struct.int64x1x2_t* [[__RET]] to i8*
368 // CHECK: [[TMP1:%.*]] = bitcast i64* %a to i8* 368 // CHECK: [[TMP1:%.*]] = bitcast i64* %a to i8*
369 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i64* 369 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i64*
370 // CHECK: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v1i64.p0i64(i64* [[TMP2]]) 370 // CHECK: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v1i64.p0i64(i64* [[TMP2]])
380 return vld1_s64_x2(a); 380 return vld1_s64_x2(a);
381 } 381 }
382 382
383 // CHECK-LABEL: @test_vld1_s64_x3( 383 // CHECK-LABEL: @test_vld1_s64_x3(
384 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int64x1x3_t, align 8 384 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int64x1x3_t, align 8
385 // CHECK-A32: %struct.int64x1x3_t* noalias sret align 8 [[RETVAL:%.*]], 385 // CHECK-A32: %struct.int64x1x3_t* noalias sret(%struct.int64x1x3_t) align 8 [[RETVAL:%.*]],
386 // CHECK: [[__RET:%.*]] = alloca %struct.int64x1x3_t, align 8 386 // CHECK: [[__RET:%.*]] = alloca %struct.int64x1x3_t, align 8
387 // CHECK: [[TMP0:%.*]] = bitcast %struct.int64x1x3_t* [[__RET]] to i8* 387 // CHECK: [[TMP0:%.*]] = bitcast %struct.int64x1x3_t* [[__RET]] to i8*
388 // CHECK: [[TMP1:%.*]] = bitcast i64* %a to i8* 388 // CHECK: [[TMP1:%.*]] = bitcast i64* %a to i8*
389 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i64* 389 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i64*
390 // CHECK: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v1i64.p0i64(i64* [[TMP2]]) 390 // CHECK: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v1i64.p0i64(i64* [[TMP2]])
400 return vld1_s64_x3(a); 400 return vld1_s64_x3(a);
401 } 401 }
402 402
403 // CHECK-LABEL: @test_vld1_s64_x4( 403 // CHECK-LABEL: @test_vld1_s64_x4(
404 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int64x1x4_t, align 8 404 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int64x1x4_t, align 8
405 // CHECK-A32: %struct.int64x1x4_t* noalias sret align 8 [[RETVAL:%.*]], 405 // CHECK-A32: %struct.int64x1x4_t* noalias sret(%struct.int64x1x4_t) align 8 [[RETVAL:%.*]],
406 // CHECK: [[__RET:%.*]] = alloca %struct.int64x1x4_t, align 8 406 // CHECK: [[__RET:%.*]] = alloca %struct.int64x1x4_t, align 8
407 // CHECK: [[TMP0:%.*]] = bitcast %struct.int64x1x4_t* [[__RET]] to i8* 407 // CHECK: [[TMP0:%.*]] = bitcast %struct.int64x1x4_t* [[__RET]] to i8*
408 // CHECK: [[TMP1:%.*]] = bitcast i64* %a to i8* 408 // CHECK: [[TMP1:%.*]] = bitcast i64* %a to i8*
409 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i64* 409 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i64*
410 // CHECK: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v1i64.p0i64(i64* [[TMP2]]) 410 // CHECK: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v1i64.p0i64(i64* [[TMP2]])
420 return vld1_s64_x4(a); 420 return vld1_s64_x4(a);
421 } 421 }
422 422
423 // CHECK-LABEL: @test_vld1_s8_x2( 423 // CHECK-LABEL: @test_vld1_s8_x2(
424 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int8x8x2_t, align 8 424 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int8x8x2_t, align 8
425 // CHECK-A32: %struct.int8x8x2_t* noalias sret align 8 [[RETVAL:%.*]], 425 // CHECK-A32: %struct.int8x8x2_t* noalias sret(%struct.int8x8x2_t) align 8 [[RETVAL:%.*]],
426 // CHECK: [[__RET:%.*]] = alloca %struct.int8x8x2_t, align 8 426 // CHECK: [[__RET:%.*]] = alloca %struct.int8x8x2_t, align 8
427 // CHECK: [[TMP0:%.*]] = bitcast %struct.int8x8x2_t* [[__RET]] to i8* 427 // CHECK: [[TMP0:%.*]] = bitcast %struct.int8x8x2_t* [[__RET]] to i8*
428 // CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v8i8.p0i8(i8* %a) 428 // CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v8i8.p0i8(i8* %a)
429 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <8 x i8>, <8 x i8> }* 429 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <8 x i8>, <8 x i8> }*
430 // CHECK: store { <8 x i8>, <8 x i8> } [[VLD1XN]], { <8 x i8>, <8 x i8> }* [[TMP1]] 430 // CHECK: store { <8 x i8>, <8 x i8> } [[VLD1XN]], { <8 x i8>, <8 x i8> }* [[TMP1]]
438 return vld1_s8_x2(a); 438 return vld1_s8_x2(a);
439 } 439 }
440 440
441 // CHECK-LABEL: @test_vld1_s8_x3( 441 // CHECK-LABEL: @test_vld1_s8_x3(
442 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int8x8x3_t, align 8 442 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int8x8x3_t, align 8
443 // CHECK-A32: %struct.int8x8x3_t* noalias sret align 8 [[RETVAL:%.*]], 443 // CHECK-A32: %struct.int8x8x3_t* noalias sret(%struct.int8x8x3_t) align 8 [[RETVAL:%.*]],
444 // CHECK: [[__RET:%.*]] = alloca %struct.int8x8x3_t, align 8 444 // CHECK: [[__RET:%.*]] = alloca %struct.int8x8x3_t, align 8
445 // CHECK: [[TMP0:%.*]] = bitcast %struct.int8x8x3_t* [[__RET]] to i8* 445 // CHECK: [[TMP0:%.*]] = bitcast %struct.int8x8x3_t* [[__RET]] to i8*
446 // CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v8i8.p0i8(i8* %a) 446 // CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v8i8.p0i8(i8* %a)
447 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <8 x i8>, <8 x i8>, <8 x i8> }* 447 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <8 x i8>, <8 x i8>, <8 x i8> }*
448 // CHECK: store { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], { <8 x i8>, <8 x i8>, <8 x i8> }* [[TMP1]] 448 // CHECK: store { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], { <8 x i8>, <8 x i8>, <8 x i8> }* [[TMP1]]
456 return vld1_s8_x3(a); 456 return vld1_s8_x3(a);
457 } 457 }
458 458
459 // CHECK-LABEL: @test_vld1_s8_x4( 459 // CHECK-LABEL: @test_vld1_s8_x4(
460 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int8x8x4_t, align 8 460 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int8x8x4_t, align 8
461 // CHECK-A32: %struct.int8x8x4_t* noalias sret align 8 [[RETVAL:%.*]], 461 // CHECK-A32: %struct.int8x8x4_t* noalias sret(%struct.int8x8x4_t) align 8 [[RETVAL:%.*]],
462 // CHECK: [[__RET:%.*]] = alloca %struct.int8x8x4_t, align 8 462 // CHECK: [[__RET:%.*]] = alloca %struct.int8x8x4_t, align 8
463 // CHECK: [[TMP0:%.*]] = bitcast %struct.int8x8x4_t* [[__RET]] to i8* 463 // CHECK: [[TMP0:%.*]] = bitcast %struct.int8x8x4_t* [[__RET]] to i8*
464 // CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v8i8.p0i8(i8* %a) 464 // CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v8i8.p0i8(i8* %a)
465 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }* 465 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }*
466 // CHECK: store { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }* [[TMP1]] 466 // CHECK: store { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }* [[TMP1]]
474 return vld1_s8_x4(a); 474 return vld1_s8_x4(a);
475 } 475 }
476 476
477 // CHECK-LABEL: @test_vld1_u16_x2( 477 // CHECK-LABEL: @test_vld1_u16_x2(
478 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint16x4x2_t, align 8 478 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint16x4x2_t, align 8
479 // CHECK-A32: %struct.uint16x4x2_t* noalias sret align 8 [[RETVAL:%.*]], 479 // CHECK-A32: %struct.uint16x4x2_t* noalias sret(%struct.uint16x4x2_t) align 8 [[RETVAL:%.*]],
480 // CHECK: [[__RET:%.*]] = alloca %struct.uint16x4x2_t, align 8 480 // CHECK: [[__RET:%.*]] = alloca %struct.uint16x4x2_t, align 8
481 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint16x4x2_t* [[__RET]] to i8* 481 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint16x4x2_t* [[__RET]] to i8*
482 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8* 482 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8*
483 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16* 483 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*
484 // CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v4i16.p0i16(i16* [[TMP2]]) 484 // CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v4i16.p0i16(i16* [[TMP2]])
494 return vld1_u16_x2(a); 494 return vld1_u16_x2(a);
495 } 495 }
496 496
497 // CHECK-LABEL: @test_vld1_u16_x3( 497 // CHECK-LABEL: @test_vld1_u16_x3(
498 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint16x4x3_t, align 8 498 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint16x4x3_t, align 8
499 // CHECK-A32: %struct.uint16x4x3_t* noalias sret align 8 [[RETVAL:%.*]], 499 // CHECK-A32: %struct.uint16x4x3_t* noalias sret(%struct.uint16x4x3_t) align 8 [[RETVAL:%.*]],
500 // CHECK: [[__RET:%.*]] = alloca %struct.uint16x4x3_t, align 8 500 // CHECK: [[__RET:%.*]] = alloca %struct.uint16x4x3_t, align 8
501 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint16x4x3_t* [[__RET]] to i8* 501 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint16x4x3_t* [[__RET]] to i8*
502 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8* 502 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8*
503 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16* 503 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*
504 // CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v4i16.p0i16(i16* [[TMP2]]) 504 // CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v4i16.p0i16(i16* [[TMP2]])
514 return vld1_u16_x3(a); 514 return vld1_u16_x3(a);
515 } 515 }
516 516
517 // CHECK-LABEL: @test_vld1_u16_x4( 517 // CHECK-LABEL: @test_vld1_u16_x4(
518 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint16x4x4_t, align 8 518 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint16x4x4_t, align 8
519 // CHECK-A32: %struct.uint16x4x4_t* noalias sret align 8 [[RETVAL:%.*]], 519 // CHECK-A32: %struct.uint16x4x4_t* noalias sret(%struct.uint16x4x4_t) align 8 [[RETVAL:%.*]],
520 // CHECK: [[__RET:%.*]] = alloca %struct.uint16x4x4_t, align 8 520 // CHECK: [[__RET:%.*]] = alloca %struct.uint16x4x4_t, align 8
521 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint16x4x4_t* [[__RET]] to i8* 521 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint16x4x4_t* [[__RET]] to i8*
522 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8* 522 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8*
523 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16* 523 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*
524 // CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v4i16.p0i16(i16* [[TMP2]]) 524 // CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v4i16.p0i16(i16* [[TMP2]])
534 return vld1_u16_x4(a); 534 return vld1_u16_x4(a);
535 } 535 }
536 536
537 // CHECK-LABEL: @test_vld1_u32_x2( 537 // CHECK-LABEL: @test_vld1_u32_x2(
538 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint32x2x2_t, align 8 538 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint32x2x2_t, align 8
539 // CHECK-A32: %struct.uint32x2x2_t* noalias sret align 8 [[RETVAL:%.*]], 539 // CHECK-A32: %struct.uint32x2x2_t* noalias sret(%struct.uint32x2x2_t) align 8 [[RETVAL:%.*]],
540 // CHECK: [[__RET:%.*]] = alloca %struct.uint32x2x2_t, align 8 540 // CHECK: [[__RET:%.*]] = alloca %struct.uint32x2x2_t, align 8
541 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint32x2x2_t* [[__RET]] to i8* 541 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint32x2x2_t* [[__RET]] to i8*
542 // CHECK: [[TMP1:%.*]] = bitcast i32* %a to i8* 542 // CHECK: [[TMP1:%.*]] = bitcast i32* %a to i8*
543 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32* 543 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32*
544 // CHECK: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v2i32.p0i32(i32* [[TMP2]]) 544 // CHECK: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v2i32.p0i32(i32* [[TMP2]])
554 return vld1_u32_x2(a); 554 return vld1_u32_x2(a);
555 } 555 }
556 556
557 // CHECK-LABEL: @test_vld1_u32_x3( 557 // CHECK-LABEL: @test_vld1_u32_x3(
558 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint32x2x3_t, align 8 558 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint32x2x3_t, align 8
559 // CHECK-A32: %struct.uint32x2x3_t* noalias sret align 8 [[RETVAL:%.*]], 559 // CHECK-A32: %struct.uint32x2x3_t* noalias sret(%struct.uint32x2x3_t) align 8 [[RETVAL:%.*]],
560 // CHECK: [[__RET:%.*]] = alloca %struct.uint32x2x3_t, align 8 560 // CHECK: [[__RET:%.*]] = alloca %struct.uint32x2x3_t, align 8
561 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint32x2x3_t* [[__RET]] to i8* 561 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint32x2x3_t* [[__RET]] to i8*
562 // CHECK: [[TMP1:%.*]] = bitcast i32* %a to i8* 562 // CHECK: [[TMP1:%.*]] = bitcast i32* %a to i8*
563 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32* 563 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32*
564 // CHECK: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v2i32.p0i32(i32* [[TMP2]]) 564 // CHECK: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v2i32.p0i32(i32* [[TMP2]])
574 return vld1_u32_x3(a); 574 return vld1_u32_x3(a);
575 } 575 }
576 576
577 // CHECK-LABEL: @test_vld1_u32_x4( 577 // CHECK-LABEL: @test_vld1_u32_x4(
578 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint32x2x4_t, align 8 578 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint32x2x4_t, align 8
579 // CHECK-A32: %struct.uint32x2x4_t* noalias sret align 8 [[RETVAL:%.*]], 579 // CHECK-A32: %struct.uint32x2x4_t* noalias sret(%struct.uint32x2x4_t) align 8 [[RETVAL:%.*]],
580 // CHECK: [[__RET:%.*]] = alloca %struct.uint32x2x4_t, align 8 580 // CHECK: [[__RET:%.*]] = alloca %struct.uint32x2x4_t, align 8
581 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint32x2x4_t* [[__RET]] to i8* 581 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint32x2x4_t* [[__RET]] to i8*
582 // CHECK: [[TMP1:%.*]] = bitcast i32* %a to i8* 582 // CHECK: [[TMP1:%.*]] = bitcast i32* %a to i8*
583 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32* 583 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32*
584 // CHECK: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v2i32.p0i32(i32* [[TMP2]]) 584 // CHECK: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v2i32.p0i32(i32* [[TMP2]])
594 return vld1_u32_x4(a); 594 return vld1_u32_x4(a);
595 } 595 }
596 596
597 // CHECK-LABEL: @test_vld1_u64_x2( 597 // CHECK-LABEL: @test_vld1_u64_x2(
598 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint64x1x2_t, align 8 598 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint64x1x2_t, align 8
599 // CHECK-A32: %struct.uint64x1x2_t* noalias sret align 8 [[RETVAL:%.*]], 599 // CHECK-A32: %struct.uint64x1x2_t* noalias sret(%struct.uint64x1x2_t) align 8 [[RETVAL:%.*]],
600 // CHECK: [[__RET:%.*]] = alloca %struct.uint64x1x2_t, align 8 600 // CHECK: [[__RET:%.*]] = alloca %struct.uint64x1x2_t, align 8
601 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint64x1x2_t* [[__RET]] to i8* 601 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint64x1x2_t* [[__RET]] to i8*
602 // CHECK: [[TMP1:%.*]] = bitcast i64* %a to i8* 602 // CHECK: [[TMP1:%.*]] = bitcast i64* %a to i8*
603 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i64* 603 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i64*
604 // CHECK: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v1i64.p0i64(i64* [[TMP2]]) 604 // CHECK: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v1i64.p0i64(i64* [[TMP2]])
614 return vld1_u64_x2(a); 614 return vld1_u64_x2(a);
615 } 615 }
616 616
617 // CHECK-LABEL: @test_vld1_u64_x3( 617 // CHECK-LABEL: @test_vld1_u64_x3(
618 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint64x1x3_t, align 8 618 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint64x1x3_t, align 8
619 // CHECK-A32: %struct.uint64x1x3_t* noalias sret align 8 [[RETVAL:%.*]], 619 // CHECK-A32: %struct.uint64x1x3_t* noalias sret(%struct.uint64x1x3_t) align 8 [[RETVAL:%.*]],
620 // CHECK: [[__RET:%.*]] = alloca %struct.uint64x1x3_t, align 8 620 // CHECK: [[__RET:%.*]] = alloca %struct.uint64x1x3_t, align 8
621 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint64x1x3_t* [[__RET]] to i8* 621 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint64x1x3_t* [[__RET]] to i8*
622 // CHECK: [[TMP1:%.*]] = bitcast i64* %a to i8* 622 // CHECK: [[TMP1:%.*]] = bitcast i64* %a to i8*
623 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i64* 623 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i64*
624 // CHECK: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v1i64.p0i64(i64* [[TMP2]]) 624 // CHECK: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v1i64.p0i64(i64* [[TMP2]])
634 return vld1_u64_x3(a); 634 return vld1_u64_x3(a);
635 } 635 }
636 636
637 // CHECK-LABEL: @test_vld1_u64_x4( 637 // CHECK-LABEL: @test_vld1_u64_x4(
638 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint64x1x4_t, align 8 638 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint64x1x4_t, align 8
639 // CHECK-A32: %struct.uint64x1x4_t* noalias sret align 8 [[RETVAL:%.*]], 639 // CHECK-A32: %struct.uint64x1x4_t* noalias sret(%struct.uint64x1x4_t) align 8 [[RETVAL:%.*]],
640 // CHECK: [[__RET:%.*]] = alloca %struct.uint64x1x4_t, align 8 640 // CHECK: [[__RET:%.*]] = alloca %struct.uint64x1x4_t, align 8
641 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint64x1x4_t* [[__RET]] to i8* 641 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint64x1x4_t* [[__RET]] to i8*
642 // CHECK: [[TMP1:%.*]] = bitcast i64* %a to i8* 642 // CHECK: [[TMP1:%.*]] = bitcast i64* %a to i8*
643 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i64* 643 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i64*
644 // CHECK: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v1i64.p0i64(i64* [[TMP2]]) 644 // CHECK: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v1i64.p0i64(i64* [[TMP2]])
654 return vld1_u64_x4(a); 654 return vld1_u64_x4(a);
655 } 655 }
656 656
657 // CHECK-LABEL: @test_vld1_u8_x2( 657 // CHECK-LABEL: @test_vld1_u8_x2(
658 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint8x8x2_t, align 8 658 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint8x8x2_t, align 8
659 // CHECK-A32: %struct.uint8x8x2_t* noalias sret align 8 [[RETVAL:%.*]], 659 // CHECK-A32: %struct.uint8x8x2_t* noalias sret(%struct.uint8x8x2_t) align 8 [[RETVAL:%.*]],
660 // CHECK: [[__RET:%.*]] = alloca %struct.uint8x8x2_t, align 8 660 // CHECK: [[__RET:%.*]] = alloca %struct.uint8x8x2_t, align 8
661 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint8x8x2_t* [[__RET]] to i8* 661 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint8x8x2_t* [[__RET]] to i8*
662 // CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v8i8.p0i8(i8* %a) 662 // CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v8i8.p0i8(i8* %a)
663 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <8 x i8>, <8 x i8> }* 663 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <8 x i8>, <8 x i8> }*
664 // CHECK: store { <8 x i8>, <8 x i8> } [[VLD1XN]], { <8 x i8>, <8 x i8> }* [[TMP1]] 664 // CHECK: store { <8 x i8>, <8 x i8> } [[VLD1XN]], { <8 x i8>, <8 x i8> }* [[TMP1]]
672 return vld1_u8_x2(a); 672 return vld1_u8_x2(a);
673 } 673 }
674 674
675 // CHECK-LABEL: @test_vld1_u8_x3( 675 // CHECK-LABEL: @test_vld1_u8_x3(
676 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint8x8x3_t, align 8 676 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint8x8x3_t, align 8
677 // CHECK-A32: %struct.uint8x8x3_t* noalias sret align 8 [[RETVAL:%.*]], 677 // CHECK-A32: %struct.uint8x8x3_t* noalias sret(%struct.uint8x8x3_t) align 8 [[RETVAL:%.*]],
678 // CHECK: [[__RET:%.*]] = alloca %struct.uint8x8x3_t, align 8 678 // CHECK: [[__RET:%.*]] = alloca %struct.uint8x8x3_t, align 8
679 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint8x8x3_t* [[__RET]] to i8* 679 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint8x8x3_t* [[__RET]] to i8*
680 // CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v8i8.p0i8(i8* %a) 680 // CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v8i8.p0i8(i8* %a)
681 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <8 x i8>, <8 x i8>, <8 x i8> }* 681 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <8 x i8>, <8 x i8>, <8 x i8> }*
682 // CHECK: store { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], { <8 x i8>, <8 x i8>, <8 x i8> }* [[TMP1]] 682 // CHECK: store { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], { <8 x i8>, <8 x i8>, <8 x i8> }* [[TMP1]]
690 return vld1_u8_x3(a); 690 return vld1_u8_x3(a);
691 } 691 }
692 692
693 // CHECK-LABEL: @test_vld1_u8_x4( 693 // CHECK-LABEL: @test_vld1_u8_x4(
694 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint8x8x4_t, align 8 694 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint8x8x4_t, align 8
695 // CHECK-A32: %struct.uint8x8x4_t* noalias sret align 8 [[RETVAL:%.*]], 695 // CHECK-A32: %struct.uint8x8x4_t* noalias sret(%struct.uint8x8x4_t) align 8 [[RETVAL:%.*]],
696 // CHECK: [[__RET:%.*]] = alloca %struct.uint8x8x4_t, align 8 696 // CHECK: [[__RET:%.*]] = alloca %struct.uint8x8x4_t, align 8
697 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint8x8x4_t* [[__RET]] to i8* 697 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint8x8x4_t* [[__RET]] to i8*
698 // CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v8i8.p0i8(i8* %a) 698 // CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v8i8.p0i8(i8* %a)
699 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }* 699 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }*
700 // CHECK: store { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }* [[TMP1]] 700 // CHECK: store { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }* [[TMP1]]
708 return vld1_u8_x4(a); 708 return vld1_u8_x4(a);
709 } 709 }
710 710
711 // CHECK-LABEL: @test_vld1q_f16_x2( 711 // CHECK-LABEL: @test_vld1q_f16_x2(
712 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float16x8x2_t, align 16 712 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float16x8x2_t, align 16
713 // CHECK-A32: %struct.float16x8x2_t* noalias sret align 8 [[RETVAL:%.*]], 713 // CHECK-A32: %struct.float16x8x2_t* noalias sret(%struct.float16x8x2_t) align 8 [[RETVAL:%.*]],
714 // CHECK: [[__RET:%.*]] = alloca %struct.float16x8x2_t, align {{16|8}} 714 // CHECK: [[__RET:%.*]] = alloca %struct.float16x8x2_t, align {{16|8}}
715 // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x8x2_t* [[__RET]] to i8* 715 // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x8x2_t* [[__RET]] to i8*
716 // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8* 716 // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*
717 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to [[HALF]]* 717 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to [[HALF]]*
718 // CHECK: [[VLD1XN:%.*]] = call { <8 x [[HALF]]>, <8 x [[HALF]]> } @llvm.{{aarch64.neon.ld1x2.v8f16.p0f16|arm.neon.vld1x2.v8i16.p0i16}}([[HALF]]* [[TMP2]]) 718 // CHECK: [[VLD1XN:%.*]] = call { <8 x [[HALF]]>, <8 x [[HALF]]> } @llvm.{{aarch64.neon.ld1x2.v8f16.p0f16|arm.neon.vld1x2.v8i16.p0i16}}([[HALF]]* [[TMP2]])
728 return vld1q_f16_x2(a); 728 return vld1q_f16_x2(a);
729 } 729 }
730 730
731 // CHECK-LABEL: @test_vld1q_f16_x3( 731 // CHECK-LABEL: @test_vld1q_f16_x3(
732 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float16x8x3_t, align 16 732 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float16x8x3_t, align 16
733 // CHECK-A32: %struct.float16x8x3_t* noalias sret align 8 [[RETVAL:%.*]], 733 // CHECK-A32: %struct.float16x8x3_t* noalias sret(%struct.float16x8x3_t) align 8 [[RETVAL:%.*]],
734 // CHECK: [[__RET:%.*]] = alloca %struct.float16x8x3_t, align {{16|8}} 734 // CHECK: [[__RET:%.*]] = alloca %struct.float16x8x3_t, align {{16|8}}
735 // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x8x3_t* [[__RET]] to i8* 735 // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x8x3_t* [[__RET]] to i8*
736 // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8* 736 // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*
737 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to [[HALF]]* 737 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to [[HALF]]*
738 // CHECK: [[VLD1XN:%.*]] = call { <8 x [[HALF]]>, <8 x [[HALF]]>, <8 x [[HALF]]> } @llvm.{{aarch64.neon.ld1x3.v8f16.p0f16|arm.neon.vld1x3.v8i16.p0i16}}([[HALF]]* [[TMP2]]) 738 // CHECK: [[VLD1XN:%.*]] = call { <8 x [[HALF]]>, <8 x [[HALF]]>, <8 x [[HALF]]> } @llvm.{{aarch64.neon.ld1x3.v8f16.p0f16|arm.neon.vld1x3.v8i16.p0i16}}([[HALF]]* [[TMP2]])
748 return vld1q_f16_x3(a); 748 return vld1q_f16_x3(a);
749 } 749 }
750 750
751 // CHECK-LABEL: @test_vld1q_f16_x4( 751 // CHECK-LABEL: @test_vld1q_f16_x4(
752 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float16x8x4_t, align 16 752 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float16x8x4_t, align 16
753 // CHECK-A32: %struct.float16x8x4_t* noalias sret align 8 [[RETVAL:%.*]], 753 // CHECK-A32: %struct.float16x8x4_t* noalias sret(%struct.float16x8x4_t) align 8 [[RETVAL:%.*]],
754 // CHECK: [[__RET:%.*]] = alloca %struct.float16x8x4_t, align {{16|8}} 754 // CHECK: [[__RET:%.*]] = alloca %struct.float16x8x4_t, align {{16|8}}
755 // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x8x4_t* [[__RET]] to i8* 755 // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x8x4_t* [[__RET]] to i8*
756 // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8* 756 // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*
757 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to [[HALF]]* 757 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to [[HALF]]*
758 // CHECK: [[VLD1XN:%.*]] = call { <8 x [[HALF]]>, <8 x [[HALF]]>, <8 x [[HALF]]>, <8 x [[HALF]]> } @llvm.{{aarch64.neon.ld1x4.v8f16.p0f16|arm.neon.vld1x4.v8i16.p0i16}}([[HALF]]* [[TMP2]]) 758 // CHECK: [[VLD1XN:%.*]] = call { <8 x [[HALF]]>, <8 x [[HALF]]>, <8 x [[HALF]]>, <8 x [[HALF]]> } @llvm.{{aarch64.neon.ld1x4.v8f16.p0f16|arm.neon.vld1x4.v8i16.p0i16}}([[HALF]]* [[TMP2]])
768 return vld1q_f16_x4(a); 768 return vld1q_f16_x4(a);
769 } 769 }
770 770
771 // CHECK-LABEL: @test_vld1q_f32_x2( 771 // CHECK-LABEL: @test_vld1q_f32_x2(
772 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float32x4x2_t, align 16 772 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float32x4x2_t, align 16
773 // CHECK-A32: %struct.float32x4x2_t* noalias sret align 8 [[RETVAL:%.*]], 773 // CHECK-A32: %struct.float32x4x2_t* noalias sret(%struct.float32x4x2_t) align 8 [[RETVAL:%.*]],
774 // CHECK: [[__RET:%.*]] = alloca %struct.float32x4x2_t, align {{16|8}} 774 // CHECK: [[__RET:%.*]] = alloca %struct.float32x4x2_t, align {{16|8}}
775 // CHECK: [[TMP0:%.*]] = bitcast %struct.float32x4x2_t* [[__RET]] to i8* 775 // CHECK: [[TMP0:%.*]] = bitcast %struct.float32x4x2_t* [[__RET]] to i8*
776 // CHECK: [[TMP1:%.*]] = bitcast float* %a to i8* 776 // CHECK: [[TMP1:%.*]] = bitcast float* %a to i8*
777 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to float* 777 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to float*
778 // CHECK: [[VLD1XN:%.*]] = call { <4 x float>, <4 x float> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v4f32.p0f32(float* [[TMP2]]) 778 // CHECK: [[VLD1XN:%.*]] = call { <4 x float>, <4 x float> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v4f32.p0f32(float* [[TMP2]])
788 return vld1q_f32_x2(a); 788 return vld1q_f32_x2(a);
789 } 789 }
790 790
791 // CHECK-LABEL: @test_vld1q_f32_x3( 791 // CHECK-LABEL: @test_vld1q_f32_x3(
792 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float32x4x3_t, align 16 792 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float32x4x3_t, align 16
793 // CHECK-A32: %struct.float32x4x3_t* noalias sret align 8 [[RETVAL:%.*]], 793 // CHECK-A32: %struct.float32x4x3_t* noalias sret(%struct.float32x4x3_t) align 8 [[RETVAL:%.*]],
794 // CHECK: [[__RET:%.*]] = alloca %struct.float32x4x3_t, align {{16|8}} 794 // CHECK: [[__RET:%.*]] = alloca %struct.float32x4x3_t, align {{16|8}}
795 // CHECK: [[TMP0:%.*]] = bitcast %struct.float32x4x3_t* [[__RET]] to i8* 795 // CHECK: [[TMP0:%.*]] = bitcast %struct.float32x4x3_t* [[__RET]] to i8*
796 // CHECK: [[TMP1:%.*]] = bitcast float* %a to i8* 796 // CHECK: [[TMP1:%.*]] = bitcast float* %a to i8*
797 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to float* 797 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to float*
798 // CHECK: [[VLD1XN:%.*]] = call { <4 x float>, <4 x float>, <4 x float> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v4f32.p0f32(float* [[TMP2]]) 798 // CHECK: [[VLD1XN:%.*]] = call { <4 x float>, <4 x float>, <4 x float> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v4f32.p0f32(float* [[TMP2]])
808 return vld1q_f32_x3(a); 808 return vld1q_f32_x3(a);
809 } 809 }
810 810
811 // CHECK-LABEL: @test_vld1q_f32_x4( 811 // CHECK-LABEL: @test_vld1q_f32_x4(
812 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float32x4x4_t, align 16 812 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float32x4x4_t, align 16
813 // CHECK-A32: %struct.float32x4x4_t* noalias sret align 8 [[RETVAL:%.*]], 813 // CHECK-A32: %struct.float32x4x4_t* noalias sret(%struct.float32x4x4_t) align 8 [[RETVAL:%.*]],
814 // CHECK: [[__RET:%.*]] = alloca %struct.float32x4x4_t, align {{16|8}} 814 // CHECK: [[__RET:%.*]] = alloca %struct.float32x4x4_t, align {{16|8}}
815 // CHECK: [[TMP0:%.*]] = bitcast %struct.float32x4x4_t* [[__RET]] to i8* 815 // CHECK: [[TMP0:%.*]] = bitcast %struct.float32x4x4_t* [[__RET]] to i8*
816 // CHECK: [[TMP1:%.*]] = bitcast float* %a to i8* 816 // CHECK: [[TMP1:%.*]] = bitcast float* %a to i8*
817 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to float* 817 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to float*
818 // CHECK: [[VLD1XN:%.*]] = call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v4f32.p0f32(float* [[TMP2]]) 818 // CHECK: [[VLD1XN:%.*]] = call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v4f32.p0f32(float* [[TMP2]])
828 return vld1q_f32_x4(a); 828 return vld1q_f32_x4(a);
829 } 829 }
830 830
831 // CHECK-LABEL: @test_vld1q_p16_x2( 831 // CHECK-LABEL: @test_vld1q_p16_x2(
832 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly16x8x2_t, align 16 832 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly16x8x2_t, align 16
833 // CHECK-A32: %struct.poly16x8x2_t* noalias sret align 8 [[RETVAL:%.*]], 833 // CHECK-A32: %struct.poly16x8x2_t* noalias sret(%struct.poly16x8x2_t) align 8 [[RETVAL:%.*]],
834 // CHECK: [[__RET:%.*]] = alloca %struct.poly16x8x2_t, align {{16|8}} 834 // CHECK: [[__RET:%.*]] = alloca %struct.poly16x8x2_t, align {{16|8}}
835 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly16x8x2_t* [[__RET]] to i8* 835 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly16x8x2_t* [[__RET]] to i8*
836 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8* 836 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8*
837 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16* 837 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*
838 // CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v8i16.p0i16(i16* [[TMP2]]) 838 // CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v8i16.p0i16(i16* [[TMP2]])
848 return vld1q_p16_x2(a); 848 return vld1q_p16_x2(a);
849 } 849 }
850 850
851 // CHECK-LABEL: @test_vld1q_p16_x3( 851 // CHECK-LABEL: @test_vld1q_p16_x3(
852 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly16x8x3_t, align 16 852 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly16x8x3_t, align 16
853 // CHECK-A32: %struct.poly16x8x3_t* noalias sret align 8 [[RETVAL:%.*]], 853 // CHECK-A32: %struct.poly16x8x3_t* noalias sret(%struct.poly16x8x3_t) align 8 [[RETVAL:%.*]],
854 // CHECK: [[__RET:%.*]] = alloca %struct.poly16x8x3_t, align {{16|8}} 854 // CHECK: [[__RET:%.*]] = alloca %struct.poly16x8x3_t, align {{16|8}}
855 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly16x8x3_t* [[__RET]] to i8* 855 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly16x8x3_t* [[__RET]] to i8*
856 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8* 856 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8*
857 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16* 857 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*
858 // CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v8i16.p0i16(i16* [[TMP2]]) 858 // CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v8i16.p0i16(i16* [[TMP2]])
868 return vld1q_p16_x3(a); 868 return vld1q_p16_x3(a);
869 } 869 }
870 870
871 // CHECK-LABEL: @test_vld1q_p16_x4( 871 // CHECK-LABEL: @test_vld1q_p16_x4(
872 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly16x8x4_t, align 16 872 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly16x8x4_t, align 16
873 // CHECK-A32: %struct.poly16x8x4_t* noalias sret align 8 [[RETVAL:%.*]], 873 // CHECK-A32: %struct.poly16x8x4_t* noalias sret(%struct.poly16x8x4_t) align 8 [[RETVAL:%.*]],
874 // CHECK: [[__RET:%.*]] = alloca %struct.poly16x8x4_t, align {{16|8}} 874 // CHECK: [[__RET:%.*]] = alloca %struct.poly16x8x4_t, align {{16|8}}
875 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly16x8x4_t* [[__RET]] to i8* 875 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly16x8x4_t* [[__RET]] to i8*
876 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8* 876 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8*
877 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16* 877 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*
878 // CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v8i16.p0i16(i16* [[TMP2]]) 878 // CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v8i16.p0i16(i16* [[TMP2]])
888 return vld1q_p16_x4(a); 888 return vld1q_p16_x4(a);
889 } 889 }
890 890
891 // CHECK-LABEL: @test_vld1q_p8_x2( 891 // CHECK-LABEL: @test_vld1q_p8_x2(
892 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly8x16x2_t, align 16 892 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly8x16x2_t, align 16
893 // CHECK-A32: %struct.poly8x16x2_t* noalias sret align 8 [[RETVAL:%.*]], 893 // CHECK-A32: %struct.poly8x16x2_t* noalias sret(%struct.poly8x16x2_t) align 8 [[RETVAL:%.*]],
894 // CHECK: [[__RET:%.*]] = alloca %struct.poly8x16x2_t, align {{16|8}} 894 // CHECK: [[__RET:%.*]] = alloca %struct.poly8x16x2_t, align {{16|8}}
895 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly8x16x2_t* [[__RET]] to i8* 895 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly8x16x2_t* [[__RET]] to i8*
896 // CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v16i8.p0i8(i8* %a) 896 // CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v16i8.p0i8(i8* %a)
897 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <16 x i8>, <16 x i8> }* 897 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <16 x i8>, <16 x i8> }*
898 // CHECK: store { <16 x i8>, <16 x i8> } [[VLD1XN]], { <16 x i8>, <16 x i8> }* [[TMP1]] 898 // CHECK: store { <16 x i8>, <16 x i8> } [[VLD1XN]], { <16 x i8>, <16 x i8> }* [[TMP1]]
906 return vld1q_p8_x2(a); 906 return vld1q_p8_x2(a);
907 } 907 }
908 908
909 // CHECK-LABEL: @test_vld1q_p8_x3( 909 // CHECK-LABEL: @test_vld1q_p8_x3(
910 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly8x16x3_t, align 16 910 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly8x16x3_t, align 16
911 // CHECK-A32: %struct.poly8x16x3_t* noalias sret align 8 [[RETVAL:%.*]], 911 // CHECK-A32: %struct.poly8x16x3_t* noalias sret(%struct.poly8x16x3_t) align 8 [[RETVAL:%.*]],
912 // CHECK: [[__RET:%.*]] = alloca %struct.poly8x16x3_t, align {{16|8}} 912 // CHECK: [[__RET:%.*]] = alloca %struct.poly8x16x3_t, align {{16|8}}
913 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly8x16x3_t* [[__RET]] to i8* 913 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly8x16x3_t* [[__RET]] to i8*
914 // CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v16i8.p0i8(i8* %a) 914 // CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v16i8.p0i8(i8* %a)
915 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <16 x i8>, <16 x i8>, <16 x i8> }* 915 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <16 x i8>, <16 x i8>, <16 x i8> }*
916 // CHECK: store { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], { <16 x i8>, <16 x i8>, <16 x i8> }* [[TMP1]] 916 // CHECK: store { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], { <16 x i8>, <16 x i8>, <16 x i8> }* [[TMP1]]
924 return vld1q_p8_x3(a); 924 return vld1q_p8_x3(a);
925 } 925 }
926 926
927 // CHECK-LABEL: @test_vld1q_p8_x4( 927 // CHECK-LABEL: @test_vld1q_p8_x4(
928 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly8x16x4_t, align 16 928 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly8x16x4_t, align 16
929 // CHECK-A32: %struct.poly8x16x4_t* noalias sret align 8 [[RETVAL:%.*]], 929 // CHECK-A32: %struct.poly8x16x4_t* noalias sret(%struct.poly8x16x4_t) align 8 [[RETVAL:%.*]],
930 // CHECK: [[__RET:%.*]] = alloca %struct.poly8x16x4_t, align {{16|8}} 930 // CHECK: [[__RET:%.*]] = alloca %struct.poly8x16x4_t, align {{16|8}}
931 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly8x16x4_t* [[__RET]] to i8* 931 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly8x16x4_t* [[__RET]] to i8*
932 // CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v16i8.p0i8(i8* %a) 932 // CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v16i8.p0i8(i8* %a)
933 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> }* 933 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> }*
934 // CHECK: store { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> }* [[TMP1]] 934 // CHECK: store { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> }* [[TMP1]]
942 return vld1q_p8_x4(a); 942 return vld1q_p8_x4(a);
943 } 943 }
944 944
945 // CHECK-LABEL: @test_vld1q_s16_x2( 945 // CHECK-LABEL: @test_vld1q_s16_x2(
946 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int16x8x2_t, align 16 946 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int16x8x2_t, align 16
947 // CHECK-A32: %struct.int16x8x2_t* noalias sret align 8 [[RETVAL:%.*]], 947 // CHECK-A32: %struct.int16x8x2_t* noalias sret(%struct.int16x8x2_t) align 8 [[RETVAL:%.*]],
948 // CHECK: [[__RET:%.*]] = alloca %struct.int16x8x2_t, align {{16|8}} 948 // CHECK: [[__RET:%.*]] = alloca %struct.int16x8x2_t, align {{16|8}}
949 // CHECK: [[TMP0:%.*]] = bitcast %struct.int16x8x2_t* [[__RET]] to i8* 949 // CHECK: [[TMP0:%.*]] = bitcast %struct.int16x8x2_t* [[__RET]] to i8*
950 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8* 950 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8*
951 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16* 951 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*
952 // CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v8i16.p0i16(i16* [[TMP2]]) 952 // CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v8i16.p0i16(i16* [[TMP2]])
962 return vld1q_s16_x2(a); 962 return vld1q_s16_x2(a);
963 } 963 }
964 964
965 // CHECK-LABEL: @test_vld1q_s16_x3( 965 // CHECK-LABEL: @test_vld1q_s16_x3(
966 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int16x8x3_t, align 16 966 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int16x8x3_t, align 16
967 // CHECK-A32: %struct.int16x8x3_t* noalias sret align 8 [[RETVAL:%.*]], 967 // CHECK-A32: %struct.int16x8x3_t* noalias sret(%struct.int16x8x3_t) align 8 [[RETVAL:%.*]],
968 // CHECK: [[__RET:%.*]] = alloca %struct.int16x8x3_t, align {{16|8}} 968 // CHECK: [[__RET:%.*]] = alloca %struct.int16x8x3_t, align {{16|8}}
969 // CHECK: [[TMP0:%.*]] = bitcast %struct.int16x8x3_t* [[__RET]] to i8* 969 // CHECK: [[TMP0:%.*]] = bitcast %struct.int16x8x3_t* [[__RET]] to i8*
970 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8* 970 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8*
971 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16* 971 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*
972 // CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v8i16.p0i16(i16* [[TMP2]]) 972 // CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v8i16.p0i16(i16* [[TMP2]])
982 return vld1q_s16_x3(a); 982 return vld1q_s16_x3(a);
983 } 983 }
984 984
985 // CHECK-LABEL: @test_vld1q_s16_x4( 985 // CHECK-LABEL: @test_vld1q_s16_x4(
986 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int16x8x4_t, align 16 986 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int16x8x4_t, align 16
987 // CHECK-A32: %struct.int16x8x4_t* noalias sret align 8 [[RETVAL:%.*]], 987 // CHECK-A32: %struct.int16x8x4_t* noalias sret(%struct.int16x8x4_t) align 8 [[RETVAL:%.*]],
988 // CHECK: [[__RET:%.*]] = alloca %struct.int16x8x4_t, align {{16|8}} 988 // CHECK: [[__RET:%.*]] = alloca %struct.int16x8x4_t, align {{16|8}}
989 // CHECK: [[TMP0:%.*]] = bitcast %struct.int16x8x4_t* [[__RET]] to i8* 989 // CHECK: [[TMP0:%.*]] = bitcast %struct.int16x8x4_t* [[__RET]] to i8*
990 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8* 990 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8*
991 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16* 991 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*
992 // CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v8i16.p0i16(i16* [[TMP2]]) 992 // CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v8i16.p0i16(i16* [[TMP2]])
1002 return vld1q_s16_x4(a); 1002 return vld1q_s16_x4(a);
1003 } 1003 }
1004 1004
1005 // CHECK-LABEL: @test_vld1q_s32_x2( 1005 // CHECK-LABEL: @test_vld1q_s32_x2(
1006 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int32x4x2_t, align 16 1006 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int32x4x2_t, align 16
1007 // CHECK-A32: %struct.int32x4x2_t* noalias sret align 8 [[RETVAL:%.*]], 1007 // CHECK-A32: %struct.int32x4x2_t* noalias sret(%struct.int32x4x2_t) align 8 [[RETVAL:%.*]],
1008 // CHECK: [[__RET:%.*]] = alloca %struct.int32x4x2_t, align {{16|8}} 1008 // CHECK: [[__RET:%.*]] = alloca %struct.int32x4x2_t, align {{16|8}}
1009 // CHECK: [[TMP0:%.*]] = bitcast %struct.int32x4x2_t* [[__RET]] to i8* 1009 // CHECK: [[TMP0:%.*]] = bitcast %struct.int32x4x2_t* [[__RET]] to i8*
1010 // CHECK: [[TMP1:%.*]] = bitcast i32* %a to i8* 1010 // CHECK: [[TMP1:%.*]] = bitcast i32* %a to i8*
1011 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32* 1011 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32*
1012 // CHECK: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v4i32.p0i32(i32* [[TMP2]]) 1012 // CHECK: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v4i32.p0i32(i32* [[TMP2]])
1022 return vld1q_s32_x2(a); 1022 return vld1q_s32_x2(a);
1023 } 1023 }
1024 1024
1025 // CHECK-LABEL: @test_vld1q_s32_x3( 1025 // CHECK-LABEL: @test_vld1q_s32_x3(
1026 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int32x4x3_t, align 16 1026 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int32x4x3_t, align 16
1027 // CHECK-A32: %struct.int32x4x3_t* noalias sret align 8 [[RETVAL:%.*]], 1027 // CHECK-A32: %struct.int32x4x3_t* noalias sret(%struct.int32x4x3_t) align 8 [[RETVAL:%.*]],
1028 // CHECK: [[__RET:%.*]] = alloca %struct.int32x4x3_t, align {{16|8}} 1028 // CHECK: [[__RET:%.*]] = alloca %struct.int32x4x3_t, align {{16|8}}
1029 // CHECK: [[TMP0:%.*]] = bitcast %struct.int32x4x3_t* [[__RET]] to i8* 1029 // CHECK: [[TMP0:%.*]] = bitcast %struct.int32x4x3_t* [[__RET]] to i8*
1030 // CHECK: [[TMP1:%.*]] = bitcast i32* %a to i8* 1030 // CHECK: [[TMP1:%.*]] = bitcast i32* %a to i8*
1031 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32* 1031 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32*
1032 // CHECK: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v4i32.p0i32(i32* [[TMP2]]) 1032 // CHECK: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v4i32.p0i32(i32* [[TMP2]])
1042 return vld1q_s32_x3(a); 1042 return vld1q_s32_x3(a);
1043 } 1043 }
1044 1044
1045 // CHECK-LABEL: @test_vld1q_s32_x4( 1045 // CHECK-LABEL: @test_vld1q_s32_x4(
1046 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int32x4x4_t, align 16 1046 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int32x4x4_t, align 16
1047 // CHECK-A32: %struct.int32x4x4_t* noalias sret align 8 [[RETVAL:%.*]], 1047 // CHECK-A32: %struct.int32x4x4_t* noalias sret(%struct.int32x4x4_t) align 8 [[RETVAL:%.*]],
1048 // CHECK: [[__RET:%.*]] = alloca %struct.int32x4x4_t, align {{16|8}} 1048 // CHECK: [[__RET:%.*]] = alloca %struct.int32x4x4_t, align {{16|8}}
1049 // CHECK: [[TMP0:%.*]] = bitcast %struct.int32x4x4_t* [[__RET]] to i8* 1049 // CHECK: [[TMP0:%.*]] = bitcast %struct.int32x4x4_t* [[__RET]] to i8*
1050 // CHECK: [[TMP1:%.*]] = bitcast i32* %a to i8* 1050 // CHECK: [[TMP1:%.*]] = bitcast i32* %a to i8*
1051 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32* 1051 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32*
1052 // CHECK: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v4i32.p0i32(i32* [[TMP2]]) 1052 // CHECK: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v4i32.p0i32(i32* [[TMP2]])
1062 return vld1q_s32_x4(a); 1062 return vld1q_s32_x4(a);
1063 } 1063 }
1064 1064
1065 // CHECK-LABEL: @test_vld1q_s64_x2( 1065 // CHECK-LABEL: @test_vld1q_s64_x2(
1066 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int64x2x2_t, align 16 1066 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int64x2x2_t, align 16
1067 // CHECK-A32: %struct.int64x2x2_t* noalias sret align 8 [[RETVAL:%.*]], 1067 // CHECK-A32: %struct.int64x2x2_t* noalias sret(%struct.int64x2x2_t) align 8 [[RETVAL:%.*]],
1068 // CHECK: [[__RET:%.*]] = alloca %struct.int64x2x2_t, align {{16|8}} 1068 // CHECK: [[__RET:%.*]] = alloca %struct.int64x2x2_t, align {{16|8}}
1069 // CHECK: [[TMP0:%.*]] = bitcast %struct.int64x2x2_t* [[__RET]] to i8* 1069 // CHECK: [[TMP0:%.*]] = bitcast %struct.int64x2x2_t* [[__RET]] to i8*
1070 // CHECK: [[TMP1:%.*]] = bitcast i64* %a to i8* 1070 // CHECK: [[TMP1:%.*]] = bitcast i64* %a to i8*
1071 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i64* 1071 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i64*
1072 // CHECK: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v2i64.p0i64(i64* [[TMP2]]) 1072 // CHECK: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v2i64.p0i64(i64* [[TMP2]])
1082 return vld1q_s64_x2(a); 1082 return vld1q_s64_x2(a);
1083 } 1083 }
1084 1084
1085 // CHECK-LABEL: @test_vld1q_s64_x3( 1085 // CHECK-LABEL: @test_vld1q_s64_x3(
1086 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int64x2x3_t, align 16 1086 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int64x2x3_t, align 16
1087 // CHECK-A32: %struct.int64x2x3_t* noalias sret align 8 [[RETVAL:%.*]], 1087 // CHECK-A32: %struct.int64x2x3_t* noalias sret(%struct.int64x2x3_t) align 8 [[RETVAL:%.*]],
1088 // CHECK: [[__RET:%.*]] = alloca %struct.int64x2x3_t, align {{16|8}} 1088 // CHECK: [[__RET:%.*]] = alloca %struct.int64x2x3_t, align {{16|8}}
1089 // CHECK: [[TMP0:%.*]] = bitcast %struct.int64x2x3_t* [[__RET]] to i8* 1089 // CHECK: [[TMP0:%.*]] = bitcast %struct.int64x2x3_t* [[__RET]] to i8*
1090 // CHECK: [[TMP1:%.*]] = bitcast i64* %a to i8* 1090 // CHECK: [[TMP1:%.*]] = bitcast i64* %a to i8*
1091 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i64* 1091 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i64*
1092 // CHECK: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v2i64.p0i64(i64* [[TMP2]]) 1092 // CHECK: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v2i64.p0i64(i64* [[TMP2]])
1102 return vld1q_s64_x3(a); 1102 return vld1q_s64_x3(a);
1103 } 1103 }
1104 1104
1105 // CHECK-LABEL: @test_vld1q_s64_x4( 1105 // CHECK-LABEL: @test_vld1q_s64_x4(
1106 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int64x2x4_t, align 16 1106 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int64x2x4_t, align 16
1107 // CHECK-A32: %struct.int64x2x4_t* noalias sret align 8 [[RETVAL:%.*]], 1107 // CHECK-A32: %struct.int64x2x4_t* noalias sret(%struct.int64x2x4_t) align 8 [[RETVAL:%.*]],
1108 // CHECK: [[__RET:%.*]] = alloca %struct.int64x2x4_t, align {{16|8}} 1108 // CHECK: [[__RET:%.*]] = alloca %struct.int64x2x4_t, align {{16|8}}
1109 // CHECK: [[TMP0:%.*]] = bitcast %struct.int64x2x4_t* [[__RET]] to i8* 1109 // CHECK: [[TMP0:%.*]] = bitcast %struct.int64x2x4_t* [[__RET]] to i8*
1110 // CHECK: [[TMP1:%.*]] = bitcast i64* %a to i8* 1110 // CHECK: [[TMP1:%.*]] = bitcast i64* %a to i8*
1111 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i64* 1111 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i64*
1112 // CHECK: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v2i64.p0i64(i64* [[TMP2]]) 1112 // CHECK: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v2i64.p0i64(i64* [[TMP2]])
1122 return vld1q_s64_x4(a); 1122 return vld1q_s64_x4(a);
1123 } 1123 }
1124 1124
1125 // CHECK-LABEL: @test_vld1q_s8_x2( 1125 // CHECK-LABEL: @test_vld1q_s8_x2(
1126 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int8x16x2_t, align 16 1126 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int8x16x2_t, align 16
1127 // CHECK-A32: %struct.int8x16x2_t* noalias sret align 8 [[RETVAL:%.*]], 1127 // CHECK-A32: %struct.int8x16x2_t* noalias sret(%struct.int8x16x2_t) align 8 [[RETVAL:%.*]],
1128 // CHECK: [[__RET:%.*]] = alloca %struct.int8x16x2_t, align {{16|8}} 1128 // CHECK: [[__RET:%.*]] = alloca %struct.int8x16x2_t, align {{16|8}}
1129 // CHECK: [[TMP0:%.*]] = bitcast %struct.int8x16x2_t* [[__RET]] to i8* 1129 // CHECK: [[TMP0:%.*]] = bitcast %struct.int8x16x2_t* [[__RET]] to i8*
1130 // CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v16i8.p0i8(i8* %a) 1130 // CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v16i8.p0i8(i8* %a)
1131 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <16 x i8>, <16 x i8> }* 1131 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <16 x i8>, <16 x i8> }*
1132 // CHECK: store { <16 x i8>, <16 x i8> } [[VLD1XN]], { <16 x i8>, <16 x i8> }* [[TMP1]] 1132 // CHECK: store { <16 x i8>, <16 x i8> } [[VLD1XN]], { <16 x i8>, <16 x i8> }* [[TMP1]]
1140 return vld1q_s8_x2(a); 1140 return vld1q_s8_x2(a);
1141 } 1141 }
1142 1142
1143 // CHECK-LABEL: @test_vld1q_s8_x3( 1143 // CHECK-LABEL: @test_vld1q_s8_x3(
1144 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int8x16x3_t, align 16 1144 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int8x16x3_t, align 16
1145 // CHECK-A32: %struct.int8x16x3_t* noalias sret align 8 [[RETVAL:%.*]], 1145 // CHECK-A32: %struct.int8x16x3_t* noalias sret(%struct.int8x16x3_t) align 8 [[RETVAL:%.*]],
1146 // CHECK: [[__RET:%.*]] = alloca %struct.int8x16x3_t, align {{16|8}} 1146 // CHECK: [[__RET:%.*]] = alloca %struct.int8x16x3_t, align {{16|8}}
1147 // CHECK: [[TMP0:%.*]] = bitcast %struct.int8x16x3_t* [[__RET]] to i8* 1147 // CHECK: [[TMP0:%.*]] = bitcast %struct.int8x16x3_t* [[__RET]] to i8*
1148 // CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v16i8.p0i8(i8* %a) 1148 // CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v16i8.p0i8(i8* %a)
1149 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <16 x i8>, <16 x i8>, <16 x i8> }* 1149 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <16 x i8>, <16 x i8>, <16 x i8> }*
1150 // CHECK: store { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], { <16 x i8>, <16 x i8>, <16 x i8> }* [[TMP1]] 1150 // CHECK: store { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], { <16 x i8>, <16 x i8>, <16 x i8> }* [[TMP1]]
1158 return vld1q_s8_x3(a); 1158 return vld1q_s8_x3(a);
1159 } 1159 }
1160 1160
1161 // CHECK-LABEL: @test_vld1q_s8_x4( 1161 // CHECK-LABEL: @test_vld1q_s8_x4(
1162 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int8x16x4_t, align 16 1162 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int8x16x4_t, align 16
1163 // CHECK-A32: %struct.int8x16x4_t* noalias sret align 8 [[RETVAL:%.*]], 1163 // CHECK-A32: %struct.int8x16x4_t* noalias sret(%struct.int8x16x4_t) align 8 [[RETVAL:%.*]],
1164 // CHECK: [[__RET:%.*]] = alloca %struct.int8x16x4_t, align {{16|8}} 1164 // CHECK: [[__RET:%.*]] = alloca %struct.int8x16x4_t, align {{16|8}}
1165 // CHECK: [[TMP0:%.*]] = bitcast %struct.int8x16x4_t* [[__RET]] to i8* 1165 // CHECK: [[TMP0:%.*]] = bitcast %struct.int8x16x4_t* [[__RET]] to i8*
1166 // CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v16i8.p0i8(i8* %a) 1166 // CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v16i8.p0i8(i8* %a)
1167 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> }* 1167 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> }*
1168 // CHECK: store { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> }* [[TMP1]] 1168 // CHECK: store { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> }* [[TMP1]]
1176 return vld1q_s8_x4(a); 1176 return vld1q_s8_x4(a);
1177 } 1177 }
1178 1178
1179 // CHECK-LABEL: @test_vld1q_u16_x2( 1179 // CHECK-LABEL: @test_vld1q_u16_x2(
1180 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint16x8x2_t, align 16 1180 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint16x8x2_t, align 16
1181 // CHECK-A32: %struct.uint16x8x2_t* noalias sret align 8 [[RETVAL:%.*]], 1181 // CHECK-A32: %struct.uint16x8x2_t* noalias sret(%struct.uint16x8x2_t) align 8 [[RETVAL:%.*]],
1182 // CHECK: [[__RET:%.*]] = alloca %struct.uint16x8x2_t, align {{16|8}} 1182 // CHECK: [[__RET:%.*]] = alloca %struct.uint16x8x2_t, align {{16|8}}
1183 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint16x8x2_t* [[__RET]] to i8* 1183 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint16x8x2_t* [[__RET]] to i8*
1184 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8* 1184 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8*
1185 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16* 1185 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*
1186 // CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v8i16.p0i16(i16* [[TMP2]]) 1186 // CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v8i16.p0i16(i16* [[TMP2]])
1196 return vld1q_u16_x2(a); 1196 return vld1q_u16_x2(a);
1197 } 1197 }
1198 1198
1199 // CHECK-LABEL: @test_vld1q_u16_x3( 1199 // CHECK-LABEL: @test_vld1q_u16_x3(
1200 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint16x8x3_t, align 16 1200 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint16x8x3_t, align 16
1201 // CHECK-A32: %struct.uint16x8x3_t* noalias sret align 8 [[RETVAL:%.*]], 1201 // CHECK-A32: %struct.uint16x8x3_t* noalias sret(%struct.uint16x8x3_t) align 8 [[RETVAL:%.*]],
1202 // CHECK: [[__RET:%.*]] = alloca %struct.uint16x8x3_t, align {{16|8}} 1202 // CHECK: [[__RET:%.*]] = alloca %struct.uint16x8x3_t, align {{16|8}}
1203 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint16x8x3_t* [[__RET]] to i8* 1203 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint16x8x3_t* [[__RET]] to i8*
1204 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8* 1204 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8*
1205 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16* 1205 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*
1206 // CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v8i16.p0i16(i16* [[TMP2]]) 1206 // CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v8i16.p0i16(i16* [[TMP2]])
1216 return vld1q_u16_x3(a); 1216 return vld1q_u16_x3(a);
1217 } 1217 }
1218 1218
1219 // CHECK-LABEL: @test_vld1q_u16_x4( 1219 // CHECK-LABEL: @test_vld1q_u16_x4(
1220 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint16x8x4_t, align 16 1220 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint16x8x4_t, align 16
1221 // CHECK-A32: %struct.uint16x8x4_t* noalias sret align 8 [[RETVAL:%.*]], 1221 // CHECK-A32: %struct.uint16x8x4_t* noalias sret(%struct.uint16x8x4_t) align 8 [[RETVAL:%.*]],
1222 // CHECK: [[__RET:%.*]] = alloca %struct.uint16x8x4_t, align {{16|8}} 1222 // CHECK: [[__RET:%.*]] = alloca %struct.uint16x8x4_t, align {{16|8}}
1223 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint16x8x4_t* [[__RET]] to i8* 1223 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint16x8x4_t* [[__RET]] to i8*
1224 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8* 1224 // CHECK: [[TMP1:%.*]] = bitcast i16* %a to i8*
1225 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16* 1225 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*
1226 // CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v8i16.p0i16(i16* [[TMP2]]) 1226 // CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v8i16.p0i16(i16* [[TMP2]])
1236 return vld1q_u16_x4(a); 1236 return vld1q_u16_x4(a);
1237 } 1237 }
1238 1238
1239 // CHECK-LABEL: @test_vld1q_u32_x2( 1239 // CHECK-LABEL: @test_vld1q_u32_x2(
1240 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint32x4x2_t, align 16 1240 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint32x4x2_t, align 16
1241 // CHECK-A32: %struct.uint32x4x2_t* noalias sret align 8 [[RETVAL:%.*]], 1241 // CHECK-A32: %struct.uint32x4x2_t* noalias sret(%struct.uint32x4x2_t) align 8 [[RETVAL:%.*]],
1242 // CHECK: [[__RET:%.*]] = alloca %struct.uint32x4x2_t, align {{16|8}} 1242 // CHECK: [[__RET:%.*]] = alloca %struct.uint32x4x2_t, align {{16|8}}
1243 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint32x4x2_t* [[__RET]] to i8* 1243 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint32x4x2_t* [[__RET]] to i8*
1244 // CHECK: [[TMP1:%.*]] = bitcast i32* %a to i8* 1244 // CHECK: [[TMP1:%.*]] = bitcast i32* %a to i8*
1245 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32* 1245 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32*
1246 // CHECK: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v4i32.p0i32(i32* [[TMP2]]) 1246 // CHECK: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v4i32.p0i32(i32* [[TMP2]])
1256 return vld1q_u32_x2(a); 1256 return vld1q_u32_x2(a);
1257 } 1257 }
1258 1258
1259 // CHECK-LABEL: @test_vld1q_u32_x3( 1259 // CHECK-LABEL: @test_vld1q_u32_x3(
1260 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint32x4x3_t, align 16 1260 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint32x4x3_t, align 16
1261 // CHECK-A32: %struct.uint32x4x3_t* noalias sret align 8 [[RETVAL:%.*]], 1261 // CHECK-A32: %struct.uint32x4x3_t* noalias sret(%struct.uint32x4x3_t) align 8 [[RETVAL:%.*]],
1262 // CHECK: [[__RET:%.*]] = alloca %struct.uint32x4x3_t, align {{16|8}} 1262 // CHECK: [[__RET:%.*]] = alloca %struct.uint32x4x3_t, align {{16|8}}
1263 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint32x4x3_t* [[__RET]] to i8* 1263 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint32x4x3_t* [[__RET]] to i8*
1264 // CHECK: [[TMP1:%.*]] = bitcast i32* %a to i8* 1264 // CHECK: [[TMP1:%.*]] = bitcast i32* %a to i8*
1265 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32* 1265 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32*
1266 // CHECK: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v4i32.p0i32(i32* [[TMP2]]) 1266 // CHECK: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v4i32.p0i32(i32* [[TMP2]])
1276 return vld1q_u32_x3(a); 1276 return vld1q_u32_x3(a);
1277 } 1277 }
1278 1278
1279 // CHECK-LABEL: @test_vld1q_u32_x4( 1279 // CHECK-LABEL: @test_vld1q_u32_x4(
1280 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint32x4x4_t, align 16 1280 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint32x4x4_t, align 16
1281 // CHECK-A32: %struct.uint32x4x4_t* noalias sret align 8 [[RETVAL:%.*]], 1281 // CHECK-A32: %struct.uint32x4x4_t* noalias sret(%struct.uint32x4x4_t) align 8 [[RETVAL:%.*]],
1282 // CHECK: [[__RET:%.*]] = alloca %struct.uint32x4x4_t, align {{16|8}} 1282 // CHECK: [[__RET:%.*]] = alloca %struct.uint32x4x4_t, align {{16|8}}
1283 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint32x4x4_t* [[__RET]] to i8* 1283 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint32x4x4_t* [[__RET]] to i8*
1284 // CHECK: [[TMP1:%.*]] = bitcast i32* %a to i8* 1284 // CHECK: [[TMP1:%.*]] = bitcast i32* %a to i8*
1285 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32* 1285 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32*
1286 // CHECK: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v4i32.p0i32(i32* [[TMP2]]) 1286 // CHECK: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v4i32.p0i32(i32* [[TMP2]])
1296 return vld1q_u32_x4(a); 1296 return vld1q_u32_x4(a);
1297 } 1297 }
1298 1298
1299 // CHECK-LABEL: @test_vld1q_u64_x2( 1299 // CHECK-LABEL: @test_vld1q_u64_x2(
1300 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint64x2x2_t, align 16 1300 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint64x2x2_t, align 16
1301 // CHECK-A32: %struct.uint64x2x2_t* noalias sret align 8 [[RETVAL:%.*]], 1301 // CHECK-A32: %struct.uint64x2x2_t* noalias sret(%struct.uint64x2x2_t) align 8 [[RETVAL:%.*]],
1302 // CHECK: [[__RET:%.*]] = alloca %struct.uint64x2x2_t, align {{16|8}} 1302 // CHECK: [[__RET:%.*]] = alloca %struct.uint64x2x2_t, align {{16|8}}
1303 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint64x2x2_t* [[__RET]] to i8* 1303 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint64x2x2_t* [[__RET]] to i8*
1304 // CHECK: [[TMP1:%.*]] = bitcast i64* %a to i8* 1304 // CHECK: [[TMP1:%.*]] = bitcast i64* %a to i8*
1305 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i64* 1305 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i64*
1306 // CHECK: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v2i64.p0i64(i64* [[TMP2]]) 1306 // CHECK: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v2i64.p0i64(i64* [[TMP2]])
1316 return vld1q_u64_x2(a); 1316 return vld1q_u64_x2(a);
1317 } 1317 }
1318 1318
1319 // CHECK-LABEL: @test_vld1q_u64_x3( 1319 // CHECK-LABEL: @test_vld1q_u64_x3(
1320 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint64x2x3_t, align 16 1320 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint64x2x3_t, align 16
1321 // CHECK-A32: %struct.uint64x2x3_t* noalias sret align 8 [[RETVAL:%.*]], 1321 // CHECK-A32: %struct.uint64x2x3_t* noalias sret(%struct.uint64x2x3_t) align 8 [[RETVAL:%.*]],
1322 // CHECK: [[__RET:%.*]] = alloca %struct.uint64x2x3_t, align {{16|8}} 1322 // CHECK: [[__RET:%.*]] = alloca %struct.uint64x2x3_t, align {{16|8}}
1323 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint64x2x3_t* [[__RET]] to i8* 1323 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint64x2x3_t* [[__RET]] to i8*
1324 // CHECK: [[TMP1:%.*]] = bitcast i64* %a to i8* 1324 // CHECK: [[TMP1:%.*]] = bitcast i64* %a to i8*
1325 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i64* 1325 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i64*
1326 // CHECK: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v2i64.p0i64(i64* [[TMP2]]) 1326 // CHECK: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v2i64.p0i64(i64* [[TMP2]])
1336 return vld1q_u64_x3(a); 1336 return vld1q_u64_x3(a);
1337 } 1337 }
1338 1338
1339 // CHECK-LABEL: @test_vld1q_u64_x4( 1339 // CHECK-LABEL: @test_vld1q_u64_x4(
1340 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint64x2x4_t, align 16 1340 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint64x2x4_t, align 16
1341 // CHECK-A32: %struct.uint64x2x4_t* noalias sret align 8 [[RETVAL:%.*]], 1341 // CHECK-A32: %struct.uint64x2x4_t* noalias sret(%struct.uint64x2x4_t) align 8 [[RETVAL:%.*]],
1342 // CHECK: [[__RET:%.*]] = alloca %struct.uint64x2x4_t, align {{16|8}} 1342 // CHECK: [[__RET:%.*]] = alloca %struct.uint64x2x4_t, align {{16|8}}
1343 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint64x2x4_t* [[__RET]] to i8* 1343 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint64x2x4_t* [[__RET]] to i8*
1344 // CHECK: [[TMP1:%.*]] = bitcast i64* %a to i8* 1344 // CHECK: [[TMP1:%.*]] = bitcast i64* %a to i8*
1345 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i64* 1345 // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i64*
1346 // CHECK: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v2i64.p0i64(i64* [[TMP2]]) 1346 // CHECK: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v2i64.p0i64(i64* [[TMP2]])
1356 return vld1q_u64_x4(a); 1356 return vld1q_u64_x4(a);
1357 } 1357 }
1358 1358
1359 // CHECK-LABEL: @test_vld1q_u8_x2( 1359 // CHECK-LABEL: @test_vld1q_u8_x2(
1360 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint8x16x2_t, align 16 1360 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint8x16x2_t, align 16
1361 // CHECK-A32: %struct.uint8x16x2_t* noalias sret align 8 [[RETVAL:%.*]], 1361 // CHECK-A32: %struct.uint8x16x2_t* noalias sret(%struct.uint8x16x2_t) align 8 [[RETVAL:%.*]],
1362 // CHECK: [[__RET:%.*]] = alloca %struct.uint8x16x2_t, align {{16|8}} 1362 // CHECK: [[__RET:%.*]] = alloca %struct.uint8x16x2_t, align {{16|8}}
1363 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint8x16x2_t* [[__RET]] to i8* 1363 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint8x16x2_t* [[__RET]] to i8*
1364 // CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v16i8.p0i8(i8* %a) 1364 // CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v16i8.p0i8(i8* %a)
1365 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <16 x i8>, <16 x i8> }* 1365 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <16 x i8>, <16 x i8> }*
1366 // CHECK: store { <16 x i8>, <16 x i8> } [[VLD1XN]], { <16 x i8>, <16 x i8> }* [[TMP1]] 1366 // CHECK: store { <16 x i8>, <16 x i8> } [[VLD1XN]], { <16 x i8>, <16 x i8> }* [[TMP1]]
1374 return vld1q_u8_x2(a); 1374 return vld1q_u8_x2(a);
1375 } 1375 }
1376 1376
1377 // CHECK-LABEL: @test_vld1q_u8_x3( 1377 // CHECK-LABEL: @test_vld1q_u8_x3(
1378 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint8x16x3_t, align 16 1378 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint8x16x3_t, align 16
1379 // CHECK-A32: %struct.uint8x16x3_t* noalias sret align 8 [[RETVAL:%.*]], 1379 // CHECK-A32: %struct.uint8x16x3_t* noalias sret(%struct.uint8x16x3_t) align 8 [[RETVAL:%.*]],
1380 // CHECK: [[__RET:%.*]] = alloca %struct.uint8x16x3_t, align {{16|8}} 1380 // CHECK: [[__RET:%.*]] = alloca %struct.uint8x16x3_t, align {{16|8}}
1381 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint8x16x3_t* [[__RET]] to i8* 1381 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint8x16x3_t* [[__RET]] to i8*
1382 // CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v16i8.p0i8(i8* %a) 1382 // CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v16i8.p0i8(i8* %a)
1383 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <16 x i8>, <16 x i8>, <16 x i8> }* 1383 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <16 x i8>, <16 x i8>, <16 x i8> }*
1384 // CHECK: store { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], { <16 x i8>, <16 x i8>, <16 x i8> }* [[TMP1]] 1384 // CHECK: store { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], { <16 x i8>, <16 x i8>, <16 x i8> }* [[TMP1]]
1392 return vld1q_u8_x3(a); 1392 return vld1q_u8_x3(a);
1393 } 1393 }
1394 1394
1395 // CHECK-LABEL: @test_vld1q_u8_x4( 1395 // CHECK-LABEL: @test_vld1q_u8_x4(
1396 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint8x16x4_t, align 16 1396 // CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint8x16x4_t, align 16
1397 // CHECK-A32: %struct.uint8x16x4_t* noalias sret align 8 [[RETVAL:%.*]], 1397 // CHECK-A32: %struct.uint8x16x4_t* noalias sret(%struct.uint8x16x4_t) align 8 [[RETVAL:%.*]],
1398 // CHECK: [[__RET:%.*]] = alloca %struct.uint8x16x4_t, align {{16|8}} 1398 // CHECK: [[__RET:%.*]] = alloca %struct.uint8x16x4_t, align {{16|8}}
1399 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint8x16x4_t* [[__RET]] to i8* 1399 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint8x16x4_t* [[__RET]] to i8*
1400 // CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v16i8.p0i8(i8* %a) 1400 // CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v16i8.p0i8(i8* %a)
1401 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> }* 1401 // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> }*
1402 // CHECK: store { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> }* [[TMP1]] 1402 // CHECK: store { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> }* [[TMP1]]