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comparison clang/test/CodeGen/arm64_vdupq_n_f64.c @ 207:2e18cbf3894f

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LLVM12
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Tue, 08 Jun 2021 06:07:14 +0900
parents 0572611fdcc8
children c4bab56944e8
comparison
equal deleted inserted replaced
173:0572611fdcc8 207:2e18cbf3894f
2 2
3 #include <arm_neon.h> 3 #include <arm_neon.h>
4 4
5 // vdupq_n_f64 -> dup.2d v0, v0[0] 5 // vdupq_n_f64 -> dup.2d v0, v0[0]
6 // 6 //
7 // CHECK-LABEL: define <2 x double> @test_vdupq_n_f64(double %w) #0 { 7 // CHECK-LABEL: define{{.*}} <2 x double> @test_vdupq_n_f64(double %w) #0 {
8 // CHECK: [[VECINIT_I:%.*]] = insertelement <2 x double> undef, double %w, i32 0 8 // CHECK: [[VECINIT_I:%.*]] = insertelement <2 x double> undef, double %w, i32 0
9 // CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double %w, i32 1 9 // CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double %w, i32 1
10 // CHECK: ret <2 x double> [[VECINIT1_I]] 10 // CHECK: ret <2 x double> [[VECINIT1_I]]
11 float64x2_t test_vdupq_n_f64(float64_t w) { 11 float64x2_t test_vdupq_n_f64(float64_t w) {
12 return vdupq_n_f64(w); 12 return vdupq_n_f64(w);
13 } 13 }
14 14
15 // might as well test this while we're here 15 // might as well test this while we're here
16 // vdupq_n_f32 -> dup.4s v0, v0[0] 16 // vdupq_n_f32 -> dup.4s v0, v0[0]
17 // CHECK-LABEL: define <4 x float> @test_vdupq_n_f32(float %w) #0 { 17 // CHECK-LABEL: define{{.*}} <4 x float> @test_vdupq_n_f32(float %w) #0 {
18 // CHECK: [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %w, i32 0 18 // CHECK: [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %w, i32 0
19 // CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float %w, i32 1 19 // CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float %w, i32 1
20 // CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float %w, i32 2 20 // CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float %w, i32 2
21 // CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x float> [[VECINIT2_I]], float %w, i32 3 21 // CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x float> [[VECINIT2_I]], float %w, i32 3
22 // CHECK: ret <4 x float> [[VECINIT3_I]] 22 // CHECK: ret <4 x float> [[VECINIT3_I]]
25 } 25 }
26 26
27 // vdupq_lane_f64 -> dup.2d v0, v0[0] 27 // vdupq_lane_f64 -> dup.2d v0, v0[0]
28 // this was in <rdar://problem/11778405>, but had already been implemented, 28 // this was in <rdar://problem/11778405>, but had already been implemented,
29 // test anyway 29 // test anyway
30 // CHECK-LABEL: define <2 x double> @test_vdupq_lane_f64(<1 x double> %V) #0 { 30 // CHECK-LABEL: define{{.*}} <2 x double> @test_vdupq_lane_f64(<1 x double> %V) #0 {
31 // CHECK: [[TMP0:%.*]] = bitcast <1 x double> %V to <8 x i8> 31 // CHECK: [[TMP0:%.*]] = bitcast <1 x double> %V to <8 x i8>
32 // CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x double> 32 // CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x double>
33 // CHECK: [[SHUFFLE:%.*]] = shufflevector <1 x double> [[TMP1]], <1 x double> [[TMP1]], <2 x i32> zeroinitializer 33 // CHECK: [[SHUFFLE:%.*]] = shufflevector <1 x double> [[TMP1]], <1 x double> [[TMP1]], <2 x i32> zeroinitializer
34 // CHECK: ret <2 x double> [[SHUFFLE]] 34 // CHECK: ret <2 x double> [[SHUFFLE]]
35 float64x2_t test_vdupq_lane_f64(float64x1_t V) { 35 float64x2_t test_vdupq_lane_f64(float64x1_t V) {
36 return vdupq_lane_f64(V, 0); 36 return vdupq_lane_f64(V, 0);
37 } 37 }
38 38
39 // vmovq_n_f64 -> dup Vd.2d,X0 39 // vmovq_n_f64 -> dup Vd.2d,X0
40 // this wasn't in <rdar://problem/11778405>, but it was between the vdups 40 // this wasn't in <rdar://problem/11778405>, but it was between the vdups
41 // CHECK-LABEL: define <2 x double> @test_vmovq_n_f64(double %w) #0 { 41 // CHECK-LABEL: define{{.*}} <2 x double> @test_vmovq_n_f64(double %w) #0 {
42 // CHECK: [[VECINIT_I:%.*]] = insertelement <2 x double> undef, double %w, i32 0 42 // CHECK: [[VECINIT_I:%.*]] = insertelement <2 x double> undef, double %w, i32 0
43 // CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double %w, i32 1 43 // CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double %w, i32 1
44 // CHECK: ret <2 x double> [[VECINIT1_I]] 44 // CHECK: ret <2 x double> [[VECINIT1_I]]
45 float64x2_t test_vmovq_n_f64(float64_t w) { 45 float64x2_t test_vmovq_n_f64(float64_t w) {
46 return vmovq_n_f64(w); 46 return vmovq_n_f64(w);
47 } 47 }
48 48
49 // CHECK-LABEL: define <4 x half> @test_vmov_n_f16(half* %a1) #1 { 49 // CHECK-LABEL: define{{.*}} <4 x half> @test_vmov_n_f16(half* %a1) #1 {
50 // CHECK: [[TMP0:%.*]] = load half, half* %a1, align 2 50 // CHECK: [[TMP0:%.*]] = load half, half* %a1, align 2
51 // CHECK: [[VECINIT:%.*]] = insertelement <4 x half> undef, half [[TMP0]], i32 0 51 // CHECK: [[VECINIT:%.*]] = insertelement <4 x half> undef, half [[TMP0]], i32 0
52 // CHECK: [[VECINIT1:%.*]] = insertelement <4 x half> [[VECINIT]], half [[TMP0]], i32 1 52 // CHECK: [[VECINIT1:%.*]] = insertelement <4 x half> [[VECINIT]], half [[TMP0]], i32 1
53 // CHECK: [[VECINIT2:%.*]] = insertelement <4 x half> [[VECINIT1]], half [[TMP0]], i32 2 53 // CHECK: [[VECINIT2:%.*]] = insertelement <4 x half> [[VECINIT1]], half [[TMP0]], i32 2
54 // CHECK: [[VECINIT3:%.*]] = insertelement <4 x half> [[VECINIT2]], half [[TMP0]], i32 3 54 // CHECK: [[VECINIT3:%.*]] = insertelement <4 x half> [[VECINIT2]], half [[TMP0]], i32 3
61 float64x1_t test_vmov_n_f64(float64_t a1) { 61 float64x1_t test_vmov_n_f64(float64_t a1) {
62 return vmov_n_f64(a1); 62 return vmov_n_f64(a1);
63 } 63 }
64 */ 64 */
65 65
66 // CHECK-LABEL: define <8 x half> @test_vmovq_n_f16(half* %a1) #0 { 66 // CHECK-LABEL: define{{.*}} <8 x half> @test_vmovq_n_f16(half* %a1) #0 {
67 // CHECK: [[TMP0:%.*]] = load half, half* %a1, align 2 67 // CHECK: [[TMP0:%.*]] = load half, half* %a1, align 2
68 // CHECK: [[VECINIT:%.*]] = insertelement <8 x half> undef, half [[TMP0]], i32 0 68 // CHECK: [[VECINIT:%.*]] = insertelement <8 x half> undef, half [[TMP0]], i32 0
69 // CHECK: [[VECINIT1:%.*]] = insertelement <8 x half> [[VECINIT]], half [[TMP0]], i32 1 69 // CHECK: [[VECINIT1:%.*]] = insertelement <8 x half> [[VECINIT]], half [[TMP0]], i32 1
70 // CHECK: [[VECINIT2:%.*]] = insertelement <8 x half> [[VECINIT1]], half [[TMP0]], i32 2 70 // CHECK: [[VECINIT2:%.*]] = insertelement <8 x half> [[VECINIT1]], half [[TMP0]], i32 2
71 // CHECK: [[VECINIT3:%.*]] = insertelement <8 x half> [[VECINIT2]], half [[TMP0]], i32 3 71 // CHECK: [[VECINIT3:%.*]] = insertelement <8 x half> [[VECINIT2]], half [[TMP0]], i32 3