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comparison llvm/test/CodeGen/AMDGPU/dagcombine-select.ll @ 207:2e18cbf3894f

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LLVM12
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Tue, 08 Jun 2021 06:07:14 +0900
parents 1d019706d866
children c4bab56944e8
comparison
equal deleted inserted replaced
173:0572611fdcc8 207:2e18cbf3894f
1 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s 1 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
2 2
3 ; GCN-LABEL: {{^}}select_and1: 3 ; GCN-LABEL: {{^}}select_and1:
4 ; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], 0, v{{[0-9]+}}, 4 ; GCN: s_cselect_b32 [[SEL:s[0-9]+]], s{{[0-9]+}},
5 ; GCN-NOT: v_and_b32 5 ; GCN: v_mov_b32_e32 [[VSEL:v[0-9]+]], [[SEL]]
6 ; GCN: store_dword v[{{[0-9:]+}}], [[SEL]], 6 ; GCN-NOT: v_and_b32
7 ; GCN: store_dword v{{[0-9]+}}, [[VSEL]], s{{\[[0-9]+:[0-9]+\]}}
7 define amdgpu_kernel void @select_and1(i32 addrspace(1)* %p, i32 %x, i32 %y) { 8 define amdgpu_kernel void @select_and1(i32 addrspace(1)* %p, i32 %x, i32 %y) {
8 %c = icmp slt i32 %x, 11 9 %c = icmp slt i32 %x, 11
9 %s = select i1 %c, i32 0, i32 -1 10 %s = select i1 %c, i32 0, i32 -1
10 %a = and i32 %y, %s 11 %a = and i32 %y, %s
11 store i32 %a, i32 addrspace(1)* %p, align 4 12 store i32 %a, i32 addrspace(1)* %p, align 4
12 ret void 13 ret void
13 } 14 }
14 15
15 ; GCN-LABEL: {{^}}select_and2: 16 ; GCN-LABEL: {{^}}select_and2:
16 ; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], 0, v{{[0-9]+}}, 17 ; GCN: s_cselect_b32 [[SEL:s[0-9]+]], s{{[0-9]+}},
17 ; GCN-NOT: v_and_b32 18 ; GCN: v_mov_b32_e32 [[VSEL:v[0-9]+]], [[SEL]]
18 ; GCN: store_dword v[{{[0-9:]+}}], [[SEL]], 19 ; GCN-NOT: v_and_b32
20 ; GCN: store_dword v{{[0-9]+}}, [[VSEL]], s{{\[[0-9]+:[0-9]+\]}}
19 define amdgpu_kernel void @select_and2(i32 addrspace(1)* %p, i32 %x, i32 %y) { 21 define amdgpu_kernel void @select_and2(i32 addrspace(1)* %p, i32 %x, i32 %y) {
20 %c = icmp slt i32 %x, 11 22 %c = icmp slt i32 %x, 11
21 %s = select i1 %c, i32 0, i32 -1 23 %s = select i1 %c, i32 0, i32 -1
22 %a = and i32 %s, %y 24 %a = and i32 %s, %y
23 store i32 %a, i32 addrspace(1)* %p, align 4 25 store i32 %a, i32 addrspace(1)* %p, align 4
24 ret void 26 ret void
25 } 27 }
26 28
27 ; GCN-LABEL: {{^}}select_and3: 29 ; GCN-LABEL: {{^}}select_and3:
28 ; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], 0, v{{[0-9]+}}, 30 ; GCN: s_cselect_b32 [[SEL:s[0-9]+]], s{{[0-9]+}},
29 ; GCN-NOT: v_and_b32 31 ; GCN: v_mov_b32_e32 [[VSEL:v[0-9]+]], [[SEL]]
30 ; GCN: store_dword v[{{[0-9:]+}}], [[SEL]], 32 ; GCN-NOT: v_and_b32
33 ; GCN: store_dword v{{[0-9]+}}, [[VSEL]], s{{\[[0-9]+:[0-9]+\]}}
31 define amdgpu_kernel void @select_and3(i32 addrspace(1)* %p, i32 %x, i32 %y) { 34 define amdgpu_kernel void @select_and3(i32 addrspace(1)* %p, i32 %x, i32 %y) {
32 %c = icmp slt i32 %x, 11 35 %c = icmp slt i32 %x, 11
33 %s = select i1 %c, i32 -1, i32 0 36 %s = select i1 %c, i32 -1, i32 0
34 %a = and i32 %y, %s 37 %a = and i32 %y, %s
35 store i32 %a, i32 addrspace(1)* %p, align 4 38 store i32 %a, i32 addrspace(1)* %p, align 4
50 store <4 x i32> %a, <4 x i32> addrspace(1)* %p, align 32 53 store <4 x i32> %a, <4 x i32> addrspace(1)* %p, align 32
51 ret void 54 ret void
52 } 55 }
53 56
54 ; GCN-LABEL: {{^}}select_or1: 57 ; GCN-LABEL: {{^}}select_or1:
55 ; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], -1, v{{[0-9]+}}, 58 ; GCN: s_cselect_b32 [[SEL:s[0-9]+]], s{{[0-9]+}},
56 ; GCN-NOT: v_or_b32 59 ; GCN: v_mov_b32_e32 [[VSEL:v[0-9]+]], [[SEL]]
57 ; GCN: store_dword v[{{[0-9:]+}}], [[SEL]], 60 ; GCN-NOT: v_or_b32
61 ; GCN: store_dword v{{[0-9]+}}, [[VSEL]], s{{\[[0-9]+:[0-9]+\]}}
58 define amdgpu_kernel void @select_or1(i32 addrspace(1)* %p, i32 %x, i32 %y) { 62 define amdgpu_kernel void @select_or1(i32 addrspace(1)* %p, i32 %x, i32 %y) {
59 %c = icmp slt i32 %x, 11 63 %c = icmp slt i32 %x, 11
60 %s = select i1 %c, i32 0, i32 -1 64 %s = select i1 %c, i32 0, i32 -1
61 %a = or i32 %y, %s 65 %a = or i32 %y, %s
62 store i32 %a, i32 addrspace(1)* %p, align 4 66 store i32 %a, i32 addrspace(1)* %p, align 4
63 ret void 67 ret void
64 } 68 }
65 69
66 ; GCN-LABEL: {{^}}select_or2: 70 ; GCN-LABEL: {{^}}select_or2:
67 ; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], -1, v{{[0-9]+}}, 71 ; GCN: s_cselect_b32 [[SEL:s[0-9]+]], s{{[0-9]+}},
68 ; GCN-NOT: v_or_b32 72 ; GCN: v_mov_b32_e32 [[VSEL:v[0-9]+]], [[SEL]]
69 ; GCN: store_dword v[{{[0-9:]+}}], [[SEL]], 73 ; GCN-NOT: v_or_b32
74 ; GCN: store_dword v{{[0-9]+}}, [[VSEL]], s{{\[[0-9]+:[0-9]+\]}}
70 define amdgpu_kernel void @select_or2(i32 addrspace(1)* %p, i32 %x, i32 %y) { 75 define amdgpu_kernel void @select_or2(i32 addrspace(1)* %p, i32 %x, i32 %y) {
71 %c = icmp slt i32 %x, 11 76 %c = icmp slt i32 %x, 11
72 %s = select i1 %c, i32 0, i32 -1 77 %s = select i1 %c, i32 0, i32 -1
73 %a = or i32 %s, %y 78 %a = or i32 %s, %y
74 store i32 %a, i32 addrspace(1)* %p, align 4 79 store i32 %a, i32 addrspace(1)* %p, align 4
75 ret void 80 ret void
76 } 81 }
77 82
78 ; GCN-LABEL: {{^}}select_or3: 83 ; GCN-LABEL: {{^}}select_or3:
79 ; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], -1, v{{[0-9]+}}, 84 ; GCN: s_cselect_b32 [[SEL:s[0-9]+]], s{{[0-9]+}},
80 ; GCN-NOT: v_or_b32 85 ; GCN: v_mov_b32_e32 [[VSEL:v[0-9]+]], [[SEL]]
81 ; GCN: store_dword v[{{[0-9:]+}}], [[SEL]], 86 ; GCN-NOT: v_or_b32
87 ; GCN: store_dword v{{[0-9]+}}, [[VSEL]], s{{\[[0-9]+:[0-9]+\]}}
82 define amdgpu_kernel void @select_or3(i32 addrspace(1)* %p, i32 %x, i32 %y) { 88 define amdgpu_kernel void @select_or3(i32 addrspace(1)* %p, i32 %x, i32 %y) {
83 %c = icmp slt i32 %x, 11 89 %c = icmp slt i32 %x, 11
84 %s = select i1 %c, i32 -1, i32 0 90 %s = select i1 %c, i32 -1, i32 0
85 %a = or i32 %y, %s 91 %a = or i32 %y, %s
86 store i32 %a, i32 addrspace(1)* %p, align 4 92 store i32 %a, i32 addrspace(1)* %p, align 4
101 store <4 x i32> %a, <4 x i32> addrspace(1)* %p, align 32 107 store <4 x i32> %a, <4 x i32> addrspace(1)* %p, align 32
102 ret void 108 ret void
103 } 109 }
104 110
105 ; GCN-LABEL: {{^}}sel_constants_sub_constant_sel_constants: 111 ; GCN-LABEL: {{^}}sel_constants_sub_constant_sel_constants:
106 ; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 2, 9, 112 ; GCN: s_cselect_b32 s{{[0-9]+}}, 9, 2
107 define amdgpu_kernel void @sel_constants_sub_constant_sel_constants(i32 addrspace(1)* %p, i1 %cond) { 113 define amdgpu_kernel void @sel_constants_sub_constant_sel_constants(i32 addrspace(1)* %p, i1 %cond) {
108 %sel = select i1 %cond, i32 -4, i32 3 114 %sel = select i1 %cond, i32 -4, i32 3
109 %bo = sub i32 5, %sel 115 %bo = sub i32 5, %sel
110 store i32 %bo, i32 addrspace(1)* %p, align 4 116 store i32 %bo, i32 addrspace(1)* %p, align 4
111 ret void 117 ret void
112 } 118 }
113 119
114 ; GCN-LABEL: {{^}}sel_constants_sub_constant_sel_constants_i16: 120 ; GCN-LABEL: {{^}}sel_constants_sub_constant_sel_constants_i16:
115 ; GCN: v_cndmask_b32_e64 v2, 2, 9, 121 ; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 2, 9,
116 define amdgpu_kernel void @sel_constants_sub_constant_sel_constants_i16(i16 addrspace(1)* %p, i1 %cond) { 122 define amdgpu_kernel void @sel_constants_sub_constant_sel_constants_i16(i16 addrspace(1)* %p, i1 %cond) {
117 %sel = select i1 %cond, i16 -4, i16 3 123 %sel = select i1 %cond, i16 -4, i16 3
118 %bo = sub i16 5, %sel 124 %bo = sub i16 5, %sel
119 store i16 %bo, i16 addrspace(1)* %p, align 2 125 store i16 %bo, i16 addrspace(1)* %p, align 2
120 ret void 126 ret void
129 store i16 %bo, i16 addrspace(1)* %p, align 2 135 store i16 %bo, i16 addrspace(1)* %p, align 2
130 ret void 136 ret void
131 } 137 }
132 138
133 ; GCN-LABEL: {{^}}sel_constants_sub_constant_sel_constants_v2i16: 139 ; GCN-LABEL: {{^}}sel_constants_sub_constant_sel_constants_v2i16:
134 ; GCN-DAG: v_mov_b32_e32 [[F:v[0-9]+]], 0x60002 140 ; GCN-DAG: s_mov_b32 [[T:s[0-9]+]], 0x50009
135 ; GCN-DAG: v_mov_b32_e32 [[T:v[0-9]+]], 0x50009 141 ; GCN: s_cselect_b32 s{{[0-9]+}}, [[T]], 0x60002
136 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, [[F]], [[T]],
137 define amdgpu_kernel void @sel_constants_sub_constant_sel_constants_v2i16(<2 x i16> addrspace(1)* %p, i1 %cond) { 142 define amdgpu_kernel void @sel_constants_sub_constant_sel_constants_v2i16(<2 x i16> addrspace(1)* %p, i1 %cond) {
138 %sel = select i1 %cond, <2 x i16> <i16 -4, i16 2>, <2 x i16> <i16 3, i16 1> 143 %sel = select i1 %cond, <2 x i16> <i16 -4, i16 2>, <2 x i16> <i16 3, i16 1>
139 %bo = sub <2 x i16> <i16 5, i16 7>, %sel 144 %bo = sub <2 x i16> <i16 5, i16 7>, %sel
140 store <2 x i16> %bo, <2 x i16> addrspace(1)* %p, align 4 145 store <2 x i16> %bo, <2 x i16> addrspace(1)* %p, align 4
141 ret void 146 ret void
152 store <4 x i32> %bo, <4 x i32> addrspace(1)* %p, align 32 157 store <4 x i32> %bo, <4 x i32> addrspace(1)* %p, align 32
153 ret void 158 ret void
154 } 159 }
155 160
156 ; GCN-LABEL: {{^}}sdiv_constant_sel_constants_i64: 161 ; GCN-LABEL: {{^}}sdiv_constant_sel_constants_i64:
157 ; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 5, 0, 162 ; GCN: s_cselect_b32 s{{[0-9]+}}, 0, 5
158 define amdgpu_kernel void @sdiv_constant_sel_constants_i64(i64 addrspace(1)* %p, i1 %cond) { 163 define amdgpu_kernel void @sdiv_constant_sel_constants_i64(i64 addrspace(1)* %p, i1 %cond) {
159 %sel = select i1 %cond, i64 121, i64 23 164 %sel = select i1 %cond, i64 121, i64 23
160 %bo = sdiv i64 120, %sel 165 %bo = sdiv i64 120, %sel
161 store i64 %bo, i64 addrspace(1)* %p, align 8 166 store i64 %bo, i64 addrspace(1)* %p, align 8
162 ret void 167 ret void
163 } 168 }
164 169
165 ; GCN-LABEL: {{^}}sdiv_constant_sel_constants_i32: 170 ; GCN-LABEL: {{^}}sdiv_constant_sel_constants_i32:
166 ; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 8, 26, 171 ; GCN: s_cselect_b32 s{{[0-9]+}}, 26, 8
167 define amdgpu_kernel void @sdiv_constant_sel_constants_i32(i32 addrspace(1)* %p, i1 %cond) { 172 define amdgpu_kernel void @sdiv_constant_sel_constants_i32(i32 addrspace(1)* %p, i1 %cond) {
168 %sel = select i1 %cond, i32 7, i32 23 173 %sel = select i1 %cond, i32 7, i32 23
169 %bo = sdiv i32 184, %sel 174 %bo = sdiv i32 184, %sel
170 store i32 %bo, i32 addrspace(1)* %p, align 8 175 store i32 %bo, i32 addrspace(1)* %p, align 8
171 ret void 176 ret void
172 } 177 }
173 178
174 ; GCN-LABEL: {{^}}udiv_constant_sel_constants_i64: 179 ; GCN-LABEL: {{^}}udiv_constant_sel_constants_i64:
175 ; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 5, 0, 180 ; GCN: s_cselect_b32 s{{[0-9]+}}, 0, 5
176 define amdgpu_kernel void @udiv_constant_sel_constants_i64(i64 addrspace(1)* %p, i1 %cond) { 181 define amdgpu_kernel void @udiv_constant_sel_constants_i64(i64 addrspace(1)* %p, i1 %cond) {
177 %sel = select i1 %cond, i64 -4, i64 23 182 %sel = select i1 %cond, i64 -4, i64 23
178 %bo = udiv i64 120, %sel 183 %bo = udiv i64 120, %sel
179 store i64 %bo, i64 addrspace(1)* %p, align 8 184 store i64 %bo, i64 addrspace(1)* %p, align 8
180 ret void 185 ret void
181 } 186 }
182 187
183 ; GCN-LABEL: {{^}}srem_constant_sel_constants: 188 ; GCN-LABEL: {{^}}srem_constant_sel_constants:
184 ; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 3, 33, 189 ; GCN: s_cselect_b32 s{{[0-9]+}}, 33, 3
185 define amdgpu_kernel void @srem_constant_sel_constants(i64 addrspace(1)* %p, i1 %cond) { 190 define amdgpu_kernel void @srem_constant_sel_constants(i64 addrspace(1)* %p, i1 %cond) {
186 %sel = select i1 %cond, i64 34, i64 15 191 %sel = select i1 %cond, i64 34, i64 15
187 %bo = srem i64 33, %sel 192 %bo = srem i64 33, %sel
188 store i64 %bo, i64 addrspace(1)* %p, align 8 193 store i64 %bo, i64 addrspace(1)* %p, align 8
189 ret void 194 ret void
190 } 195 }
191 196
192 ; GCN-LABEL: {{^}}urem_constant_sel_constants: 197 ; GCN-LABEL: {{^}}urem_constant_sel_constants:
193 ; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 3, 33, 198 ; GCN: s_cselect_b32 s{{[0-9]+}}, 33, 3
194 define amdgpu_kernel void @urem_constant_sel_constants(i64 addrspace(1)* %p, i1 %cond) { 199 define amdgpu_kernel void @urem_constant_sel_constants(i64 addrspace(1)* %p, i1 %cond) {
195 %sel = select i1 %cond, i64 34, i64 15 200 %sel = select i1 %cond, i64 34, i64 15
196 %bo = urem i64 33, %sel 201 %bo = urem i64 33, %sel
197 store i64 %bo, i64 addrspace(1)* %p, align 8 202 store i64 %bo, i64 addrspace(1)* %p, align 8
198 ret void 203 ret void
199 } 204 }
200 205
201 ; GCN-LABEL: {{^}}shl_constant_sel_constants: 206 ; GCN-LABEL: {{^}}shl_constant_sel_constants:
202 ; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 8, 4, 207 ; GCN: s_cselect_b32 s{{[0-9]+}}, 4, 8
203 define amdgpu_kernel void @shl_constant_sel_constants(i32 addrspace(1)* %p, i1 %cond) { 208 define amdgpu_kernel void @shl_constant_sel_constants(i32 addrspace(1)* %p, i1 %cond) {
204 %sel = select i1 %cond, i32 2, i32 3 209 %sel = select i1 %cond, i32 2, i32 3
205 %bo = shl i32 1, %sel 210 %bo = shl i32 1, %sel
206 store i32 %bo, i32 addrspace(1)* %p, align 4 211 store i32 %bo, i32 addrspace(1)* %p, align 4
207 ret void 212 ret void
208 } 213 }
209 214
210 ; GCN-LABEL: {{^}}lshr_constant_sel_constants: 215 ; GCN-LABEL: {{^}}lshr_constant_sel_constants:
211 ; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 8, 16, 216 ; GCN: s_cselect_b32 s{{[0-9]+}}, 16, 8
212 define amdgpu_kernel void @lshr_constant_sel_constants(i32 addrspace(1)* %p, i1 %cond) { 217 define amdgpu_kernel void @lshr_constant_sel_constants(i32 addrspace(1)* %p, i1 %cond) {
213 %sel = select i1 %cond, i32 2, i32 3 218 %sel = select i1 %cond, i32 2, i32 3
214 %bo = lshr i32 64, %sel 219 %bo = lshr i32 64, %sel
215 store i32 %bo, i32 addrspace(1)* %p, align 4 220 store i32 %bo, i32 addrspace(1)* %p, align 4
216 ret void 221 ret void
217 } 222 }
218 223
219 ; GCN-LABEL: {{^}}ashr_constant_sel_constants: 224 ; GCN-LABEL: {{^}}ashr_constant_sel_constants:
220 ; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 16, 32, 225 ; GCN: s_cselect_b32 s{{[0-9]+}}, 32, 16
221 define amdgpu_kernel void @ashr_constant_sel_constants(i32 addrspace(1)* %p, i1 %cond) { 226 define amdgpu_kernel void @ashr_constant_sel_constants(i32 addrspace(1)* %p, i1 %cond) {
222 %sel = select i1 %cond, i32 2, i32 3 227 %sel = select i1 %cond, i32 2, i32 3
223 %bo = ashr i32 128, %sel 228 %bo = ashr i32 128, %sel
224 store i32 %bo, i32 addrspace(1)* %p, align 4 229 store i32 %bo, i32 addrspace(1)* %p, align 4
225 ret void 230 ret void
245 store half %bo, half addrspace(1)* %p, align 2 250 store half %bo, half addrspace(1)* %p, align 2
246 ret void 251 ret void
247 } 252 }
248 253
249 ; GCN-LABEL: {{^}}fsub_constant_sel_constants_v2f16: 254 ; GCN-LABEL: {{^}}fsub_constant_sel_constants_v2f16:
250 ; GCN-DAG: v_mov_b32_e32 [[T:v[0-9]+]], 0x45003c00 255 ; GCN: s_cselect_b32 s{{[0-9]+}}, 0x45003c00, -2.0
251 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, -2.0, [[T]],
252 define amdgpu_kernel void @fsub_constant_sel_constants_v2f16(<2 x half> addrspace(1)* %p, i1 %cond) { 256 define amdgpu_kernel void @fsub_constant_sel_constants_v2f16(<2 x half> addrspace(1)* %p, i1 %cond) {
253 %sel = select i1 %cond, <2 x half> <half -2.0, half -3.0>, <2 x half> <half -1.0, half 4.0> 257 %sel = select i1 %cond, <2 x half> <half -2.0, half -3.0>, <2 x half> <half -1.0, half 4.0>
254 %bo = fsub <2 x half> <half -1.0, half 2.0>, %sel 258 %bo = fsub <2 x half> <half -1.0, half 2.0>, %sel
255 store <2 x half> %bo, <2 x half> addrspace(1)* %p, align 4 259 store <2 x half> %bo, <2 x half> addrspace(1)* %p, align 4
256 ret void 260 ret void