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comparison llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir @ 207:2e18cbf3894f

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LLVM12
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Tue, 08 Jun 2021 06:07:14 +0900
parents 0572611fdcc8
children 5f17cb93ff66
comparison
equal deleted inserted replaced
173:0572611fdcc8 207:2e18cbf3894f
25 ; CHECK: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 0, [[V_MOV_B32_e32_]], implicit $exec 25 ; CHECK: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 0, [[V_MOV_B32_e32_]], implicit $exec
26 ; CHECK: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec 26 ; CHECK: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
27 ; CHECK: [[COPY:%[0-9]+]]:vreg_512 = COPY %0 27 ; CHECK: [[COPY:%[0-9]+]]:vreg_512 = COPY %0
28 ; CHECK: bb.1: 28 ; CHECK: bb.1:
29 ; CHECK: successors: %bb.1(0x80000000) 29 ; CHECK: successors: %bb.1(0x80000000)
30 ; CHECK: BUFFER_STORE_DWORD_OFFEN %0.sub3, undef %5:vgpr_32, $sgpr24_sgpr25_sgpr26_sgpr27, $sgpr32, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4, align 8, addrspace 5) 30 ; CHECK: BUFFER_STORE_DWORD_OFFEN %0.sub3, undef %5:vgpr_32, $sgpr24_sgpr25_sgpr26_sgpr27, $sgpr32, 0, 0, 0, 0, implicit $exec :: (store 4, align 8, addrspace 5)
31 ; CHECK: dead %6:vgpr_32 = DS_READ_B32_gfx9 undef %7:vgpr_32, 0, 0, implicit $exec 31 ; CHECK: dead %6:vgpr_32 = DS_READ_B32_gfx9 undef %7:vgpr_32, 0, 0, implicit $exec
32 ; CHECK: dead %8:vreg_64 = DS_READ_B64_gfx9 [[V_MOV_B32_e32_]], 0, 0, implicit $exec 32 ; CHECK: dead %8:vreg_64 = DS_READ_B64_gfx9 [[V_MOV_B32_e32_]], 0, 0, implicit $exec
33 ; CHECK: dead %9:vreg_128 = DS_READ_B128_gfx9 [[V_ADD_U32_e32_]], 0, 0, implicit $exec 33 ; CHECK: dead %9:vreg_128 = DS_READ_B128_gfx9 [[V_ADD_U32_e32_]], 0, 0, implicit $exec
34 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0 34 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
35 ; CHECK: undef %11.sub1:vreg_512 = COPY [[COPY]].sub1 35 ; CHECK: undef %11.sub1:vreg_512 = COPY [[COPY]].sub1
36 ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VGPR_LO16 */, def dead [[COPY1]], 851978 /* regdef:VGPR_LO16 */, def dead [[COPY]].sub1, 2147483657 /* reguse tiedto:$0 */, [[COPY1]], 2147549193 /* reguse tiedto:$1 */, [[COPY]].sub1 36 ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VGPR_LO16 */, def dead [[COPY1]], 851978 /* regdef:VGPR_LO16 */, def dead [[COPY]].sub1, 2147483657 /* reguse tiedto:$0 */, [[COPY1]], 2147549193 /* reguse tiedto:$1 */, [[COPY]].sub1
37 ; CHECK: %11.sub0:vreg_512 = COPY [[COPY]].sub0 37 ; CHECK: %11.sub0:vreg_512 = COPY [[COPY]].sub0
38 ; CHECK: %11.sub3:vreg_512 = COPY [[COPY]].sub3 38 ; CHECK: %11.sub3:vreg_512 = COPY [[COPY]].sub3
39 ; CHECK: dead %10:vgpr_32 = V_ADD_I32_e32 4, [[V_MOV_B32_e32_1]], implicit-def dead $vcc, implicit $exec
40 ; CHECK: %11.sub2:vreg_512 = COPY undef [[V_MOV_B32_e32_]] 39 ; CHECK: %11.sub2:vreg_512 = COPY undef [[V_MOV_B32_e32_]]
41 ; CHECK: %11.sub5:vreg_512 = COPY undef [[V_MOV_B32_e32_]] 40 ; CHECK: %11.sub5:vreg_512 = COPY undef [[V_MOV_B32_e32_]]
42 ; CHECK: [[COPY2:%[0-9]+]]:vreg_512 = COPY %11 41 ; CHECK: [[COPY2:%[0-9]+]]:vreg_512 = COPY %11
42 ; CHECK: dead %10:vgpr_32 = V_ADD_CO_U32_e32 4, [[V_MOV_B32_e32_1]], implicit-def dead $vcc, implicit $exec
43 ; CHECK: S_BRANCH %bb.1 43 ; CHECK: S_BRANCH %bb.1
44 bb.0: 44 bb.0:
45 liveins: $sgpr6_sgpr7 45 liveins: $sgpr6_sgpr7
46 46
47 undef %0.sub3:vreg_512 = V_MOV_B32_e32 0, implicit $exec 47 undef %0.sub3:vreg_512 = V_MOV_B32_e32 0, implicit $exec
49 %2:vgpr_32 = V_ADD_U32_e32 0, %1, implicit $exec 49 %2:vgpr_32 = V_ADD_U32_e32 0, %1, implicit $exec
50 %3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec 50 %3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
51 %4:vreg_512 = COPY %0 51 %4:vreg_512 = COPY %0
52 52
53 bb.1: 53 bb.1:
54 BUFFER_STORE_DWORD_OFFEN %0.sub3, undef %5:vgpr_32, $sgpr24_sgpr25_sgpr26_sgpr27, $sgpr32, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4, align 8, addrspace 5) 54 BUFFER_STORE_DWORD_OFFEN %0.sub3, undef %5:vgpr_32, $sgpr24_sgpr25_sgpr26_sgpr27, $sgpr32, 0, 0, 0, 0, implicit $exec :: (store 4, align 8, addrspace 5)
55 %6:vgpr_32 = DS_READ_B32_gfx9 undef %7:vgpr_32, 0, 0, implicit $exec 55 %6:vgpr_32 = DS_READ_B32_gfx9 undef %7:vgpr_32, 0, 0, implicit $exec
56 %8:vreg_64 = DS_READ_B64_gfx9 %1, 0, 0, implicit $exec 56 %8:vreg_64 = DS_READ_B64_gfx9 %1, 0, 0, implicit $exec
57 %9:vreg_128 = DS_READ_B128_gfx9 %2, 0, 0, implicit $exec 57 %9:vreg_128 = DS_READ_B128_gfx9 %2, 0, 0, implicit $exec
58 %10:vgpr_32 = V_ADD_I32_e32 4, %3, implicit-def dead $vcc, implicit $exec 58 %10:vgpr_32 = V_ADD_CO_U32_e32 4, %3, implicit-def dead $vcc, implicit $exec
59 undef %11.sub0:vreg_512 = COPY %4.sub0 59 undef %11.sub0:vreg_512 = COPY %4.sub0
60 %12:vgpr_32 = COPY %4.sub0 60 %12:vgpr_32 = COPY %4.sub0
61 %11.sub1:vreg_512 = COPY %4.sub1 61 %11.sub1:vreg_512 = COPY %4.sub1
62 INLINEASM &"", 1, 851978, def dead %12, 851978, def dead %4.sub1, 2147483657, %12, 2147549193, %4.sub1 62 INLINEASM &"", 1, 851978, def dead %12, 851978, def dead %4.sub1, 2147483657, %12, 2147549193, %4.sub1
63 %11.sub2:vreg_512 = COPY undef %1 63 %11.sub2:vreg_512 = COPY undef %1