comparison llvm/test/TableGen/AsmPredicateCombiningRISCV.td @ 207:2e18cbf3894f

LLVM12
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Tue, 08 Jun 2021 06:07:14 +0900
parents 0572611fdcc8
children c4bab56944e8
comparison
equal deleted inserted replaced
173:0572611fdcc8 207:2e18cbf3894f
57 57
58 class CompressPat<dag input, dag output, list<Predicate> predicates> { 58 class CompressPat<dag input, dag output, list<Predicate> predicates> {
59 dag Input = input; 59 dag Input = input;
60 dag Output = output; 60 dag Output = output;
61 list<Predicate> Predicates = predicates; 61 list<Predicate> Predicates = predicates;
62 bit isCompressOnly = false;
62 } 63 }
63 64
64 // COMPRESS-LABEL: static bool compressInst 65 // COMPRESS-LABEL: static bool compressInst
65 // COMPRESS: case arch::BigInst 66 // COMPRESS: case arch::BigInst
66 def SmallInst1 : RVInst16<1, []>; 67 def SmallInst1 : RVInst16<1, []>;