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comparison test/MC/AMDGPU/sopk-err.s @ 122:36195a0db682

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merging ( incomplete )
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Fri, 17 Nov 2017 20:32:31 +0900
parents 803732b1fca8
children 3a76565eade5
comparison
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119:d9df2cbd60cd 122:36195a0db682
1 // RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck -check-prefix=GCN %s
2 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=SI %s
3 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=VI %s
4
5 s_setreg_b32 0x1f803, s2
6 // GCN: error: invalid immediate: only 16-bit values are legal
7
8 s_setreg_b32 hwreg(0x40), s2
9 // GCN: error: invalid code of hardware register: only 6-bit values are legal
10
11 s_setreg_b32 hwreg(HW_REG_WRONG), s2
12 // GCN: error: invalid symbolic name of hardware register
13
14 s_setreg_b32 hwreg(3,32,32), s2
15 // GCN: error: invalid bit offset: only 5-bit values are legal
16
17 s_setreg_b32 hwreg(3,0,33), s2
18 // GCN: error: invalid bitfield width: only values from 1 to 32 are legal
19
20 s_setreg_imm32_b32 0x1f803, 0xff
21 // GCN: error: invalid immediate: only 16-bit values are legal
22
23 s_setreg_imm32_b32 hwreg(3,0,33), 0xff
24 // GCN: error: invalid bitfield width: only values from 1 to 32 are legal
25
26 s_getreg_b32 s2, hwreg(3,32,32)
27 // GCN: error: invalid bit offset: only 5-bit values are legal
28
29 s_cmpk_le_u32 s2, -1
30 // GCN: error: invalid operand for instruction
31
32 s_cmpk_le_u32 s2, 0x1ffff
33 // GCN: error: invalid operand for instruction
34
35 s_cmpk_le_u32 s2, 0x10000
36 // GCN: error: invalid operand for instruction
37
38 s_mulk_i32 s2, 0xFFFFFFFFFFFF0000
39 // GCN: error: invalid operand for instruction
40
41 s_mulk_i32 s2, 0x10000
42 // GCN: error: invalid operand for instruction