CbC/CbC_llvm: lib/CodeGen/MachineLICM.cpp comparison

comparison lib/CodeGen/MachineLICM.cpp @ 134:3a76565eade5 LLVM5.0.1

update 5.0.1

author	mir3636
date	Sat, 17 Feb 2018 09:57:20 +0900
parents	803732b1fca8
children	c2174574ed3a

comparison

equal deleted inserted replaced

-:c60214abe0e8
+:3a76565eade5
 #include "llvm/CodeGen/MachineLoopInfo.h"
 #include "llvm/CodeGen/MachineMemOperand.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/PseudoSourceValue.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/CodeGen/TargetSchedule.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/IR/DebugLoc.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/Pass.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
 #include <algorithm>
 #include <cassert>
 #include <limits>
 #include <vector>
 STATISTIC(NumPostRAHoisted,
 "Number of machine instructions hoisted out of loops post regalloc");
 namespace {
-class MachineLICM : public MachineFunctionPass {
+class MachineLICMBase : public MachineFunctionPass {
 const TargetInstrInfo *TII;
 const TargetLoweringBase *TLI;
 const TargetRegisterInfo *TRI;
 const MachineFrameInfo *MFI;
 MachineRegisterInfo *MRI;
 TargetSchedModel SchedModel;
-bool PreRegAlloc = true;
+bool PreRegAlloc;
 // Various analyses that we use...
 AliasAnalysis        *AA;      // Alias analysis info.
 MachineLoopInfo      *MLI;     // Current MachineLoopInfo
 MachineDominatorTree *DT;      // Machine dominator tree for the cur loop
 // to hoist loads from this block.
 // Tri-state: 0 - false, 1 - true, 2 - unknown
 unsigned SpeculationState;
 public:
-static char ID; // Pass identification, replacement for typeid
+MachineLICMBase(char &PassID, bool PreRegAlloc)
+: MachineFunctionPass(PassID), PreRegAlloc(PreRegAlloc) {}
-MachineLICM() : MachineFunctionPass(ID) {
-initializeMachineLICMPass(*PassRegistry::getPassRegistry());
-}
-explicit MachineLICM(bool PreRA)
-: MachineFunctionPass(ID), PreRegAlloc(PreRA) {
-initializeMachineLICMPass(*PassRegistry::getPassRegistry());
-}
 bool runOnMachineFunction(MachineFunction &MF) override;
 void getAnalysisUsage(AnalysisUsage &AU) const override {
 AU.addRequired<MachineLoopInfo>();
 void InitCSEMap(MachineBasicBlock *BB);
 MachineBasicBlock *getCurPreheader();
 };
+class MachineLICM : public MachineLICMBase {
+public:
+static char ID;
+MachineLICM() : MachineLICMBase(ID, false) {
+initializeMachineLICMPass(*PassRegistry::getPassRegistry());
+}
+};
+class EarlyMachineLICM : public MachineLICMBase {
+public:
+static char ID;
+EarlyMachineLICM() : MachineLICMBase(ID, true) {
+initializeEarlyMachineLICMPass(*PassRegistry::getPassRegistry());
+}
+};
 } // end anonymous namespace
-char MachineLICM::ID = 0;
+char MachineLICM::ID;
+char EarlyMachineLICM::ID;
 char &llvm::MachineLICMID = MachineLICM::ID;
+char &llvm::EarlyMachineLICMID = EarlyMachineLICM::ID;
 INITIALIZE_PASS_BEGIN(MachineLICM, DEBUG_TYPE,
 "Machine Loop Invariant Code Motion", false, false)
 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
 INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
 INITIALIZE_PASS_END(MachineLICM, DEBUG_TYPE,
 "Machine Loop Invariant Code Motion", false, false)
+INITIALIZE_PASS_BEGIN(EarlyMachineLICM, "early-machinelicm",
+"Early Machine Loop Invariant Code Motion", false, false)
+INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
+INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
+INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
+INITIALIZE_PASS_END(EarlyMachineLICM, "early-machinelicm",
+"Early Machine Loop Invariant Code Motion", false, false)
 /// Test if the given loop is the outer-most loop that has a unique predecessor.
 static bool LoopIsOuterMostWithPredecessor(MachineLoop *CurLoop) {
 // Check whether this loop even has a unique predecessor.
 if (!CurLoop->getLoopPredecessor())
 return false;
 // None of them did, so this is the outermost with a unique predecessor.
 return true;
 }
-bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
+bool MachineLICMBase::runOnMachineFunction(MachineFunction &MF) {
-if (skipFunction(*MF.getFunction()))
+if (skipFunction(MF.getFunction()))
 return false;
 Changed = FirstInLoop = false;
 const TargetSubtargetInfo &ST = MF.getSubtarget();
 TII = ST.getInstrInfo();
 return false;
 }
 /// Examine the instruction for potentai LICM candidate. Also
 /// gather register def and frame object update information.
-void MachineLICM::ProcessMI(MachineInstr *MI,
+void MachineLICMBase::ProcessMI(MachineInstr *MI,
 BitVector &PhysRegDefs,
 BitVector &PhysRegClobbers,
 SmallSet<int, 32> &StoredFIs,
 SmallVectorImpl<CandidateInfo> &Candidates) {
 bool RuledOut = false;
 bool HasNonInvariantUse = false;
 unsigned Def = 0;
 for (const MachineOperand &MO : MI->operands()) {
 if (MO.isFI()) {
 }
 }
 /// Walk the specified region of the CFG and hoist loop invariants out to the
 /// preheader.
-void MachineLICM::HoistRegionPostRA() {
+void MachineLICMBase::HoistRegionPostRA() {
 MachineBasicBlock *Preheader = getCurPreheader();
 if (!Preheader)
 return;
 unsigned NumRegs = TRI->getNumRegs();
 }
 }
 /// Add register 'Reg' to the livein sets of BBs in the current loop, and make
 /// sure it is not killed by any instructions in the loop.
-void MachineLICM::AddToLiveIns(unsigned Reg) {
+void MachineLICMBase::AddToLiveIns(unsigned Reg) {
 const std::vector<MachineBasicBlock *> &Blocks = CurLoop->getBlocks();
 for (MachineBasicBlock *BB : Blocks) {
 if (!BB->isLiveIn(Reg))
 BB->addLiveIn(Reg);
 for (MachineInstr &MI : *BB) {
 }
 }
 /// When an instruction is found to only use loop invariant operands that is
 /// safe to hoist, this instruction is called to do the dirty work.
-void MachineLICM::HoistPostRA(MachineInstr *MI, unsigned Def) {
+void MachineLICMBase::HoistPostRA(MachineInstr *MI, unsigned Def) {
 MachineBasicBlock *Preheader = getCurPreheader();
 // Now move the instructions to the predecessor, inserting it before any
 // terminator instructions.
-DEBUG(dbgs() << "Hoisting to BB#" << Preheader->getNumber() << " from BB#"
+DEBUG(dbgs() << "Hoisting to " << printMBBReference(*Preheader) << " from "
-<< MI->getParent()->getNumber() << ": " << *MI);
+<< printMBBReference(*MI->getParent()) << ": " << *MI);
 // Splice the instruction to the preheader.
 MachineBasicBlock *MBB = MI->getParent();
 Preheader->splice(Preheader->getFirstTerminator(), MBB, MI);
 Changed = true;
 }
 /// Check if this mbb is guaranteed to execute. If not then a load from this mbb
 /// may not be safe to hoist.
-bool MachineLICM::IsGuaranteedToExecute(MachineBasicBlock *BB) {
+bool MachineLICMBase::IsGuaranteedToExecute(MachineBasicBlock *BB) {
 if (SpeculationState != SpeculateUnknown)
 return SpeculationState == SpeculateFalse;
 if (BB != CurLoop->getHeader()) {
 // Check loop exiting blocks.
 SpeculationState = SpeculateFalse;
 return true;
 }
-void MachineLICM::EnterScope(MachineBasicBlock *MBB) {
+void MachineLICMBase::EnterScope(MachineBasicBlock *MBB) {
-DEBUG(dbgs() << "Entering BB#" << MBB->getNumber() << '\n');
+DEBUG(dbgs() << "Entering " << printMBBReference(*MBB) << '\n');
 // Remember livein register pressure.
 BackTrace.push_back(RegPressure);
 }
-void MachineLICM::ExitScope(MachineBasicBlock *MBB) {
+void MachineLICMBase::ExitScope(MachineBasicBlock *MBB) {
-DEBUG(dbgs() << "Exiting BB#" << MBB->getNumber() << '\n');
+DEBUG(dbgs() << "Exiting " << printMBBReference(*MBB) << '\n');
 BackTrace.pop_back();
 }
 /// Destroy scope for the MBB that corresponds to the given dominator tree node
 /// if its a leaf or all of its children are done. Walk up the dominator tree to
 /// destroy ancestors which are now done.
-void MachineLICM::ExitScopeIfDone(MachineDomTreeNode *Node,
+void MachineLICMBase::ExitScopeIfDone(MachineDomTreeNode *Node,
 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren,
 DenseMap<MachineDomTreeNode*, MachineDomTreeNode*> &ParentMap) {
 if (OpenChildren[Node])
 return;
 // Pop scope.
 ExitScope(Node->getBlock());
 /// Walk the specified loop in the CFG (defined by all blocks dominated by the
 /// specified header block, and that are in the current loop) in depth first
 /// order w.r.t the DominatorTree. This allows us to visit definitions before
 /// uses, allowing us to hoist a loop body in one pass without iteration.
-void MachineLICM::HoistOutOfLoop(MachineDomTreeNode *HeaderN) {
+void MachineLICMBase::HoistOutOfLoop(MachineDomTreeNode *HeaderN) {
 MachineBasicBlock *Preheader = getCurPreheader();
 if (!Preheader)
 return;
 SmallVector<MachineDomTreeNode*, 32> Scopes;
 }
 /// Sink instructions into loops if profitable. This especially tries to prevent
 /// register spills caused by register pressure if there is little to no
 /// overhead moving instructions into loops.
-void MachineLICM::SinkIntoLoop() {
+void MachineLICMBase::SinkIntoLoop() {
 MachineBasicBlock *Preheader = getCurPreheader();
 if (!Preheader)
 return;
 SmallVector<MachineInstr *, 8> Candidates;
 }
 /// Find all virtual register references that are liveout of the preheader to
 /// initialize the starting "register pressure". Note this does not count live
 /// through (livein but not used) registers.
-void MachineLICM::InitRegPressure(MachineBasicBlock *BB) {
+void MachineLICMBase::InitRegPressure(MachineBasicBlock *BB) {
 std::fill(RegPressure.begin(), RegPressure.end(), 0);
 // If the preheader has only a single predecessor and it ends with a
 // fallthrough or an unconditional branch, then scan its predecessor for live
 // defs as well. This happens whenever the preheader is created by splitting
 for (const MachineInstr &MI : *BB)
 UpdateRegPressure(&MI, /*ConsiderUnseenAsDef=*/true);
 }
 /// Update estimate of register pressure after the specified instruction.
-void MachineLICM::UpdateRegPressure(const MachineInstr *MI,
+void MachineLICMBase::UpdateRegPressure(const MachineInstr *MI,
 bool ConsiderUnseenAsDef) {
 auto Cost = calcRegisterCost(MI, /*ConsiderSeen=*/true, ConsiderUnseenAsDef);
 for (const auto &RPIdAndCost : Cost) {
 unsigned Class = RPIdAndCost.first;
 if (static_cast<int>(RegPressure[Class]) < -RPIdAndCost.second)
 RegPressure[Class] = 0;
 ///
 /// If 'ConsiderSeen' is true, updates 'RegSeen' and uses the information to
 /// figure out which usages are live-ins.
 /// FIXME: Figure out a way to consider 'RegSeen' from all code paths.
 DenseMap<unsigned, int>
-MachineLICM::calcRegisterCost(const MachineInstr *MI, bool ConsiderSeen,
+MachineLICMBase::calcRegisterCost(const MachineInstr *MI, bool ConsiderSeen,
 bool ConsiderUnseenAsDef) {
 DenseMap<unsigned, int> Cost;
 if (MI->isImplicitDef())
 return Cost;
 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
 const MachineOperand &MO = MI->getOperand(i);
 return false;
 }
 /// Returns true if the instruction may be a suitable candidate for LICM.
 /// e.g. If the instruction is a call, then it's obviously not safe to hoist it.
-bool MachineLICM::IsLICMCandidate(MachineInstr &I) {
+bool MachineLICMBase::IsLICMCandidate(MachineInstr &I) {
 // Check if it's safe to move the instruction.
 bool DontMoveAcrossStore = true;
 if (!I.isSafeToMove(AA, DontMoveAcrossStore))
 return false;
 /// Returns true if the instruction is loop invariant.
 /// I.e., all virtual register operands are defined outside of the loop,
 /// physical registers aren't accessed explicitly, and there are no side
 /// effects that aren't captured by the operands or other flags.
-bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
+bool MachineLICMBase::IsLoopInvariantInst(MachineInstr &I) {
 if (!IsLICMCandidate(I))
 return false;
 // The instruction is loop invariant if all of its operands are.
 for (const MachineOperand &MO : I.operands()) {
 return true;
 }
 /// Return true if the specified instruction is used by a phi node and hoisting
 /// it could cause a copy to be inserted.
-bool MachineLICM::HasLoopPHIUse(const MachineInstr *MI) const {
+bool MachineLICMBase::HasLoopPHIUse(const MachineInstr *MI) const {
 SmallVector<const MachineInstr*, 8> Work(1, MI);
 do {
 MI = Work.pop_back_val();
 for (const MachineOperand &MO : MI->operands()) {
 if (!MO.isReg() || !MO.isDef())
 return false;
 }
 /// Compute operand latency between a def of 'Reg' and an use in the current
 /// loop, return true if the target considered it high.
-bool MachineLICM::HasHighOperandLatency(MachineInstr &MI,
+bool MachineLICMBase::HasHighOperandLatency(MachineInstr &MI,
-unsigned DefIdx, unsigned Reg) const {
+unsigned DefIdx,
+unsigned Reg) const {
 if (MRI->use_nodbg_empty(Reg))
 return false;
 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(Reg)) {
 if (UseMI.isCopyLike())
 return false;
 }
 /// Return true if the instruction is marked "cheap" or the operand latency
 /// between its def and a use is one or less.
-bool MachineLICM::IsCheapInstruction(MachineInstr &MI) const {
+bool MachineLICMBase::IsCheapInstruction(MachineInstr &MI) const {
 if (TII->isAsCheapAsAMove(MI) || MI.isCopyLike())
 return true;
 bool isCheap = false;
 unsigned NumDefs = MI.getDesc().getNumDefs();
 return isCheap;
 }
 /// Visit BBs from header to current BB, check if hoisting an instruction of the
 /// given cost matrix can cause high register pressure.
-bool MachineLICM::CanCauseHighRegPressure(const DenseMap<unsigned, int>& Cost,
+bool
-bool CheapInstr) {
+MachineLICMBase::CanCauseHighRegPressure(const DenseMap<unsigned, int>& Cost,
+bool CheapInstr) {
 for (const auto &RPIdAndCost : Cost) {
 if (RPIdAndCost.second <= 0)
 continue;
 unsigned Class = RPIdAndCost.first;
 }
 /// Traverse the back trace from header to the current block and update their
 /// register pressures to reflect the effect of hoisting MI from the current
 /// block to the preheader.
-void MachineLICM::UpdateBackTraceRegPressure(const MachineInstr *MI) {
+void MachineLICMBase::UpdateBackTraceRegPressure(const MachineInstr *MI) {
 // First compute the 'cost' of the instruction, i.e. its contribution
 // to register pressure.
 auto Cost = calcRegisterCost(MI, /*ConsiderSeen=*/false,
 /*ConsiderUnseenAsDef=*/false);
 RP[RPIdAndCost.first] += RPIdAndCost.second;
 }
 /// Return true if it is potentially profitable to hoist the given loop
 /// invariant.
-bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) {
+bool MachineLICMBase::IsProfitableToHoist(MachineInstr &MI) {
 if (MI.isImplicitDef())
 return true;
 // Besides removing computation from the loop, hoisting an instruction has
 // these effects:
 }
 /// Unfold a load from the given machineinstr if the load itself could be
 /// hoisted. Return the unfolded and hoistable load, or null if the load
 /// couldn't be unfolded or if it wouldn't be hoistable.
-MachineInstr *MachineLICM::ExtractHoistableLoad(MachineInstr *MI) {
+MachineInstr *MachineLICMBase::ExtractHoistableLoad(MachineInstr *MI) {
 // Don't unfold simple loads.
 if (MI->canFoldAsLoad())
 return nullptr;
 // If not, we may be able to unfold a load and hoist that.
 }
 /// Initialize the CSE map with instructions that are in the current loop
 /// preheader that may become duplicates of instructions that are hoisted
 /// out of the loop.
-void MachineLICM::InitCSEMap(MachineBasicBlock *BB) {
+void MachineLICMBase::InitCSEMap(MachineBasicBlock *BB) {
 for (MachineInstr &MI : *BB)
 CSEMap[MI.getOpcode()].push_back(&MI);
 }
 /// Find an instruction amount PrevMIs that is a duplicate of MI.
 /// Return this instruction if it's found.
 const MachineInstr*
-MachineLICM::LookForDuplicate(const MachineInstr *MI,
+MachineLICMBase::LookForDuplicate(const MachineInstr *MI,
 std::vector<const MachineInstr*> &PrevMIs) {
 for (const MachineInstr *PrevMI : PrevMIs)
 if (TII->produceSameValue(*MI, *PrevMI, (PreRegAlloc ? MRI : nullptr)))
 return PrevMI;
 return nullptr;
 /// Given a LICM'ed instruction, look for an instruction on the preheader that
 /// computes the same value. If it's found, do a RAU on with the definition of
 /// the existing instruction rather than hoisting the instruction to the
 /// preheader.
-bool MachineLICM::EliminateCSE(MachineInstr *MI,
+bool MachineLICMBase::EliminateCSE(MachineInstr *MI,
 DenseMap<unsigned, std::vector<const MachineInstr *>>::iterator &CI) {
 // Do not CSE implicit_def so ProcessImplicitDefs can properly propagate
 // the undef property onto uses.
 if (CI == CSEMap.end() || MI->isImplicitDef())
 return false;
 return false;
 }
 /// Return true if the given instruction will be CSE'd if it's hoisted out of
 /// the loop.
-bool MachineLICM::MayCSE(MachineInstr *MI) {
+bool MachineLICMBase::MayCSE(MachineInstr *MI) {
 unsigned Opcode = MI->getOpcode();
 DenseMap<unsigned, std::vector<const MachineInstr *>>::iterator
 CI = CSEMap.find(Opcode);
 // Do not CSE implicit_def so ProcessImplicitDefs can properly propagate
 // the undef property onto uses.
 }
 /// When an instruction is found to use only loop invariant operands
 /// that are safe to hoist, this instruction is called to do the dirty work.
 /// It returns true if the instruction is hoisted.
-bool MachineLICM::Hoist(MachineInstr *MI, MachineBasicBlock *Preheader) {
+bool MachineLICMBase::Hoist(MachineInstr *MI, MachineBasicBlock *Preheader) {
 // First check whether we should hoist this instruction.
 if (!IsLoopInvariantInst(*MI) || !IsProfitableToHoist(*MI)) {
 // If not, try unfolding a hoistable load.
 MI = ExtractHoistableLoad(MI);
 if (!MI) return false;
 // Now move the instructions to the predecessor, inserting it before any
 // terminator instructions.
 DEBUG({
 dbgs() << "Hoisting " << *MI;
 if (MI->getParent()->getBasicBlock())
-dbgs() << " from BB#" << MI->getParent()->getNumber();
+dbgs() << " from " << printMBBReference(*MI->getParent());
 if (Preheader->getBasicBlock())
-dbgs() << " to BB#" << Preheader->getNumber();
+dbgs() << " to " << printMBBReference(*Preheader);
 dbgs() << "\n";
 });
 // If this is the first instruction being hoisted to the preheader,
 // initialize the CSE map with potential common expressions.
 return true;
 }
 /// Get the preheader for the current loop, splitting a critical edge if needed.
-MachineBasicBlock *MachineLICM::getCurPreheader() {
+MachineBasicBlock *MachineLICMBase::getCurPreheader() {
 // Determine the block to which to hoist instructions. If we can't find a
 // suitable loop predecessor, we can't do any hoisting.
 // If we've tried to get a preheader and failed, don't try again.
 if (CurPreheader == reinterpret_cast<MachineBasicBlock *>(-1))

Mercurial > hg > CbC > CbC_llvm

comparison lib/CodeGen/MachineLICM.cpp @ 134:3a76565eade5 LLVM5.0.1