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comparison lib/CodeGen/ScheduleDAG.cpp @ 134:3a76565eade5 LLVM5.0.1

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update 5.0.1
author mir3636
date Sat, 17 Feb 2018 09:57:20 +0900
parents 803732b1fca8
children c2174574ed3a
comparison
equal deleted inserted replaced
133:c60214abe0e8 134:3a76565eade5
17 #include "llvm/ADT/SmallVector.h" 17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/iterator_range.h" 18 #include "llvm/ADT/iterator_range.h"
19 #include "llvm/CodeGen/MachineFunction.h" 19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/ScheduleHazardRecognizer.h" 20 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
21 #include "llvm/CodeGen/SelectionDAGNodes.h" 21 #include "llvm/CodeGen/SelectionDAGNodes.h"
22 #include "llvm/CodeGen/TargetInstrInfo.h"
23 #include "llvm/CodeGen/TargetRegisterInfo.h"
24 #include "llvm/CodeGen/TargetSubtargetInfo.h"
22 #include "llvm/Support/CommandLine.h" 25 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/Compiler.h" 26 #include "llvm/Support/Compiler.h"
24 #include "llvm/Support/Debug.h" 27 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/raw_ostream.h" 28 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Target/TargetRegisterInfo.h"
28 #include "llvm/Target/TargetSubtargetInfo.h"
29 #include <algorithm> 29 #include <algorithm>
30 #include <cassert> 30 #include <cassert>
31 #include <iterator> 31 #include <iterator>
32 #include <limits> 32 #include <limits>
33 #include <utility> 33 #include <utility>
78 78
79 switch (getKind()) { 79 switch (getKind()) {
80 case Data: 80 case Data:
81 OS << " Latency=" << getLatency(); 81 OS << " Latency=" << getLatency();
82 if (TRI && isAssignedRegDep()) 82 if (TRI && isAssignedRegDep())
83 OS << " Reg=" << PrintReg(getReg(), TRI); 83 OS << " Reg=" << printReg(getReg(), TRI);
84 break; 84 break;
85 case Anti: 85 case Anti:
86 case Output: 86 case Output:
87 OS << " Latency=" << getLatency(); 87 OS << " Latency=" << getLatency();
88 break; 88 break;