CbC/CbC_llvm: lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp comparison

comparison lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @ 134:3a76565eade5 LLVM5.0.1

update 5.0.1

author	mir3636
date	Sat, 17 Feb 2018 09:57:20 +0900
parents	803732b1fca8
children	c2174574ed3a

comparison

equal deleted inserted replaced

-:c60214abe0e8
+:3a76565eade5
 #include "llvm/CodeGen/ISDOpcodes.h"
 #include "llvm/CodeGen/MachineMemOperand.h"
 #include "llvm/CodeGen/MachineValueType.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/TargetLowering.h"
 #include "llvm/CodeGen/ValueTypes.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MathExtras.h"
-#include "llvm/Target/TargetLowering.h"
 #include <cassert>
 #include <cstdint>
 #include <iterator>
 #include <utility>
 using namespace llvm;
+#define DEBUG_TYPE "legalizevectorops"
 namespace {
 class VectorLegalizer {
 SelectionDAG& DAG;
 /// bitcasting the result back to the original type.
 SDValue Promote(SDValue Op);
 /// \brief Implements [SU]INT_TO_FP vector promotion.
 ///
-/// This is a [zs]ext of the input operand to the next size up.
+/// This is a [zs]ext of the input operand to a larger integer type.
 SDValue PromoteINT_TO_FP(SDValue Op);
 /// \brief Implements FP_TO_[SU]INT vector promotion of the result type.
 ///
-/// It is promoted to the next size up integer type.  The result is then
+/// It is promoted to a larger integer type.  The result is then
 /// truncated back to the original type.
-SDValue PromoteFP_TO_INT(SDValue Op, bool isSigned);
+SDValue PromoteFP_TO_INT(SDValue Op);
 public:
 VectorLegalizer(SelectionDAG& dag) :
 DAG(dag), TLI(dag.getTargetLoweringInfo()) {}
 bool HasVectorValue = false;
 if (Op.getOpcode() == ISD::LOAD) {
 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
 ISD::LoadExtType ExtType = LD->getExtensionType();
-if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD)
+if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) {
+DEBUG(dbgs() << "\nLegalizing extending vector load: "; Node->dump(&DAG));
 switch (TLI.getLoadExtAction(LD->getExtensionType(), LD->getValueType(0),
 LD->getMemoryVT())) {
 default: llvm_unreachable("This action is not supported yet!");
 case TargetLowering::Legal:
 return TranslateLegalizeResults(Op, Result);
 LLVM_FALLTHROUGH;
 case TargetLowering::Expand:
 Changed = true;
 return LegalizeOp(ExpandLoad(Op));
 }
+}
 } else if (Op.getOpcode() == ISD::STORE) {
 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
 EVT StVT = ST->getMemoryVT();
 MVT ValVT = ST->getValue().getSimpleValueType();
-if (StVT.isVector() && ST->isTruncatingStore())
+if (StVT.isVector() && ST->isTruncatingStore()) {
+DEBUG(dbgs() << "\nLegalizing truncating vector store: ";
+Node->dump(&DAG));
 switch (TLI.getTruncStoreAction(ValVT, StVT)) {
 default: llvm_unreachable("This action is not supported yet!");
 case TargetLowering::Legal:
 return TranslateLegalizeResults(Op, Result);
 case TargetLowering::Custom: {
 }
 case TargetLowering::Expand:
 Changed = true;
 return LegalizeOp(ExpandStore(Op));
 }
+}
 } else if (Op.getOpcode() == ISD::MSCATTER || Op.getOpcode() == ISD::MSTORE)
 HasVectorValue = true;
 for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end();
 J != E;
 case ISD::MSTORE:
 QueryType = cast<MaskedStoreSDNode>(Node)->getValue().getValueType();
 break;
 }
+DEBUG(dbgs() << "\nLegalizing vector op: "; Node->dump(&DAG));
 switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) {
 default: llvm_unreachable("This action is not supported yet!");
 case TargetLowering::Promote:
 Result = Promote(Op);
 Changed = true;
 break;
 case TargetLowering::Legal:
+DEBUG(dbgs() << "Legal node: nothing to do\n");
 break;
 case TargetLowering::Custom: {
+DEBUG(dbgs() << "Trying custom legalization\n");
 if (SDValue Tmp1 = TLI.LowerOperation(Op, DAG)) {
+DEBUG(dbgs() << "Successfully custom legalized node\n");
 Result = Tmp1;
 break;
 }
+DEBUG(dbgs() << "Could not custom legalize node\n");
 LLVM_FALLTHROUGH;
 }
 case TargetLowering::Expand:
 Result = Expand(Op);
 }
 // "Promote" the operation by extending the operand.
 return PromoteINT_TO_FP(Op);
 case ISD::FP_TO_UINT:
 case ISD::FP_TO_SINT:
 // Promote the operation by extending the operand.
-return PromoteFP_TO_INT(Op, Op->getOpcode() == ISD::FP_TO_SINT);
+return PromoteFP_TO_INT(Op);
 }
 // There are currently two cases of vector promotion:
 // 1) Bitcasting a vector of integers to a different type to a vector of the
 //    same overall length. For example, x86 promotes ISD::AND v2i32 to v1i64.
 }
 SDValue VectorLegalizer::PromoteINT_TO_FP(SDValue Op) {
 // INT_TO_FP operations may require the input operand be promoted even
 // when the type is otherwise legal.
-EVT VT = Op.getOperand(0).getValueType();
+MVT VT = Op.getOperand(0).getSimpleValueType();
-assert(Op.getNode()->getNumValues() == 1 &&
+MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
-"Can't promote a vector with multiple results!");
+assert(NVT.getVectorNumElements() == VT.getVectorNumElements() &&
+"Vectors have different number of elements!");
-// Normal getTypeToPromoteTo() doesn't work here, as that will promote
-// by widening the vector w/ the same element width and twice the number
-// of elements. We want the other way around, the same number of elements,
-// each twice the width.
-//
-// Increase the bitwidth of the element to the next pow-of-two
-// (which is greater than 8 bits).
-EVT NVT = VT.widenIntegerVectorElementType(*DAG.getContext());
-assert(NVT.isSimple() && "Promoting to a non-simple vector type!");
 SDLoc dl(Op);
 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
 unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND :
 ISD::SIGN_EXTEND;
 // For FP_TO_INT we promote the result type to a vector type with wider
 // elements and then truncate the result.  This is different from the default
 // PromoteVector which uses bitcast to promote thus assumning that the
 // promoted vector type has the same overall size.
-SDValue VectorLegalizer::PromoteFP_TO_INT(SDValue Op, bool isSigned) {
+SDValue VectorLegalizer::PromoteFP_TO_INT(SDValue Op) {
-assert(Op.getNode()->getNumValues() == 1 &&
+MVT VT = Op.getSimpleValueType();
-"Can't promote a vector with multiple results!");
+MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
-EVT VT = Op.getValueType();
+assert(NVT.getVectorNumElements() == VT.getVectorNumElements() &&
+"Vectors have different number of elements!");
-EVT NewVT;
-unsigned NewOpc;
+unsigned NewOpc = Op->getOpcode();
-while (true) {
+// Change FP_TO_UINT to FP_TO_SINT if possible.
-NewVT = VT.widenIntegerVectorElementType(*DAG.getContext());
+// TODO: Should we only do this if FP_TO_UINT itself isn't legal?
-assert(NewVT.isSimple() && "Promoting to a non-simple vector type!");
+if (NewOpc == ISD::FP_TO_UINT &&
-if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) {
+TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
 NewOpc = ISD::FP_TO_SINT;
-break;
-}
+SDLoc dl(Op);
-if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewVT)) {
+SDValue Promoted  = DAG.getNode(NewOpc, dl, NVT, Op.getOperand(0));
-NewOpc = ISD::FP_TO_UINT;
-break;
+// Assert that the converted value fits in the original type.  If it doesn't
-}
+// (eg: because the value being converted is too big), then the result of the
-}
+// original operation was undefined anyway, so the assert is still correct.
+Promoted = DAG.getNode(Op->getOpcode() == ISD::FP_TO_UINT ? ISD::AssertZext
-SDLoc loc(Op);
+: ISD::AssertSext,
-SDValue promoted  = DAG.getNode(NewOpc, SDLoc(Op), NewVT, Op.getOperand(0));
+dl, NVT, Promoted,
-return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT, promoted);
+DAG.getValueType(VT.getScalarType()));
+return DAG.getNode(ISD::TRUNCATE, dl, VT, Promoted);
 }
 SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
 unsigned WideBytes = WideVT.getStoreSize();
 unsigned Offset = 0;
 unsigned RemainingBytes = SrcVT.getStoreSize();
 SmallVector<SDValue, 8> LoadVals;
 while (RemainingBytes > 0) {
 SDValue ScalarLoad;
 unsigned LoadBytes = WideBytes;
 if (RemainingBytes >= LoadBytes) {
 LD->getMemOperand()->getFlags(), LD->getAAInfo());
 }
 RemainingBytes -= LoadBytes;
 Offset += LoadBytes;
-BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
-DAG.getConstant(LoadBytes, dl,
+BasePTR = DAG.getObjectPtrOffset(dl, BasePTR, LoadBytes);
-BasePTR.getValueType()));
 LoadVals.push_back(ScalarLoad.getValue(0));
 LoadChains.push_back(ScalarLoad.getValue(1));
 }
 return (Op.getResNo() ? NewChain : Value);
 }
 SDValue VectorLegalizer::ExpandStore(SDValue Op) {
 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
-EVT StVT = ST->getMemoryVT();
-EVT MemSclVT = StVT.getScalarType();
-unsigned ScalarSize = MemSclVT.getSizeInBits();
-// Round odd types to the next pow of two.
-if (!isPowerOf2_32(ScalarSize)) {
-// FIXME: This is completely broken and inconsistent with ExpandLoad
-// handling.
-// For sub-byte element sizes, this ends up with 0 stride between elements,
-// so the same element just gets re-written to the same location. There seem
-// to be tests explicitly testing for this broken behavior though.  tests
-// for this broken behavior.
-LLVMContext &Ctx = *DAG.getContext();
-EVT NewMemVT
-= EVT::getVectorVT(Ctx,
-MemSclVT.getIntegerVT(Ctx, NextPowerOf2(ScalarSize)),
-StVT.getVectorNumElements());
-SDValue NewVectorStore = DAG.getTruncStore(
-ST->getChain(), SDLoc(Op), ST->getValue(), ST->getBasePtr(),
-ST->getPointerInfo(), NewMemVT, ST->getAlignment(),
-ST->getMemOperand()->getFlags(), ST->getAAInfo());
-ST = cast<StoreSDNode>(NewVectorStore.getNode());
-}
 SDValue TF = TLI.scalarizeVectorStore(ST, DAG);
 AddLegalizedOperand(Op, TF);
 return TF;
 }

Mercurial > hg > CbC > CbC_llvm

comparison lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @ 134:3a76565eade5 LLVM5.0.1