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comparison lib/Target/Mips/MipsLongBranch.cpp @ 134:3a76565eade5 LLVM5.0.1

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update 5.0.1
author mir3636
date Sat, 17 Feb 2018 09:57:20 +0900
parents 803732b1fca8
children
comparison
equal deleted inserted replaced
133:c60214abe0e8 134:3a76565eade5
29 #include "llvm/CodeGen/MachineFunction.h" 29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineFunctionPass.h" 30 #include "llvm/CodeGen/MachineFunctionPass.h"
31 #include "llvm/CodeGen/MachineInstr.h" 31 #include "llvm/CodeGen/MachineInstr.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h" 32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineOperand.h" 33 #include "llvm/CodeGen/MachineOperand.h"
34 #include "llvm/CodeGen/TargetSubtargetInfo.h"
34 #include "llvm/IR/DebugLoc.h" 35 #include "llvm/IR/DebugLoc.h"
35 #include "llvm/Support/CommandLine.h" 36 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h" 37 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h" 38 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Target/TargetMachine.h" 39 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetSubtargetInfo.h"
40 #include <cassert> 40 #include <cassert>
41 #include <cstdint> 41 #include <cstdint>
42 #include <iterator> 42 #include <iterator>
43 43
44 using namespace llvm; 44 using namespace llvm;
277 MachineBasicBlock *BalTgtMBB = MF->CreateMachineBasicBlock(BB); 277 MachineBasicBlock *BalTgtMBB = MF->CreateMachineBasicBlock(BB);
278 MF->insert(FallThroughMBB, BalTgtMBB); 278 MF->insert(FallThroughMBB, BalTgtMBB);
279 LongBrMBB->addSuccessor(BalTgtMBB); 279 LongBrMBB->addSuccessor(BalTgtMBB);
280 BalTgtMBB->addSuccessor(TgtMBB); 280 BalTgtMBB->addSuccessor(TgtMBB);
281 281
282 // We must select between the MIPS32r6/MIPS64r6 BAL (which is a normal 282 // We must select between the MIPS32r6/MIPS64r6 BALC (which is a normal
283 // instruction) and the pre-MIPS32r6/MIPS64r6 definition (which is an 283 // instruction) and the pre-MIPS32r6/MIPS64r6 definition (which is an
284 // pseudo-instruction wrapping BGEZAL). 284 // pseudo-instruction wrapping BGEZAL).
285 unsigned BalOp = Subtarget.hasMips32r6() ? Mips::BAL : Mips::BAL_BR; 285 const unsigned BalOp =
286 Subtarget.hasMips32r6()
287 ? Subtarget.inMicroMipsMode() ? Mips::BALC_MMR6 : Mips::BALC
288 : Mips::BAL_BR;
286 289
287 if (!ABI.IsN64()) { 290 if (!ABI.IsN64()) {
291 // Pre R6:
288 // $longbr: 292 // $longbr:
289 // addiu $sp, $sp, -8 293 // addiu $sp, $sp, -8
290 // sw $ra, 0($sp) 294 // sw $ra, 0($sp)
291 // lui $at, %hi($tgt - $baltgt) 295 // lui $at, %hi($tgt - $baltgt)
292 // bal $baltgt 296 // bal $baltgt
297 // jr $at 301 // jr $at
298 // addiu $sp, $sp, 8 302 // addiu $sp, $sp, 8
299 // $fallthrough: 303 // $fallthrough:
300 // 304 //
301 305
306 // R6:
307 // $longbr:
308 // addiu $sp, $sp, -8
309 // sw $ra, 0($sp)
310 // lui $at, %hi($tgt - $baltgt)
311 // addiu $at, $at, %lo($tgt - $baltgt)
312 // balc $baltgt
313 // $baltgt:
314 // addu $at, $ra, $at
315 // lw $ra, 0($sp)
316 // addiu $sp, $sp, 8
317 // jic $at, 0
318 // $fallthrough:
319
302 Pos = LongBrMBB->begin(); 320 Pos = LongBrMBB->begin();
303 321
304 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) 322 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
305 .addReg(Mips::SP).addImm(-8); 323 .addReg(Mips::SP).addImm(-8);
306 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA) 324 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA)
307 .addReg(Mips::SP).addImm(0); 325 .addReg(Mips::SP).addImm(0);
308 326
309 // LUi and ADDiu instructions create 32-bit offset of the target basic 327 // LUi and ADDiu instructions create 32-bit offset of the target basic
310 // block from the target of BAL instruction. We cannot use immediate 328 // block from the target of BAL(C) instruction. We cannot use immediate
311 // value for this offset because it cannot be determined accurately when 329 // value for this offset because it cannot be determined accurately when
312 // the program has inline assembly statements. We therefore use the 330 // the program has inline assembly statements. We therefore use the
313 // relocation expressions %hi($tgt-$baltgt) and %lo($tgt-$baltgt) which 331 // relocation expressions %hi($tgt-$baltgt) and %lo($tgt-$baltgt) which
314 // are resolved during the fixup, so the values will always be correct. 332 // are resolved during the fixup, so the values will always be correct.
315 // 333 //
322 // %hi($tgt-$baltgt) and %lo($tgt-$baltgt) expressions and add them as 340 // %hi($tgt-$baltgt) and %lo($tgt-$baltgt) expressions and add them as
323 // operands to lowered instructions. 341 // operands to lowered instructions.
324 342
325 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT) 343 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT)
326 .addMBB(TgtMBB).addMBB(BalTgtMBB); 344 .addMBB(TgtMBB).addMBB(BalTgtMBB);
327 MIBundleBuilder(*LongBrMBB, Pos) 345
328 .append(BuildMI(*MF, DL, TII->get(BalOp)).addMBB(BalTgtMBB)) 346 MachineInstrBuilder BalInstr =
329 .append(BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT) 347 BuildMI(*MF, DL, TII->get(BalOp)).addMBB(BalTgtMBB);
330 .addReg(Mips::AT) 348 MachineInstrBuilder ADDiuInstr =
331 .addMBB(TgtMBB) 349 BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT)
332 .addMBB(BalTgtMBB)); 350 .addReg(Mips::AT)
351 .addMBB(TgtMBB)
352 .addMBB(BalTgtMBB);
353 if (Subtarget.hasMips32r6()) {
354 LongBrMBB->insert(Pos, ADDiuInstr);
355 LongBrMBB->insert(Pos, BalInstr);
356 } else {
357 LongBrMBB->insert(Pos, BalInstr);
358 LongBrMBB->insert(Pos, ADDiuInstr);
359 LongBrMBB->rbegin()->bundleWithPred();
360 }
333 361
334 Pos = BalTgtMBB->begin(); 362 Pos = BalTgtMBB->begin();
335 363
336 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT) 364 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT)
337 .addReg(Mips::RA).addReg(Mips::AT); 365 .addReg(Mips::RA).addReg(Mips::AT);
338 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA) 366 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
339 .addReg(Mips::SP).addImm(0); 367 .addReg(Mips::SP).addImm(0);
368 if (Subtarget.isTargetNaCl())
369 // Bundle-align the target of indirect branch JR.
370 TgtMBB->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
340 371
341 // In NaCl, modifying the sp is not allowed in branch delay slot. 372 // In NaCl, modifying the sp is not allowed in branch delay slot.
342 if (Subtarget.isTargetNaCl()) 373 // For MIPS32R6, we can skip using a delay slot branch.
374 if (Subtarget.isTargetNaCl() || Subtarget.hasMips32r6())
343 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) 375 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
344 .addReg(Mips::SP).addImm(8); 376 .addReg(Mips::SP).addImm(8);
345 377
346 if (Subtarget.hasMips32r6()) 378 if (Subtarget.hasMips32r6()) {
347 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JALR)) 379 const unsigned JICOp =
348 .addReg(Mips::ZERO).addReg(Mips::AT); 380 Subtarget.inMicroMipsMode() ? Mips::JIC_MMR6 : Mips::JIC;
349 else 381 BuildMI(*BalTgtMBB, Pos, DL, TII->get(JICOp))
382 .addReg(Mips::AT)
383 .addImm(0);
384
385 } else {
350 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JR)).addReg(Mips::AT); 386 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JR)).addReg(Mips::AT);
351 387
352 if (Subtarget.isTargetNaCl()) { 388 if (Subtarget.isTargetNaCl()) {
353 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::NOP)); 389 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::NOP));
354 // Bundle-align the target of indirect branch JR. 390 } else
355 TgtMBB->setAlignment(MIPS_NACL_BUNDLE_ALIGN); 391 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
356 } else 392 .addReg(Mips::SP)
357 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) 393 .addImm(8);
358 .addReg(Mips::SP).addImm(8); 394
359 395 BalTgtMBB->rbegin()->bundleWithPred();
360 BalTgtMBB->rbegin()->bundleWithPred(); 396 }
361 } else { 397 } else {
398 // Pre R6:
362 // $longbr: 399 // $longbr:
363 // daddiu $sp, $sp, -16 400 // daddiu $sp, $sp, -16
364 // sd $ra, 0($sp) 401 // sd $ra, 0($sp)
365 // daddiu $at, $zero, %hi($tgt - $baltgt) 402 // daddiu $at, $zero, %hi($tgt - $baltgt)
366 // dsll $at, $at, 16 403 // dsll $at, $at, 16
370 // daddu $at, $ra, $at 407 // daddu $at, $ra, $at
371 // ld $ra, 0($sp) 408 // ld $ra, 0($sp)
372 // jr64 $at 409 // jr64 $at
373 // daddiu $sp, $sp, 16 410 // daddiu $sp, $sp, 16
374 // $fallthrough: 411 // $fallthrough:
375 // 412
413 // R6:
414 // $longbr:
415 // daddiu $sp, $sp, -16
416 // sd $ra, 0($sp)
417 // daddiu $at, $zero, %hi($tgt - $baltgt)
418 // dsll $at, $at, 16
419 // daddiu $at, $at, %lo($tgt - $baltgt)
420 // balc $baltgt
421 // $baltgt:
422 // daddu $at, $ra, $at
423 // ld $ra, 0($sp)
424 // daddiu $sp, $sp, 16
425 // jic $at, 0
426 // $fallthrough:
376 427
377 // We assume the branch is within-function, and that offset is within 428 // We assume the branch is within-function, and that offset is within
378 // +/- 2GB. High 32 bits will therefore always be zero. 429 // +/- 2GB. High 32 bits will therefore always be zero.
379 430
380 // Note that this will work even if the offset is negative, because 431 // Note that this will work even if the offset is negative, because
399 Mips::AT_64).addReg(Mips::ZERO_64) 450 Mips::AT_64).addReg(Mips::ZERO_64)
400 .addMBB(TgtMBB, MipsII::MO_ABS_HI).addMBB(BalTgtMBB); 451 .addMBB(TgtMBB, MipsII::MO_ABS_HI).addMBB(BalTgtMBB);
401 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::AT_64) 452 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::AT_64)
402 .addReg(Mips::AT_64).addImm(16); 453 .addReg(Mips::AT_64).addImm(16);
403 454
404 MIBundleBuilder(*LongBrMBB, Pos) 455 MachineInstrBuilder BalInstr =
405 .append(BuildMI(*MF, DL, TII->get(BalOp)).addMBB(BalTgtMBB)) 456 BuildMI(*MF, DL, TII->get(BalOp)).addMBB(BalTgtMBB);
406 .append( 457 MachineInstrBuilder DADDiuInstr =
407 BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_DADDiu), Mips::AT_64) 458 BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_DADDiu), Mips::AT_64)
408 .addReg(Mips::AT_64) 459 .addReg(Mips::AT_64)
409 .addMBB(TgtMBB, MipsII::MO_ABS_LO) 460 .addMBB(TgtMBB, MipsII::MO_ABS_LO)
410 .addMBB(BalTgtMBB)); 461 .addMBB(BalTgtMBB);
462 if (Subtarget.hasMips32r6()) {
463 LongBrMBB->insert(Pos, DADDiuInstr);
464 LongBrMBB->insert(Pos, BalInstr);
465 } else {
466 LongBrMBB->insert(Pos, BalInstr);
467 LongBrMBB->insert(Pos, DADDiuInstr);
468 LongBrMBB->rbegin()->bundleWithPred();
469 }
411 470
412 Pos = BalTgtMBB->begin(); 471 Pos = BalTgtMBB->begin();
413 472
414 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDu), Mips::AT_64) 473 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDu), Mips::AT_64)
415 .addReg(Mips::RA_64).addReg(Mips::AT_64); 474 .addReg(Mips::RA_64).addReg(Mips::AT_64);
416 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LD), Mips::RA_64) 475 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LD), Mips::RA_64)
417 .addReg(Mips::SP_64).addImm(0); 476 .addReg(Mips::SP_64).addImm(0);
418 477
419 if (Subtarget.hasMips64r6()) 478 if (Subtarget.hasMips64r6()) {
420 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JALR64)) 479 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
421 .addReg(Mips::ZERO_64).addReg(Mips::AT_64); 480 .addReg(Mips::SP_64)
422 else 481 .addImm(16);
482 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JIC64))
483 .addReg(Mips::AT_64)
484 .addImm(0);
485 } else {
423 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JR64)).addReg(Mips::AT_64); 486 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JR64)).addReg(Mips::AT_64);
424 487 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
425 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64) 488 .addReg(Mips::SP_64)
426 .addReg(Mips::SP_64).addImm(16); 489 .addImm(16);
427 BalTgtMBB->rbegin()->bundleWithPred(); 490 BalTgtMBB->rbegin()->bundleWithPred();
491 }
428 } 492 }
429 493
430 assert(LongBrMBB->size() + BalTgtMBB->size() == LongBranchSeqSize); 494 assert(LongBrMBB->size() + BalTgtMBB->size() == LongBranchSeqSize);
431 } else { 495 } else {
432 // $longbr: 496 // Pre R6: R6:
433 // j $tgt 497 // $longbr: $longbr:
434 // nop 498 // j $tgt bc $tgt
499 // nop $fallthrough
435 // $fallthrough: 500 // $fallthrough:
436 // 501 //
437 Pos = LongBrMBB->begin(); 502 Pos = LongBrMBB->begin();
438 LongBrMBB->addSuccessor(TgtMBB); 503 LongBrMBB->addSuccessor(TgtMBB);
439 MIBundleBuilder(*LongBrMBB, Pos) 504 if (Subtarget.hasMips32r6())
440 .append(BuildMI(*MF, DL, TII->get(Mips::J)).addMBB(TgtMBB)) 505 BuildMI(*LongBrMBB, Pos, DL,
441 .append(BuildMI(*MF, DL, TII->get(Mips::NOP))); 506 TII->get(Subtarget.inMicroMipsMode() ? Mips::BC_MMR6 : Mips::BC))
507 .addMBB(TgtMBB);
508 else
509 MIBundleBuilder(*LongBrMBB, Pos)
510 .append(BuildMI(*MF, DL, TII->get(Mips::J)).addMBB(TgtMBB))
511 .append(BuildMI(*MF, DL, TII->get(Mips::NOP)));
442 512
443 assert(LongBrMBB->size() == LongBranchSeqSize); 513 assert(LongBrMBB->size() == LongBranchSeqSize);
444 } 514 }
445 515
446 if (I.Br->isUnconditionalBranch()) { 516 if (I.Br->isUnconditionalBranch()) {
472 542
473 const TargetMachine& TM = F.getTarget(); 543 const TargetMachine& TM = F.getTarget();
474 IsPIC = TM.isPositionIndependent(); 544 IsPIC = TM.isPositionIndependent();
475 ABI = static_cast<const MipsTargetMachine &>(TM).getABI(); 545 ABI = static_cast<const MipsTargetMachine &>(TM).getABI();
476 546
477 LongBranchSeqSize = 547 LongBranchSeqSize = IsPIC ? ((ABI.IsN64() || STI.isTargetNaCl()) ? 10 : 9)
478 !IsPIC ? 2 : (ABI.IsN64() ? 10 : (!STI.isTargetNaCl() ? 9 : 10)); 548 : (STI.hasMips32r6() ? 1 : 2);
479 549
480 if (STI.inMips16Mode() || !STI.enableLongBranchPass()) 550 if (STI.inMips16Mode() || !STI.enableLongBranchPass())
481 return false; 551 return false;
482 if (IsPIC && static_cast<const MipsTargetMachine &>(TM).getABI().IsO32() && 552 if (IsPIC && static_cast<const MipsTargetMachine &>(TM).getABI().IsO32() &&
483 F.getInfo<MipsFunctionInfo>()->globalBaseRegSet()) 553 F.getInfo<MipsFunctionInfo>()->globalBaseRegSet())