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comparison lib/Target/SystemZ/SystemZInstrFormats.td @ 134:3a76565eade5 LLVM5.0.1

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update 5.0.1
author mir3636
date Sat, 17 Feb 2018 09:57:20 +0900
parents 803732b1fca8
children c2174574ed3a
comparison
equal deleted inserted replaced
133:c60214abe0e8 134:3a76565eade5
18 dag OutOperandList = outs; 18 dag OutOperandList = outs;
19 dag InOperandList = ins; 19 dag InOperandList = ins;
20 let Size = size; 20 let Size = size;
21 let Pattern = pattern; 21 let Pattern = pattern;
22 let AsmString = asmstr; 22 let AsmString = asmstr;
23
24 let hasSideEffects = 0;
25 let mayLoad = 0;
26 let mayStore = 0;
23 27
24 // Some instructions come in pairs, one having a 12-bit displacement 28 // Some instructions come in pairs, one having a 12-bit displacement
25 // and the other having a 20-bit displacement. Both instructions in 29 // and the other having a 20-bit displacement. Both instructions in
26 // the pair have the same DispKey and their DispSizes are "12" and "20" 30 // the pair have the same DispKey and their DispSizes are "12" and "20"
27 // respectively. 31 // respectively.
2098 2102
2099 class CondBranchRXY<string mnemonic, bits<16> opcode> 2103 class CondBranchRXY<string mnemonic, bits<16> opcode>
2100 : InstRXYb<opcode, (outs), (ins cond4:$valid, cond4:$M1, bdxaddr20only:$XBD2), 2104 : InstRXYb<opcode, (outs), (ins cond4:$valid, cond4:$M1, bdxaddr20only:$XBD2),
2101 !subst("#", "${M1}", mnemonic)#"\t$XBD2", []> { 2105 !subst("#", "${M1}", mnemonic)#"\t$XBD2", []> {
2102 let CCMaskFirst = 1; 2106 let CCMaskFirst = 1;
2107 let mayLoad = 1;
2103 } 2108 }
2104 2109
2105 class AsmCondBranchRXY<string mnemonic, bits<16> opcode> 2110 class AsmCondBranchRXY<string mnemonic, bits<16> opcode>
2106 : InstRXYb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr20only:$XBD2), 2111 : InstRXYb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr20only:$XBD2),
2107 mnemonic#"\t$M1, $XBD2", []>; 2112 mnemonic#"\t$M1, $XBD2", []> {
2113 let mayLoad = 1;
2114 }
2108 2115
2109 class FixedCondBranchRXY<CondVariant V, string mnemonic, bits<16> opcode, 2116 class FixedCondBranchRXY<CondVariant V, string mnemonic, bits<16> opcode,
2110 SDPatternOperator operator = null_frag> 2117 SDPatternOperator operator = null_frag>
2111 : InstRXYb<opcode, (outs), (ins bdxaddr20only:$XBD2), 2118 : InstRXYb<opcode, (outs), (ins bdxaddr20only:$XBD2),
2112 !subst("#", V.suffix, mnemonic)#"\t$XBD2", 2119 !subst("#", V.suffix, mnemonic)#"\t$XBD2",
2113 [(operator (load bdxaddr20only:$XBD2))]> { 2120 [(operator (load bdxaddr20only:$XBD2))]> {
2114 let isAsmParserOnly = V.alternate; 2121 let isAsmParserOnly = V.alternate;
2115 let M1 = V.ccmask; 2122 let M1 = V.ccmask;
2123 let mayLoad = 1;
2116 } 2124 }
2117 2125
2118 class CmpBranchRIEa<string mnemonic, bits<16> opcode, 2126 class CmpBranchRIEa<string mnemonic, bits<16> opcode,
2119 RegisterOperand cls, Immediate imm> 2127 RegisterOperand cls, Immediate imm>
2120 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, cond4:$M3), 2128 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, cond4:$M3),
2781 AddressingMode mode = bdaddr20only> { 2789 AddressingMode mode = bdaddr20only> {
2782 let isCodeGenOnly = 1 in 2790 let isCodeGenOnly = 1 in
2783 def "" : CondUnaryRSY<mnemonic, opcode, operator, cls, bytes, mode>; 2791 def "" : CondUnaryRSY<mnemonic, opcode, operator, cls, bytes, mode>;
2784 def Asm : AsmCondUnaryRSY<mnemonic, opcode, cls, bytes, mode>; 2792 def Asm : AsmCondUnaryRSY<mnemonic, opcode, cls, bytes, mode>;
2785 } 2793 }
2786
2787 2794
2788 class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator, 2795 class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2789 RegisterOperand cls, bits<5> bytes, 2796 RegisterOperand cls, bits<5> bytes,
2790 AddressingMode mode = bdxaddr12only> 2797 AddressingMode mode = bdxaddr12only>
2791 : InstRXa<opcode, (outs cls:$R1), (ins mode:$XBD2), 2798 : InstRXa<opcode, (outs cls:$R1), (ins mode:$XBD2),
4686 } 4693 }
4687 4694
4688 // Stores $new to $addr if $cc is true ("" case) or false (Inv case). 4695 // Stores $new to $addr if $cc is true ("" case) or false (Inv case).
4689 multiclass CondStores<RegisterOperand cls, SDPatternOperator store, 4696 multiclass CondStores<RegisterOperand cls, SDPatternOperator store,
4690 SDPatternOperator load, AddressingMode mode> { 4697 SDPatternOperator load, AddressingMode mode> {
4691 let Defs = [CC], Uses = [CC], usesCustomInserter = 1 in { 4698 let Defs = [CC], Uses = [CC], usesCustomInserter = 1,
4699 mayLoad = 1, mayStore = 1 in {
4692 def "" : Pseudo<(outs), 4700 def "" : Pseudo<(outs),
4693 (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc), 4701 (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc),
4694 [(store (z_select_ccmask cls:$new, (load mode:$addr), 4702 [(store (z_select_ccmask cls:$new, (load mode:$addr),
4695 imm32zx4:$valid, imm32zx4:$cc), 4703 imm32zx4:$valid, imm32zx4:$cc),
4696 mode:$addr)]>; 4704 mode:$addr)]>;