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comparison test/CodeGen/Mips/llvm-ir/and.ll @ 134:3a76565eade5 LLVM5.0.1

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update 5.0.1
author mir3636
date Sat, 17 Feb 2018 09:57:20 +0900
parents 803732b1fca8
children c2174574ed3a
comparison
equal deleted inserted replaced
133:c60214abe0e8 134:3a76565eade5
1 ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: -check-prefixes=ALL,GP32 2 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips2 | FileCheck %s \
3 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ 3 ; RUN: -check-prefix=MIPS
4 ; RUN: -check-prefixes=ALL,GP32 4 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 | FileCheck %s \
5 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ 5 ; RUN: -check-prefix=MIPS
6 ; RUN: -check-prefixes=ALL,GP32 6 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r2 | FileCheck %s \
7 ; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ 7 ; RUN: -check-prefix=MIPS32R2
8 ; RUN: -check-prefixes=ALL,GP32 8 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 | FileCheck %s \
9 ; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ 9 ; RUN: -check-prefix=MIPS32R2
10 ; RUN: -check-prefixes=ALL,GP32 10 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 | FileCheck %s \
11 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ 11 ; RUN: -check-prefix=MIPS32R2
12 ; RUN: -check-prefixes=ALL,GP32 12 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 | FileCheck %s \
13 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ 13 ; RUN: -check-prefix=MIPS32R6
14 ; RUN: -check-prefixes=ALL,GP64 14 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips3 | FileCheck %s \
15 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ 15 ; RUN: -check-prefix=MIPS64
16 ; RUN: -check-prefixes=ALL,GP64 16 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips4 | FileCheck %s \
17 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ 17 ; RUN: -check-prefix=MIPS64
18 ; RUN: -check-prefixes=ALL,GP64 18 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64 | FileCheck %s \
19 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ 19 ; RUN: -check-prefix=MIPS64
20 ; RUN: -check-prefixes=ALL,GP64 20 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 | FileCheck %s \
21 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ 21 ; RUN: -check-prefix=MIPS64R2
22 ; RUN: -check-prefixes=ALL,GP64 22 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r3 | FileCheck %s \
23 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ 23 ; RUN: -check-prefix=MIPS64R2
24 ; RUN: -check-prefixes=ALL,GP64 24 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r5 | FileCheck %s \
25 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ 25 ; RUN: -check-prefix=MIPS64R2
26 ; RUN: -check-prefixes=ALL,GP64 26 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 | FileCheck %s \
27 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ 27 ; RUN: -check-prefix=MIPS64R6
28 ; RUN: -check-prefixes=ALL,MM,MM32 28 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
29 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ 29 ; RUN: -check-prefix=MM32R3
30 ; RUN: -check-prefixes=ALL,MM,MM32 30 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
31 ; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \ 31 ; RUN: -check-prefix=MM32R6
32 ; RUN: -check-prefixes=ALL,MM,MM64
33 32
34 define signext i1 @and_i1(i1 signext %a, i1 signext %b) { 33 define signext i1 @and_i1(i1 signext %a, i1 signext %b) {
35 entry: 34 ; MIPS-LABEL: and_i1:
36 ; ALL-LABEL: and_i1: 35 ; MIPS: # %bb.0: # %entry
37 36 ; MIPS-NEXT: jr $ra
38 ; GP32: and $2, $4, $5 37 ; MIPS-NEXT: and $2, $4, $5
39 38 ;
40 ; GP64: and $1, $4, $5 39 ; MIPS32R2-LABEL: and_i1:
41 40 ; MIPS32R2: # %bb.0: # %entry
42 ; MM32: and16 $[[T0:[0-9]+]], $5 41 ; MIPS32R2-NEXT: jr $ra
43 ; MM32: move $2, $[[T0]] 42 ; MIPS32R2-NEXT: and $2, $4, $5
44 43 ;
45 ; MM64: and $1, $4, $5 44 ; MIPS32R6-LABEL: and_i1:
46 45 ; MIPS32R6: # %bb.0: # %entry
46 ; MIPS32R6-NEXT: jr $ra
47 ; MIPS32R6-NEXT: and $2, $4, $5
48 ;
49 ; MIPS64-LABEL: and_i1:
50 ; MIPS64: # %bb.0: # %entry
51 ; MIPS64-NEXT: and $1, $4, $5
52 ; MIPS64-NEXT: jr $ra
53 ; MIPS64-NEXT: sll $2, $1, 0
54 ;
55 ; MIPS64R2-LABEL: and_i1:
56 ; MIPS64R2: # %bb.0: # %entry
57 ; MIPS64R2-NEXT: and $1, $4, $5
58 ; MIPS64R2-NEXT: jr $ra
59 ; MIPS64R2-NEXT: sll $2, $1, 0
60 ;
61 ; MIPS64R6-LABEL: and_i1:
62 ; MIPS64R6: # %bb.0: # %entry
63 ; MIPS64R6-NEXT: and $1, $4, $5
64 ; MIPS64R6-NEXT: jr $ra
65 ; MIPS64R6-NEXT: sll $2, $1, 0
66 ;
67 ; MM32R3-LABEL: and_i1:
68 ; MM32R3: # %bb.0: # %entry
69 ; MM32R3-NEXT: and16 $4, $5
70 ; MM32R3-NEXT: move $2, $4
71 ; MM32R3-NEXT: jrc $ra
72 ;
73 ; MM32R6-LABEL: and_i1:
74 ; MM32R6: # %bb.0: # %entry
75 ; MM32R6-NEXT: and $2, $4, $5
76 ; MM32R6-NEXT: jrc $ra
77 entry:
47 %r = and i1 %a, %b 78 %r = and i1 %a, %b
48 ret i1 %r 79 ret i1 %r
49 } 80 }
50 81
51 define signext i8 @and_i8(i8 signext %a, i8 signext %b) { 82 define signext i8 @and_i8(i8 signext %a, i8 signext %b) {
52 entry: 83 ; MIPS-LABEL: and_i8:
53 ; ALL-LABEL: and_i8: 84 ; MIPS: # %bb.0: # %entry
54 85 ; MIPS-NEXT: jr $ra
55 ; GP32: and $2, $4, $5 86 ; MIPS-NEXT: and $2, $4, $5
56 87 ;
57 ; GP64: and $1, $4, $5 88 ; MIPS32R2-LABEL: and_i8:
58 89 ; MIPS32R2: # %bb.0: # %entry
59 ; MM32: and16 $[[T0:[0-9]+]], $5 90 ; MIPS32R2-NEXT: jr $ra
60 ; MM32: move $2, $[[T0]] 91 ; MIPS32R2-NEXT: and $2, $4, $5
61 92 ;
62 ; MM64: and $1, $4, $5 93 ; MIPS32R6-LABEL: and_i8:
63 94 ; MIPS32R6: # %bb.0: # %entry
95 ; MIPS32R6-NEXT: jr $ra
96 ; MIPS32R6-NEXT: and $2, $4, $5
97 ;
98 ; MIPS64-LABEL: and_i8:
99 ; MIPS64: # %bb.0: # %entry
100 ; MIPS64-NEXT: and $1, $4, $5
101 ; MIPS64-NEXT: jr $ra
102 ; MIPS64-NEXT: sll $2, $1, 0
103 ;
104 ; MIPS64R2-LABEL: and_i8:
105 ; MIPS64R2: # %bb.0: # %entry
106 ; MIPS64R2-NEXT: and $1, $4, $5
107 ; MIPS64R2-NEXT: jr $ra
108 ; MIPS64R2-NEXT: sll $2, $1, 0
109 ;
110 ; MIPS64R6-LABEL: and_i8:
111 ; MIPS64R6: # %bb.0: # %entry
112 ; MIPS64R6-NEXT: and $1, $4, $5
113 ; MIPS64R6-NEXT: jr $ra
114 ; MIPS64R6-NEXT: sll $2, $1, 0
115 ;
116 ; MM32R3-LABEL: and_i8:
117 ; MM32R3: # %bb.0: # %entry
118 ; MM32R3-NEXT: and16 $4, $5
119 ; MM32R3-NEXT: move $2, $4
120 ; MM32R3-NEXT: jrc $ra
121 ;
122 ; MM32R6-LABEL: and_i8:
123 ; MM32R6: # %bb.0: # %entry
124 ; MM32R6-NEXT: and $2, $4, $5
125 ; MM32R6-NEXT: jrc $ra
126 entry:
64 %r = and i8 %a, %b 127 %r = and i8 %a, %b
65 ret i8 %r 128 ret i8 %r
66 } 129 }
67 130
68 define signext i16 @and_i16(i16 signext %a, i16 signext %b) { 131 define signext i16 @and_i16(i16 signext %a, i16 signext %b) {
69 entry: 132 ; MIPS-LABEL: and_i16:
70 ; ALL-LABEL: and_i16: 133 ; MIPS: # %bb.0: # %entry
71 134 ; MIPS-NEXT: jr $ra
72 ; GP32: and $2, $4, $5 135 ; MIPS-NEXT: and $2, $4, $5
73 136 ;
74 ; GP64: and $1, $4, $5 137 ; MIPS32R2-LABEL: and_i16:
75 138 ; MIPS32R2: # %bb.0: # %entry
76 ; MM32: and16 $[[T0:[0-9]+]], $5 139 ; MIPS32R2-NEXT: jr $ra
77 ; MM32 move $2, $[[T0]] 140 ; MIPS32R2-NEXT: and $2, $4, $5
78 141 ;
79 ; MM64: and $1, $4, $5 142 ; MIPS32R6-LABEL: and_i16:
80 143 ; MIPS32R6: # %bb.0: # %entry
144 ; MIPS32R6-NEXT: jr $ra
145 ; MIPS32R6-NEXT: and $2, $4, $5
146 ;
147 ; MIPS64-LABEL: and_i16:
148 ; MIPS64: # %bb.0: # %entry
149 ; MIPS64-NEXT: and $1, $4, $5
150 ; MIPS64-NEXT: jr $ra
151 ; MIPS64-NEXT: sll $2, $1, 0
152 ;
153 ; MIPS64R2-LABEL: and_i16:
154 ; MIPS64R2: # %bb.0: # %entry
155 ; MIPS64R2-NEXT: and $1, $4, $5
156 ; MIPS64R2-NEXT: jr $ra
157 ; MIPS64R2-NEXT: sll $2, $1, 0
158 ;
159 ; MIPS64R6-LABEL: and_i16:
160 ; MIPS64R6: # %bb.0: # %entry
161 ; MIPS64R6-NEXT: and $1, $4, $5
162 ; MIPS64R6-NEXT: jr $ra
163 ; MIPS64R6-NEXT: sll $2, $1, 0
164 ;
165 ; MM32R3-LABEL: and_i16:
166 ; MM32R3: # %bb.0: # %entry
167 ; MM32R3-NEXT: and16 $4, $5
168 ; MM32R3-NEXT: move $2, $4
169 ; MM32R3-NEXT: jrc $ra
170 ;
171 ; MM32R6-LABEL: and_i16:
172 ; MM32R6: # %bb.0: # %entry
173 ; MM32R6-NEXT: and $2, $4, $5
174 ; MM32R6-NEXT: jrc $ra
175 entry:
81 %r = and i16 %a, %b 176 %r = and i16 %a, %b
82 ret i16 %r 177 ret i16 %r
83 } 178 }
84 179
85 define signext i32 @and_i32(i32 signext %a, i32 signext %b) { 180 define signext i32 @and_i32(i32 signext %a, i32 signext %b) {
86 entry: 181 ; MIPS-LABEL: and_i32:
87 ; ALL-LABEL: and_i32: 182 ; MIPS: # %bb.0: # %entry
88 183 ; MIPS-NEXT: jr $ra
89 ; GP32: and $2, $4, $5 184 ; MIPS-NEXT: and $2, $4, $5
90 185 ;
91 ; GP64: and $[[T0:[0-9]+]], $4, $5 186 ; MIPS32R2-LABEL: and_i32:
92 ; GP64: sll $2, $[[T0]], 0 187 ; MIPS32R2: # %bb.0: # %entry
93 188 ; MIPS32R2-NEXT: jr $ra
94 ; MM32: and16 $[[T0:[0-9]+]], $5 189 ; MIPS32R2-NEXT: and $2, $4, $5
95 ; MM32: move $2, $[[T0]] 190 ;
96 191 ; MIPS32R6-LABEL: and_i32:
97 ; MM64: and $[[T0:[0-9]+]], $4, $5 192 ; MIPS32R6: # %bb.0: # %entry
98 ; MM64: sll $2, $[[T0]], 0 193 ; MIPS32R6-NEXT: jr $ra
99 194 ; MIPS32R6-NEXT: and $2, $4, $5
195 ;
196 ; MIPS64-LABEL: and_i32:
197 ; MIPS64: # %bb.0: # %entry
198 ; MIPS64-NEXT: and $1, $4, $5
199 ; MIPS64-NEXT: jr $ra
200 ; MIPS64-NEXT: sll $2, $1, 0
201 ;
202 ; MIPS64R2-LABEL: and_i32:
203 ; MIPS64R2: # %bb.0: # %entry
204 ; MIPS64R2-NEXT: and $1, $4, $5
205 ; MIPS64R2-NEXT: jr $ra
206 ; MIPS64R2-NEXT: sll $2, $1, 0
207 ;
208 ; MIPS64R6-LABEL: and_i32:
209 ; MIPS64R6: # %bb.0: # %entry
210 ; MIPS64R6-NEXT: and $1, $4, $5
211 ; MIPS64R6-NEXT: jr $ra
212 ; MIPS64R6-NEXT: sll $2, $1, 0
213 ;
214 ; MM32R3-LABEL: and_i32:
215 ; MM32R3: # %bb.0: # %entry
216 ; MM32R3-NEXT: and16 $4, $5
217 ; MM32R3-NEXT: move $2, $4
218 ; MM32R3-NEXT: jrc $ra
219 ;
220 ; MM32R6-LABEL: and_i32:
221 ; MM32R6: # %bb.0: # %entry
222 ; MM32R6-NEXT: and $2, $4, $5
223 ; MM32R6-NEXT: jrc $ra
224 entry:
100 %r = and i32 %a, %b 225 %r = and i32 %a, %b
101 ret i32 %r 226 ret i32 %r
102 } 227 }
103 228
104 define signext i64 @and_i64(i64 signext %a, i64 signext %b) { 229 define signext i64 @and_i64(i64 signext %a, i64 signext %b) {
105 entry: 230 ; MIPS-LABEL: and_i64:
106 ; ALL-LABEL: and_i64: 231 ; MIPS: # %bb.0: # %entry
107 232 ; MIPS-NEXT: and $2, $4, $6
108 ; GP32: and $2, $4, $6 233 ; MIPS-NEXT: jr $ra
109 ; GP32: and $3, $5, $7 234 ; MIPS-NEXT: and $3, $5, $7
110 235 ;
111 ; GP64: and $2, $4, $5 236 ; MIPS32R2-LABEL: and_i64:
112 237 ; MIPS32R2: # %bb.0: # %entry
113 ; MM32: and16 $[[T0:[0-9]+]], $6 238 ; MIPS32R2-NEXT: and $2, $4, $6
114 ; MM32: and16 $[[T1:[0-9]+]], $7 239 ; MIPS32R2-NEXT: jr $ra
115 ; MM32: move $2, $[[T0]] 240 ; MIPS32R2-NEXT: and $3, $5, $7
116 ; MM32: move $3, $[[T1]] 241 ;
117 242 ; MIPS32R6-LABEL: and_i64:
118 ; MM64: and $2, $4, $5 243 ; MIPS32R6: # %bb.0: # %entry
119 244 ; MIPS32R6-NEXT: and $2, $4, $6
245 ; MIPS32R6-NEXT: jr $ra
246 ; MIPS32R6-NEXT: and $3, $5, $7
247 ;
248 ; MIPS64-LABEL: and_i64:
249 ; MIPS64: # %bb.0: # %entry
250 ; MIPS64-NEXT: jr $ra
251 ; MIPS64-NEXT: and $2, $4, $5
252 ;
253 ; MIPS64R2-LABEL: and_i64:
254 ; MIPS64R2: # %bb.0: # %entry
255 ; MIPS64R2-NEXT: jr $ra
256 ; MIPS64R2-NEXT: and $2, $4, $5
257 ;
258 ; MIPS64R6-LABEL: and_i64:
259 ; MIPS64R6: # %bb.0: # %entry
260 ; MIPS64R6-NEXT: jr $ra
261 ; MIPS64R6-NEXT: and $2, $4, $5
262 ;
263 ; MM32R3-LABEL: and_i64:
264 ; MM32R3: # %bb.0: # %entry
265 ; MM32R3-NEXT: and16 $4, $6
266 ; MM32R3-NEXT: and16 $5, $7
267 ; MM32R3-NEXT: move $2, $4
268 ; MM32R3-NEXT: move $3, $5
269 ; MM32R3-NEXT: jrc $ra
270 ;
271 ; MM32R6-LABEL: and_i64:
272 ; MM32R6: # %bb.0: # %entry
273 ; MM32R6-NEXT: and $2, $4, $6
274 ; MM32R6-NEXT: and $3, $5, $7
275 ; MM32R6-NEXT: jrc $ra
276 entry:
120 %r = and i64 %a, %b 277 %r = and i64 %a, %b
121 ret i64 %r 278 ret i64 %r
122 } 279 }
123 280
124 define signext i128 @and_i128(i128 signext %a, i128 signext %b) { 281 define signext i128 @and_i128(i128 signext %a, i128 signext %b) {
125 entry: 282 ; MIPS-LABEL: and_i128:
126 ; ALL-LABEL: and_i128: 283 ; MIPS: # %bb.0: # %entry
127 284 ; MIPS-NEXT: lw $1, 20($sp)
128 ; GP32: lw $[[T0:[0-9]+]], 20($sp) 285 ; MIPS-NEXT: lw $2, 16($sp)
129 ; GP32: lw $[[T1:[0-9]+]], 16($sp) 286 ; MIPS-NEXT: and $2, $4, $2
130 ; GP32: and $2, $4, $[[T1]] 287 ; MIPS-NEXT: and $3, $5, $1
131 ; GP32: and $3, $5, $[[T0]] 288 ; MIPS-NEXT: lw $1, 24($sp)
132 ; GP32: lw $[[T2:[0-9]+]], 24($sp) 289 ; MIPS-NEXT: and $4, $6, $1
133 ; GP32: and $4, $6, $[[T2]] 290 ; MIPS-NEXT: lw $1, 28($sp)
134 ; GP32: lw $[[T3:[0-9]+]], 28($sp) 291 ; MIPS-NEXT: jr $ra
135 ; GP32: and $5, $7, $[[T3]] 292 ; MIPS-NEXT: and $5, $7, $1
136 293 ;
137 ; GP64: and $2, $4, $6 294 ; MIPS32R2-LABEL: and_i128:
138 ; GP64: and $3, $5, $7 295 ; MIPS32R2: # %bb.0: # %entry
139 296 ; MIPS32R2-NEXT: lw $1, 20($sp)
140 ; MM32: lw $[[T0:[0-9]+]], 20($sp) 297 ; MIPS32R2-NEXT: lw $2, 16($sp)
141 ; MM32: lw $[[T1:[0-9]+]], 16($sp) 298 ; MIPS32R2-NEXT: and $2, $4, $2
142 ; MM32: and16 $[[T1]], $4 299 ; MIPS32R2-NEXT: and $3, $5, $1
143 ; MM32: and16 $[[T0]], $5 300 ; MIPS32R2-NEXT: lw $1, 24($sp)
144 ; MM32: lw $[[T2:[0-9]+]], 24($sp) 301 ; MIPS32R2-NEXT: and $4, $6, $1
145 ; MM32: and16 $[[T2]], $6 302 ; MIPS32R2-NEXT: lw $1, 28($sp)
146 ; MM32: lw $[[T3:[0-9]+]], 28($sp) 303 ; MIPS32R2-NEXT: jr $ra
147 ; MM32: and16 $[[T3]], $7 304 ; MIPS32R2-NEXT: and $5, $7, $1
148 305 ;
149 ; MM64: and $2, $4, $6 306 ; MIPS32R6-LABEL: and_i128:
150 ; MM64: and $3, $5, $7 307 ; MIPS32R6: # %bb.0: # %entry
151 308 ; MIPS32R6-NEXT: lw $1, 20($sp)
309 ; MIPS32R6-NEXT: lw $2, 16($sp)
310 ; MIPS32R6-NEXT: and $2, $4, $2
311 ; MIPS32R6-NEXT: and $3, $5, $1
312 ; MIPS32R6-NEXT: lw $1, 24($sp)
313 ; MIPS32R6-NEXT: and $4, $6, $1
314 ; MIPS32R6-NEXT: lw $1, 28($sp)
315 ; MIPS32R6-NEXT: jr $ra
316 ; MIPS32R6-NEXT: and $5, $7, $1
317 ;
318 ; MIPS64-LABEL: and_i128:
319 ; MIPS64: # %bb.0: # %entry
320 ; MIPS64-NEXT: and $2, $4, $6
321 ; MIPS64-NEXT: jr $ra
322 ; MIPS64-NEXT: and $3, $5, $7
323 ;
324 ; MIPS64R2-LABEL: and_i128:
325 ; MIPS64R2: # %bb.0: # %entry
326 ; MIPS64R2-NEXT: and $2, $4, $6
327 ; MIPS64R2-NEXT: jr $ra
328 ; MIPS64R2-NEXT: and $3, $5, $7
329 ;
330 ; MIPS64R6-LABEL: and_i128:
331 ; MIPS64R6: # %bb.0: # %entry
332 ; MIPS64R6-NEXT: and $2, $4, $6
333 ; MIPS64R6-NEXT: jr $ra
334 ; MIPS64R6-NEXT: and $3, $5, $7
335 ;
336 ; MM32R3-LABEL: and_i128:
337 ; MM32R3: # %bb.0: # %entry
338 ; MM32R3-NEXT: lw $3, 20($sp)
339 ; MM32R3-NEXT: lw $2, 16($sp)
340 ; MM32R3-NEXT: and16 $2, $4
341 ; MM32R3-NEXT: and16 $3, $5
342 ; MM32R3-NEXT: lw $4, 24($sp)
343 ; MM32R3-NEXT: and16 $4, $6
344 ; MM32R3-NEXT: lw $5, 28($sp)
345 ; MM32R3-NEXT: and16 $5, $7
346 ; MM32R3-NEXT: jrc $ra
347 ;
348 ; MM32R6-LABEL: and_i128:
349 ; MM32R6: # %bb.0: # %entry
350 ; MM32R6-NEXT: lw $1, 20($sp)
351 ; MM32R6-NEXT: lw $2, 16($sp)
352 ; MM32R6-NEXT: and $2, $4, $2
353 ; MM32R6-NEXT: and $3, $5, $1
354 ; MM32R6-NEXT: lw $1, 24($sp)
355 ; MM32R6-NEXT: and $4, $6, $1
356 ; MM32R6-NEXT: lw $1, 28($sp)
357 ; MM32R6-NEXT: and $5, $7, $1
358 ; MM32R6-NEXT: jrc $ra
359 entry:
152 %r = and i128 %a, %b 360 %r = and i128 %a, %b
153 ret i128 %r 361 ret i128 %r
154 } 362 }
155 363
156 define signext i1 @and_i1_4(i1 signext %b) { 364 define signext i1 @and_i1_4(i1 signext %b) {
157 entry: 365 ; MIPS-LABEL: and_i1_4:
158 ; ALL-LABEL: and_i1_4: 366 ; MIPS: # %bb.0: # %entry
159 367 ; MIPS-NEXT: jr $ra
160 ; GP32: addiu $2, $zero, 0 368 ; MIPS-NEXT: addiu $2, $zero, 0
161 369 ;
162 ; GP64: addiu $2, $zero, 0 370 ; MIPS32R2-LABEL: and_i1_4:
163 371 ; MIPS32R2: # %bb.0: # %entry
164 ; MM: li16 $2, 0 372 ; MIPS32R2-NEXT: jr $ra
165 373 ; MIPS32R2-NEXT: addiu $2, $zero, 0
374 ;
375 ; MIPS32R6-LABEL: and_i1_4:
376 ; MIPS32R6: # %bb.0: # %entry
377 ; MIPS32R6-NEXT: jr $ra
378 ; MIPS32R6-NEXT: addiu $2, $zero, 0
379 ;
380 ; MIPS64-LABEL: and_i1_4:
381 ; MIPS64: # %bb.0: # %entry
382 ; MIPS64-NEXT: jr $ra
383 ; MIPS64-NEXT: addiu $2, $zero, 0
384 ;
385 ; MIPS64R2-LABEL: and_i1_4:
386 ; MIPS64R2: # %bb.0: # %entry
387 ; MIPS64R2-NEXT: jr $ra
388 ; MIPS64R2-NEXT: addiu $2, $zero, 0
389 ;
390 ; MIPS64R6-LABEL: and_i1_4:
391 ; MIPS64R6: # %bb.0: # %entry
392 ; MIPS64R6-NEXT: jr $ra
393 ; MIPS64R6-NEXT: addiu $2, $zero, 0
394 ;
395 ; MM32R3-LABEL: and_i1_4:
396 ; MM32R3: # %bb.0: # %entry
397 ; MM32R3-NEXT: li16 $2, 0
398 ; MM32R3-NEXT: jrc $ra
399 ;
400 ; MM32R6-LABEL: and_i1_4:
401 ; MM32R6: # %bb.0: # %entry
402 ; MM32R6-NEXT: li16 $2, 0
403 ; MM32R6-NEXT: jrc $ra
404 entry:
166 %r = and i1 4, %b 405 %r = and i1 4, %b
167 ret i1 %r 406 ret i1 %r
168 } 407 }
169 408
170 define signext i8 @and_i8_4(i8 signext %b) { 409 define signext i8 @and_i8_4(i8 signext %b) {
171 entry: 410 ; MIPS-LABEL: and_i8_4:
172 ; ALL-LABEL: and_i8_4: 411 ; MIPS: # %bb.0: # %entry
173 412 ; MIPS-NEXT: jr $ra
174 ; GP32: andi $2, $4, 4 413 ; MIPS-NEXT: andi $2, $4, 4
175 414 ;
176 ; GP64: andi $2, $4, 4 415 ; MIPS32R2-LABEL: and_i8_4:
177 416 ; MIPS32R2: # %bb.0: # %entry
178 ; MM: andi16 $2, $4, 4 417 ; MIPS32R2-NEXT: jr $ra
179 418 ; MIPS32R2-NEXT: andi $2, $4, 4
419 ;
420 ; MIPS32R6-LABEL: and_i8_4:
421 ; MIPS32R6: # %bb.0: # %entry
422 ; MIPS32R6-NEXT: jr $ra
423 ; MIPS32R6-NEXT: andi $2, $4, 4
424 ;
425 ; MIPS64-LABEL: and_i8_4:
426 ; MIPS64: # %bb.0: # %entry
427 ; MIPS64-NEXT: jr $ra
428 ; MIPS64-NEXT: andi $2, $4, 4
429 ;
430 ; MIPS64R2-LABEL: and_i8_4:
431 ; MIPS64R2: # %bb.0: # %entry
432 ; MIPS64R2-NEXT: jr $ra
433 ; MIPS64R2-NEXT: andi $2, $4, 4
434 ;
435 ; MIPS64R6-LABEL: and_i8_4:
436 ; MIPS64R6: # %bb.0: # %entry
437 ; MIPS64R6-NEXT: jr $ra
438 ; MIPS64R6-NEXT: andi $2, $4, 4
439 ;
440 ; MM32R3-LABEL: and_i8_4:
441 ; MM32R3: # %bb.0: # %entry
442 ; MM32R3-NEXT: andi16 $2, $4, 4
443 ; MM32R3-NEXT: jrc $ra
444 ;
445 ; MM32R6-LABEL: and_i8_4:
446 ; MM32R6: # %bb.0: # %entry
447 ; MM32R6-NEXT: andi16 $2, $4, 4
448 ; MM32R6-NEXT: jrc $ra
449 entry:
180 %r = and i8 4, %b 450 %r = and i8 4, %b
181 ret i8 %r 451 ret i8 %r
182 } 452 }
183 453
184 define signext i16 @and_i16_4(i16 signext %b) { 454 define signext i16 @and_i16_4(i16 signext %b) {
185 entry: 455 ; MIPS-LABEL: and_i16_4:
186 ; ALL-LABEL: and_i16_4: 456 ; MIPS: # %bb.0: # %entry
187 457 ; MIPS-NEXT: jr $ra
188 ; GP32: andi $2, $4, 4 458 ; MIPS-NEXT: andi $2, $4, 4
189 459 ;
190 ; GP64: andi $2, $4, 4 460 ; MIPS32R2-LABEL: and_i16_4:
191 461 ; MIPS32R2: # %bb.0: # %entry
192 ; MM: andi16 $2, $4, 4 462 ; MIPS32R2-NEXT: jr $ra
193 463 ; MIPS32R2-NEXT: andi $2, $4, 4
464 ;
465 ; MIPS32R6-LABEL: and_i16_4:
466 ; MIPS32R6: # %bb.0: # %entry
467 ; MIPS32R6-NEXT: jr $ra
468 ; MIPS32R6-NEXT: andi $2, $4, 4
469 ;
470 ; MIPS64-LABEL: and_i16_4:
471 ; MIPS64: # %bb.0: # %entry
472 ; MIPS64-NEXT: jr $ra
473 ; MIPS64-NEXT: andi $2, $4, 4
474 ;
475 ; MIPS64R2-LABEL: and_i16_4:
476 ; MIPS64R2: # %bb.0: # %entry
477 ; MIPS64R2-NEXT: jr $ra
478 ; MIPS64R2-NEXT: andi $2, $4, 4
479 ;
480 ; MIPS64R6-LABEL: and_i16_4:
481 ; MIPS64R6: # %bb.0: # %entry
482 ; MIPS64R6-NEXT: jr $ra
483 ; MIPS64R6-NEXT: andi $2, $4, 4
484 ;
485 ; MM32R3-LABEL: and_i16_4:
486 ; MM32R3: # %bb.0: # %entry
487 ; MM32R3-NEXT: andi16 $2, $4, 4
488 ; MM32R3-NEXT: jrc $ra
489 ;
490 ; MM32R6-LABEL: and_i16_4:
491 ; MM32R6: # %bb.0: # %entry
492 ; MM32R6-NEXT: andi16 $2, $4, 4
493 ; MM32R6-NEXT: jrc $ra
494 entry:
194 %r = and i16 4, %b 495 %r = and i16 4, %b
195 ret i16 %r 496 ret i16 %r
196 } 497 }
197 498
198 define signext i32 @and_i32_4(i32 signext %b) { 499 define signext i32 @and_i32_4(i32 signext %b) {
199 entry: 500 ; MIPS-LABEL: and_i32_4:
200 ; ALL-LABEL: and_i32_4: 501 ; MIPS: # %bb.0: # %entry
201 502 ; MIPS-NEXT: jr $ra
202 ; GP32: andi $2, $4, 4 503 ; MIPS-NEXT: andi $2, $4, 4
203 504 ;
204 ; GP64: andi $2, $4, 4 505 ; MIPS32R2-LABEL: and_i32_4:
205 506 ; MIPS32R2: # %bb.0: # %entry
206 ; MM: andi16 $2, $4, 4 507 ; MIPS32R2-NEXT: jr $ra
207 508 ; MIPS32R2-NEXT: andi $2, $4, 4
509 ;
510 ; MIPS32R6-LABEL: and_i32_4:
511 ; MIPS32R6: # %bb.0: # %entry
512 ; MIPS32R6-NEXT: jr $ra
513 ; MIPS32R6-NEXT: andi $2, $4, 4
514 ;
515 ; MIPS64-LABEL: and_i32_4:
516 ; MIPS64: # %bb.0: # %entry
517 ; MIPS64-NEXT: jr $ra
518 ; MIPS64-NEXT: andi $2, $4, 4
519 ;
520 ; MIPS64R2-LABEL: and_i32_4:
521 ; MIPS64R2: # %bb.0: # %entry
522 ; MIPS64R2-NEXT: jr $ra
523 ; MIPS64R2-NEXT: andi $2, $4, 4
524 ;
525 ; MIPS64R6-LABEL: and_i32_4:
526 ; MIPS64R6: # %bb.0: # %entry
527 ; MIPS64R6-NEXT: jr $ra
528 ; MIPS64R6-NEXT: andi $2, $4, 4
529 ;
530 ; MM32R3-LABEL: and_i32_4:
531 ; MM32R3: # %bb.0: # %entry
532 ; MM32R3-NEXT: andi16 $2, $4, 4
533 ; MM32R3-NEXT: jrc $ra
534 ;
535 ; MM32R6-LABEL: and_i32_4:
536 ; MM32R6: # %bb.0: # %entry
537 ; MM32R6-NEXT: andi16 $2, $4, 4
538 ; MM32R6-NEXT: jrc $ra
539 entry:
208 %r = and i32 4, %b 540 %r = and i32 4, %b
209 ret i32 %r 541 ret i32 %r
210 } 542 }
211 543
212 define signext i64 @and_i64_4(i64 signext %b) { 544 define signext i64 @and_i64_4(i64 signext %b) {
213 entry: 545 ; MIPS-LABEL: and_i64_4:
214 ; ALL-LABEL: and_i64_4: 546 ; MIPS: # %bb.0: # %entry
215 547 ; MIPS-NEXT: andi $3, $5, 4
216 ; GP32: andi $3, $5, 4 548 ; MIPS-NEXT: jr $ra
217 ; GP32: addiu $2, $zero, 0 549 ; MIPS-NEXT: addiu $2, $zero, 0
218 550 ;
219 ; GP64: andi $2, $4, 4 551 ; MIPS32R2-LABEL: and_i64_4:
220 552 ; MIPS32R2: # %bb.0: # %entry
221 ; MM32: andi16 $3, $5, 4 553 ; MIPS32R2-NEXT: andi $3, $5, 4
222 ; MM32: li16 $2, 0 554 ; MIPS32R2-NEXT: jr $ra
223 555 ; MIPS32R2-NEXT: addiu $2, $zero, 0
224 ; MM64: andi $2, $4, 4 556 ;
225 557 ; MIPS32R6-LABEL: and_i64_4:
558 ; MIPS32R6: # %bb.0: # %entry
559 ; MIPS32R6-NEXT: andi $3, $5, 4
560 ; MIPS32R6-NEXT: jr $ra
561 ; MIPS32R6-NEXT: addiu $2, $zero, 0
562 ;
563 ; MIPS64-LABEL: and_i64_4:
564 ; MIPS64: # %bb.0: # %entry
565 ; MIPS64-NEXT: jr $ra
566 ; MIPS64-NEXT: andi $2, $4, 4
567 ;
568 ; MIPS64R2-LABEL: and_i64_4:
569 ; MIPS64R2: # %bb.0: # %entry
570 ; MIPS64R2-NEXT: jr $ra
571 ; MIPS64R2-NEXT: andi $2, $4, 4
572 ;
573 ; MIPS64R6-LABEL: and_i64_4:
574 ; MIPS64R6: # %bb.0: # %entry
575 ; MIPS64R6-NEXT: jr $ra
576 ; MIPS64R6-NEXT: andi $2, $4, 4
577 ;
578 ; MM32R3-LABEL: and_i64_4:
579 ; MM32R3: # %bb.0: # %entry
580 ; MM32R3-NEXT: andi16 $3, $5, 4
581 ; MM32R3-NEXT: li16 $2, 0
582 ; MM32R3-NEXT: jrc $ra
583 ;
584 ; MM32R6-LABEL: and_i64_4:
585 ; MM32R6: # %bb.0: # %entry
586 ; MM32R6-NEXT: andi16 $3, $5, 4
587 ; MM32R6-NEXT: li16 $2, 0
588 ; MM32R6-NEXT: jrc $ra
589 entry:
226 %r = and i64 4, %b 590 %r = and i64 4, %b
227 ret i64 %r 591 ret i64 %r
228 } 592 }
229 593
230 define signext i128 @and_i128_4(i128 signext %b) { 594 define signext i128 @and_i128_4(i128 signext %b) {
231 entry: 595 ; MIPS-LABEL: and_i128_4:
232 ; ALL-LABEL: and_i128_4: 596 ; MIPS: # %bb.0: # %entry
233 597 ; MIPS-NEXT: andi $5, $7, 4
234 ; GP32: andi $5, $7, 4 598 ; MIPS-NEXT: addiu $2, $zero, 0
235 ; GP32: addiu $2, $zero, 0 599 ; MIPS-NEXT: addiu $3, $zero, 0
236 ; GP32: addiu $3, $zero, 0 600 ; MIPS-NEXT: jr $ra
237 ; GP32: addiu $4, $zero, 0 601 ; MIPS-NEXT: addiu $4, $zero, 0
238 602 ;
239 ; GP64: andi $3, $5, 4 603 ; MIPS32R2-LABEL: and_i128_4:
240 ; GP64: daddiu $2, $zero, 0 604 ; MIPS32R2: # %bb.0: # %entry
241 605 ; MIPS32R2-NEXT: andi $5, $7, 4
242 ; MM32: andi16 $5, $7, 4 606 ; MIPS32R2-NEXT: addiu $2, $zero, 0
243 ; MM32: li16 $2, 0 607 ; MIPS32R2-NEXT: addiu $3, $zero, 0
244 ; MM32: li16 $3, 0 608 ; MIPS32R2-NEXT: jr $ra
245 ; MM32: li16 $4, 0 609 ; MIPS32R2-NEXT: addiu $4, $zero, 0
246 610 ;
247 ; MM64: andi $3, $5, 4 611 ; MIPS32R6-LABEL: and_i128_4:
248 ; MM64: daddiu $2, $zero, 0 612 ; MIPS32R6: # %bb.0: # %entry
249 613 ; MIPS32R6-NEXT: andi $5, $7, 4
614 ; MIPS32R6-NEXT: addiu $2, $zero, 0
615 ; MIPS32R6-NEXT: addiu $3, $zero, 0
616 ; MIPS32R6-NEXT: jr $ra
617 ; MIPS32R6-NEXT: addiu $4, $zero, 0
618 ;
619 ; MIPS64-LABEL: and_i128_4:
620 ; MIPS64: # %bb.0: # %entry
621 ; MIPS64-NEXT: andi $3, $5, 4
622 ; MIPS64-NEXT: jr $ra
623 ; MIPS64-NEXT: daddiu $2, $zero, 0
624 ;
625 ; MIPS64R2-LABEL: and_i128_4:
626 ; MIPS64R2: # %bb.0: # %entry
627 ; MIPS64R2-NEXT: andi $3, $5, 4
628 ; MIPS64R2-NEXT: jr $ra
629 ; MIPS64R2-NEXT: daddiu $2, $zero, 0
630 ;
631 ; MIPS64R6-LABEL: and_i128_4:
632 ; MIPS64R6: # %bb.0: # %entry
633 ; MIPS64R6-NEXT: andi $3, $5, 4
634 ; MIPS64R6-NEXT: jr $ra
635 ; MIPS64R6-NEXT: daddiu $2, $zero, 0
636 ;
637 ; MM32R3-LABEL: and_i128_4:
638 ; MM32R3: # %bb.0: # %entry
639 ; MM32R3-NEXT: andi16 $5, $7, 4
640 ; MM32R3-NEXT: li16 $2, 0
641 ; MM32R3-NEXT: li16 $3, 0
642 ; MM32R3-NEXT: li16 $4, 0
643 ; MM32R3-NEXT: jrc $ra
644 ;
645 ; MM32R6-LABEL: and_i128_4:
646 ; MM32R6: # %bb.0: # %entry
647 ; MM32R6-NEXT: andi16 $5, $7, 4
648 ; MM32R6-NEXT: li16 $2, 0
649 ; MM32R6-NEXT: li16 $3, 0
650 ; MM32R6-NEXT: li16 $4, 0
651 ; MM32R6-NEXT: jrc $ra
652 entry:
250 %r = and i128 4, %b 653 %r = and i128 4, %b
251 ret i128 %r 654 ret i128 %r
252 } 655 }
253 656
254 define signext i1 @and_i1_31(i1 signext %b) { 657 define signext i1 @and_i1_31(i1 signext %b) {
255 entry: 658 ; MIPS-LABEL: and_i1_31:
256 ; ALL-LABEL: and_i1_31: 659 ; MIPS: # %bb.0: # %entry
257 660 ; MIPS-NEXT: jr $ra
258 ; ALL: move $2, $4 661 ; MIPS-NEXT: move $2, $4
259 662 ;
663 ; MIPS32R2-LABEL: and_i1_31:
664 ; MIPS32R2: # %bb.0: # %entry
665 ; MIPS32R2-NEXT: jr $ra
666 ; MIPS32R2-NEXT: move $2, $4
667 ;
668 ; MIPS32R6-LABEL: and_i1_31:
669 ; MIPS32R6: # %bb.0: # %entry
670 ; MIPS32R6-NEXT: jr $ra
671 ; MIPS32R6-NEXT: move $2, $4
672 ;
673 ; MIPS64-LABEL: and_i1_31:
674 ; MIPS64: # %bb.0: # %entry
675 ; MIPS64-NEXT: jr $ra
676 ; MIPS64-NEXT: move $2, $4
677 ;
678 ; MIPS64R2-LABEL: and_i1_31:
679 ; MIPS64R2: # %bb.0: # %entry
680 ; MIPS64R2-NEXT: jr $ra
681 ; MIPS64R2-NEXT: move $2, $4
682 ;
683 ; MIPS64R6-LABEL: and_i1_31:
684 ; MIPS64R6: # %bb.0: # %entry
685 ; MIPS64R6-NEXT: jr $ra
686 ; MIPS64R6-NEXT: move $2, $4
687 ;
688 ; MM32R3-LABEL: and_i1_31:
689 ; MM32R3: # %bb.0: # %entry
690 ; MM32R3-NEXT: move $2, $4
691 ; MM32R3-NEXT: jrc $ra
692 ;
693 ; MM32R6-LABEL: and_i1_31:
694 ; MM32R6: # %bb.0: # %entry
695 ; MM32R6-NEXT: move $2, $4
696 ; MM32R6-NEXT: jrc $ra
697 entry:
260 %r = and i1 31, %b 698 %r = and i1 31, %b
261 ret i1 %r 699 ret i1 %r
262 } 700 }
263 701
264 define signext i8 @and_i8_31(i8 signext %b) { 702 define signext i8 @and_i8_31(i8 signext %b) {
265 entry: 703 ; MIPS-LABEL: and_i8_31:
266 ; ALL-LABEL: and_i8_31: 704 ; MIPS: # %bb.0: # %entry
267 705 ; MIPS-NEXT: jr $ra
268 ; GP32: andi $2, $4, 31 706 ; MIPS-NEXT: andi $2, $4, 31
269 707 ;
270 ; GP64: andi $2, $4, 31 708 ; MIPS32R2-LABEL: and_i8_31:
271 709 ; MIPS32R2: # %bb.0: # %entry
272 ; MM: andi16 $2, $4, 31 710 ; MIPS32R2-NEXT: jr $ra
273 711 ; MIPS32R2-NEXT: andi $2, $4, 31
712 ;
713 ; MIPS32R6-LABEL: and_i8_31:
714 ; MIPS32R6: # %bb.0: # %entry
715 ; MIPS32R6-NEXT: jr $ra
716 ; MIPS32R6-NEXT: andi $2, $4, 31
717 ;
718 ; MIPS64-LABEL: and_i8_31:
719 ; MIPS64: # %bb.0: # %entry
720 ; MIPS64-NEXT: jr $ra
721 ; MIPS64-NEXT: andi $2, $4, 31
722 ;
723 ; MIPS64R2-LABEL: and_i8_31:
724 ; MIPS64R2: # %bb.0: # %entry
725 ; MIPS64R2-NEXT: jr $ra
726 ; MIPS64R2-NEXT: andi $2, $4, 31
727 ;
728 ; MIPS64R6-LABEL: and_i8_31:
729 ; MIPS64R6: # %bb.0: # %entry
730 ; MIPS64R6-NEXT: jr $ra
731 ; MIPS64R6-NEXT: andi $2, $4, 31
732 ;
733 ; MM32R3-LABEL: and_i8_31:
734 ; MM32R3: # %bb.0: # %entry
735 ; MM32R3-NEXT: andi16 $2, $4, 31
736 ; MM32R3-NEXT: jrc $ra
737 ;
738 ; MM32R6-LABEL: and_i8_31:
739 ; MM32R6: # %bb.0: # %entry
740 ; MM32R6-NEXT: andi16 $2, $4, 31
741 ; MM32R6-NEXT: jrc $ra
742 entry:
274 %r = and i8 31, %b 743 %r = and i8 31, %b
275 ret i8 %r 744 ret i8 %r
276 } 745 }
277 746
278 define signext i16 @and_i16_31(i16 signext %b) { 747 define signext i16 @and_i16_31(i16 signext %b) {
279 entry: 748 ; MIPS-LABEL: and_i16_31:
280 ; ALL-LABEL: and_i16_31: 749 ; MIPS: # %bb.0: # %entry
281 750 ; MIPS-NEXT: jr $ra
282 ; GP32: andi $2, $4, 31 751 ; MIPS-NEXT: andi $2, $4, 31
283 752 ;
284 ; GP64: andi $2, $4, 31 753 ; MIPS32R2-LABEL: and_i16_31:
285 754 ; MIPS32R2: # %bb.0: # %entry
286 ; MM: andi16 $2, $4, 31 755 ; MIPS32R2-NEXT: jr $ra
287 756 ; MIPS32R2-NEXT: andi $2, $4, 31
757 ;
758 ; MIPS32R6-LABEL: and_i16_31:
759 ; MIPS32R6: # %bb.0: # %entry
760 ; MIPS32R6-NEXT: jr $ra
761 ; MIPS32R6-NEXT: andi $2, $4, 31
762 ;
763 ; MIPS64-LABEL: and_i16_31:
764 ; MIPS64: # %bb.0: # %entry
765 ; MIPS64-NEXT: jr $ra
766 ; MIPS64-NEXT: andi $2, $4, 31
767 ;
768 ; MIPS64R2-LABEL: and_i16_31:
769 ; MIPS64R2: # %bb.0: # %entry
770 ; MIPS64R2-NEXT: jr $ra
771 ; MIPS64R2-NEXT: andi $2, $4, 31
772 ;
773 ; MIPS64R6-LABEL: and_i16_31:
774 ; MIPS64R6: # %bb.0: # %entry
775 ; MIPS64R6-NEXT: jr $ra
776 ; MIPS64R6-NEXT: andi $2, $4, 31
777 ;
778 ; MM32R3-LABEL: and_i16_31:
779 ; MM32R3: # %bb.0: # %entry
780 ; MM32R3-NEXT: andi16 $2, $4, 31
781 ; MM32R3-NEXT: jrc $ra
782 ;
783 ; MM32R6-LABEL: and_i16_31:
784 ; MM32R6: # %bb.0: # %entry
785 ; MM32R6-NEXT: andi16 $2, $4, 31
786 ; MM32R6-NEXT: jrc $ra
787 entry:
288 %r = and i16 31, %b 788 %r = and i16 31, %b
289 ret i16 %r 789 ret i16 %r
290 } 790 }
291 791
292 define signext i32 @and_i32_31(i32 signext %b) { 792 define signext i32 @and_i32_31(i32 signext %b) {
293 entry: 793 ; MIPS-LABEL: and_i32_31:
294 ; ALL-LABEL: and_i32_31: 794 ; MIPS: # %bb.0: # %entry
295 795 ; MIPS-NEXT: jr $ra
296 ; GP32: andi $2, $4, 31 796 ; MIPS-NEXT: andi $2, $4, 31
297 797 ;
298 ; GP64: andi $2, $4, 31 798 ; MIPS32R2-LABEL: and_i32_31:
299 799 ; MIPS32R2: # %bb.0: # %entry
300 ; MM: andi16 $2, $4, 31 800 ; MIPS32R2-NEXT: jr $ra
301 801 ; MIPS32R2-NEXT: andi $2, $4, 31
802 ;
803 ; MIPS32R6-LABEL: and_i32_31:
804 ; MIPS32R6: # %bb.0: # %entry
805 ; MIPS32R6-NEXT: jr $ra
806 ; MIPS32R6-NEXT: andi $2, $4, 31
807 ;
808 ; MIPS64-LABEL: and_i32_31:
809 ; MIPS64: # %bb.0: # %entry
810 ; MIPS64-NEXT: jr $ra
811 ; MIPS64-NEXT: andi $2, $4, 31
812 ;
813 ; MIPS64R2-LABEL: and_i32_31:
814 ; MIPS64R2: # %bb.0: # %entry
815 ; MIPS64R2-NEXT: jr $ra
816 ; MIPS64R2-NEXT: andi $2, $4, 31
817 ;
818 ; MIPS64R6-LABEL: and_i32_31:
819 ; MIPS64R6: # %bb.0: # %entry
820 ; MIPS64R6-NEXT: jr $ra
821 ; MIPS64R6-NEXT: andi $2, $4, 31
822 ;
823 ; MM32R3-LABEL: and_i32_31:
824 ; MM32R3: # %bb.0: # %entry
825 ; MM32R3-NEXT: andi16 $2, $4, 31
826 ; MM32R3-NEXT: jrc $ra
827 ;
828 ; MM32R6-LABEL: and_i32_31:
829 ; MM32R6: # %bb.0: # %entry
830 ; MM32R6-NEXT: andi16 $2, $4, 31
831 ; MM32R6-NEXT: jrc $ra
832 entry:
302 %r = and i32 31, %b 833 %r = and i32 31, %b
303 ret i32 %r 834 ret i32 %r
304 } 835 }
305 836
306 define signext i64 @and_i64_31(i64 signext %b) { 837 define signext i64 @and_i64_31(i64 signext %b) {
307 entry: 838 ; MIPS-LABEL: and_i64_31:
308 ; ALL-LABEL: and_i64_31: 839 ; MIPS: # %bb.0: # %entry
309 840 ; MIPS-NEXT: andi $3, $5, 31
310 ; GP32: andi $3, $5, 31 841 ; MIPS-NEXT: jr $ra
311 ; GP32: addiu $2, $zero, 0 842 ; MIPS-NEXT: addiu $2, $zero, 0
312 843 ;
313 ; GP64: andi $2, $4, 31 844 ; MIPS32R2-LABEL: and_i64_31:
314 845 ; MIPS32R2: # %bb.0: # %entry
315 ; MM32: andi16 $3, $5, 31 846 ; MIPS32R2-NEXT: andi $3, $5, 31
316 ; MM32: li16 $2, 0 847 ; MIPS32R2-NEXT: jr $ra
317 848 ; MIPS32R2-NEXT: addiu $2, $zero, 0
318 ; MM64: andi $2, $4, 31 849 ;
319 850 ; MIPS32R6-LABEL: and_i64_31:
851 ; MIPS32R6: # %bb.0: # %entry
852 ; MIPS32R6-NEXT: andi $3, $5, 31
853 ; MIPS32R6-NEXT: jr $ra
854 ; MIPS32R6-NEXT: addiu $2, $zero, 0
855 ;
856 ; MIPS64-LABEL: and_i64_31:
857 ; MIPS64: # %bb.0: # %entry
858 ; MIPS64-NEXT: jr $ra
859 ; MIPS64-NEXT: andi $2, $4, 31
860 ;
861 ; MIPS64R2-LABEL: and_i64_31:
862 ; MIPS64R2: # %bb.0: # %entry
863 ; MIPS64R2-NEXT: jr $ra
864 ; MIPS64R2-NEXT: andi $2, $4, 31
865 ;
866 ; MIPS64R6-LABEL: and_i64_31:
867 ; MIPS64R6: # %bb.0: # %entry
868 ; MIPS64R6-NEXT: jr $ra
869 ; MIPS64R6-NEXT: andi $2, $4, 31
870 ;
871 ; MM32R3-LABEL: and_i64_31:
872 ; MM32R3: # %bb.0: # %entry
873 ; MM32R3-NEXT: andi16 $3, $5, 31
874 ; MM32R3-NEXT: li16 $2, 0
875 ; MM32R3-NEXT: jrc $ra
876 ;
877 ; MM32R6-LABEL: and_i64_31:
878 ; MM32R6: # %bb.0: # %entry
879 ; MM32R6-NEXT: andi16 $3, $5, 31
880 ; MM32R6-NEXT: li16 $2, 0
881 ; MM32R6-NEXT: jrc $ra
882 entry:
320 %r = and i64 31, %b 883 %r = and i64 31, %b
321 ret i64 %r 884 ret i64 %r
322 } 885 }
323 886
324 define signext i128 @and_i128_31(i128 signext %b) { 887 define signext i128 @and_i128_31(i128 signext %b) {
325 entry: 888 ; MIPS-LABEL: and_i128_31:
326 ; ALL-LABEL: and_i128_31: 889 ; MIPS: # %bb.0: # %entry
327 890 ; MIPS-NEXT: andi $5, $7, 31
328 ; GP32: andi $5, $7, 31 891 ; MIPS-NEXT: addiu $2, $zero, 0
329 ; GP32: addiu $2, $zero, 0 892 ; MIPS-NEXT: addiu $3, $zero, 0
330 ; GP32: addiu $3, $zero, 0 893 ; MIPS-NEXT: jr $ra
331 ; GP32: addiu $4, $zero, 0 894 ; MIPS-NEXT: addiu $4, $zero, 0
332 895 ;
333 ; GP64: andi $3, $5, 31 896 ; MIPS32R2-LABEL: and_i128_31:
334 ; GP64: daddiu $2, $zero, 0 897 ; MIPS32R2: # %bb.0: # %entry
335 898 ; MIPS32R2-NEXT: andi $5, $7, 31
336 ; MM32: andi16 $5, $7, 31 899 ; MIPS32R2-NEXT: addiu $2, $zero, 0
337 ; MM32: li16 $2, 0 900 ; MIPS32R2-NEXT: addiu $3, $zero, 0
338 ; MM32: li16 $3, 0 901 ; MIPS32R2-NEXT: jr $ra
339 ; MM32: li16 $4, 0 902 ; MIPS32R2-NEXT: addiu $4, $zero, 0
340 903 ;
341 ; MM64: andi $3, $5, 31 904 ; MIPS32R6-LABEL: and_i128_31:
342 ; MM64: daddiu $2, $zero, 0 905 ; MIPS32R6: # %bb.0: # %entry
343 906 ; MIPS32R6-NEXT: andi $5, $7, 31
907 ; MIPS32R6-NEXT: addiu $2, $zero, 0
908 ; MIPS32R6-NEXT: addiu $3, $zero, 0
909 ; MIPS32R6-NEXT: jr $ra
910 ; MIPS32R6-NEXT: addiu $4, $zero, 0
911 ;
912 ; MIPS64-LABEL: and_i128_31:
913 ; MIPS64: # %bb.0: # %entry
914 ; MIPS64-NEXT: andi $3, $5, 31
915 ; MIPS64-NEXT: jr $ra
916 ; MIPS64-NEXT: daddiu $2, $zero, 0
917 ;
918 ; MIPS64R2-LABEL: and_i128_31:
919 ; MIPS64R2: # %bb.0: # %entry
920 ; MIPS64R2-NEXT: andi $3, $5, 31
921 ; MIPS64R2-NEXT: jr $ra
922 ; MIPS64R2-NEXT: daddiu $2, $zero, 0
923 ;
924 ; MIPS64R6-LABEL: and_i128_31:
925 ; MIPS64R6: # %bb.0: # %entry
926 ; MIPS64R6-NEXT: andi $3, $5, 31
927 ; MIPS64R6-NEXT: jr $ra
928 ; MIPS64R6-NEXT: daddiu $2, $zero, 0
929 ;
930 ; MM32R3-LABEL: and_i128_31:
931 ; MM32R3: # %bb.0: # %entry
932 ; MM32R3-NEXT: andi16 $5, $7, 31
933 ; MM32R3-NEXT: li16 $2, 0
934 ; MM32R3-NEXT: li16 $3, 0
935 ; MM32R3-NEXT: li16 $4, 0
936 ; MM32R3-NEXT: jrc $ra
937 ;
938 ; MM32R6-LABEL: and_i128_31:
939 ; MM32R6: # %bb.0: # %entry
940 ; MM32R6-NEXT: andi16 $5, $7, 31
941 ; MM32R6-NEXT: li16 $2, 0
942 ; MM32R6-NEXT: li16 $3, 0
943 ; MM32R6-NEXT: li16 $4, 0
944 ; MM32R6-NEXT: jrc $ra
945 entry:
344 %r = and i128 31, %b 946 %r = and i128 31, %b
345 ret i128 %r 947 ret i128 %r
346 } 948 }
347 949
348 define signext i1 @and_i1_255(i1 signext %b) { 950 define signext i1 @and_i1_255(i1 signext %b) {
349 entry: 951 ; MIPS-LABEL: and_i1_255:
350 ; ALL-LABEL: and_i1_255: 952 ; MIPS: # %bb.0: # %entry
351 953 ; MIPS-NEXT: jr $ra
352 ; ALL: move $2, $4 954 ; MIPS-NEXT: move $2, $4
353 955 ;
956 ; MIPS32R2-LABEL: and_i1_255:
957 ; MIPS32R2: # %bb.0: # %entry
958 ; MIPS32R2-NEXT: jr $ra
959 ; MIPS32R2-NEXT: move $2, $4
960 ;
961 ; MIPS32R6-LABEL: and_i1_255:
962 ; MIPS32R6: # %bb.0: # %entry
963 ; MIPS32R6-NEXT: jr $ra
964 ; MIPS32R6-NEXT: move $2, $4
965 ;
966 ; MIPS64-LABEL: and_i1_255:
967 ; MIPS64: # %bb.0: # %entry
968 ; MIPS64-NEXT: jr $ra
969 ; MIPS64-NEXT: move $2, $4
970 ;
971 ; MIPS64R2-LABEL: and_i1_255:
972 ; MIPS64R2: # %bb.0: # %entry
973 ; MIPS64R2-NEXT: jr $ra
974 ; MIPS64R2-NEXT: move $2, $4
975 ;
976 ; MIPS64R6-LABEL: and_i1_255:
977 ; MIPS64R6: # %bb.0: # %entry
978 ; MIPS64R6-NEXT: jr $ra
979 ; MIPS64R6-NEXT: move $2, $4
980 ;
981 ; MM32R3-LABEL: and_i1_255:
982 ; MM32R3: # %bb.0: # %entry
983 ; MM32R3-NEXT: move $2, $4
984 ; MM32R3-NEXT: jrc $ra
985 ;
986 ; MM32R6-LABEL: and_i1_255:
987 ; MM32R6: # %bb.0: # %entry
988 ; MM32R6-NEXT: move $2, $4
989 ; MM32R6-NEXT: jrc $ra
990 entry:
354 %r = and i1 255, %b 991 %r = and i1 255, %b
355 ret i1 %r 992 ret i1 %r
356 } 993 }
357 994
358 define signext i8 @and_i8_255(i8 signext %b) { 995 define signext i8 @and_i8_255(i8 signext %b) {
359 entry: 996 ; MIPS-LABEL: and_i8_255:
360 ; ALL-LABEL: and_i8_255: 997 ; MIPS: # %bb.0: # %entry
361 998 ; MIPS-NEXT: jr $ra
362 ; ALL: move $2, $4 999 ; MIPS-NEXT: move $2, $4
363 1000 ;
1001 ; MIPS32R2-LABEL: and_i8_255:
1002 ; MIPS32R2: # %bb.0: # %entry
1003 ; MIPS32R2-NEXT: jr $ra
1004 ; MIPS32R2-NEXT: move $2, $4
1005 ;
1006 ; MIPS32R6-LABEL: and_i8_255:
1007 ; MIPS32R6: # %bb.0: # %entry
1008 ; MIPS32R6-NEXT: jr $ra
1009 ; MIPS32R6-NEXT: move $2, $4
1010 ;
1011 ; MIPS64-LABEL: and_i8_255:
1012 ; MIPS64: # %bb.0: # %entry
1013 ; MIPS64-NEXT: jr $ra
1014 ; MIPS64-NEXT: move $2, $4
1015 ;
1016 ; MIPS64R2-LABEL: and_i8_255:
1017 ; MIPS64R2: # %bb.0: # %entry
1018 ; MIPS64R2-NEXT: jr $ra
1019 ; MIPS64R2-NEXT: move $2, $4
1020 ;
1021 ; MIPS64R6-LABEL: and_i8_255:
1022 ; MIPS64R6: # %bb.0: # %entry
1023 ; MIPS64R6-NEXT: jr $ra
1024 ; MIPS64R6-NEXT: move $2, $4
1025 ;
1026 ; MM32R3-LABEL: and_i8_255:
1027 ; MM32R3: # %bb.0: # %entry
1028 ; MM32R3-NEXT: move $2, $4
1029 ; MM32R3-NEXT: jrc $ra
1030 ;
1031 ; MM32R6-LABEL: and_i8_255:
1032 ; MM32R6: # %bb.0: # %entry
1033 ; MM32R6-NEXT: move $2, $4
1034 ; MM32R6-NEXT: jrc $ra
1035 entry:
364 %r = and i8 255, %b 1036 %r = and i8 255, %b
365 ret i8 %r 1037 ret i8 %r
366 } 1038 }
367 1039
368 define signext i16 @and_i16_255(i16 signext %b) { 1040 define signext i16 @and_i16_255(i16 signext %b) {
369 entry: 1041 ; MIPS-LABEL: and_i16_255:
370 ; ALL-LABEL: and_i16_255: 1042 ; MIPS: # %bb.0: # %entry
371 1043 ; MIPS-NEXT: jr $ra
372 ; GP32: andi $2, $4, 255 1044 ; MIPS-NEXT: andi $2, $4, 255
373 1045 ;
374 ; GP64: andi $2, $4, 255 1046 ; MIPS32R2-LABEL: and_i16_255:
375 1047 ; MIPS32R2: # %bb.0: # %entry
376 ; MM: andi16 $2, $4, 255 1048 ; MIPS32R2-NEXT: jr $ra
377 1049 ; MIPS32R2-NEXT: andi $2, $4, 255
1050 ;
1051 ; MIPS32R6-LABEL: and_i16_255:
1052 ; MIPS32R6: # %bb.0: # %entry
1053 ; MIPS32R6-NEXT: jr $ra
1054 ; MIPS32R6-NEXT: andi $2, $4, 255
1055 ;
1056 ; MIPS64-LABEL: and_i16_255:
1057 ; MIPS64: # %bb.0: # %entry
1058 ; MIPS64-NEXT: jr $ra
1059 ; MIPS64-NEXT: andi $2, $4, 255
1060 ;
1061 ; MIPS64R2-LABEL: and_i16_255:
1062 ; MIPS64R2: # %bb.0: # %entry
1063 ; MIPS64R2-NEXT: jr $ra
1064 ; MIPS64R2-NEXT: andi $2, $4, 255
1065 ;
1066 ; MIPS64R6-LABEL: and_i16_255:
1067 ; MIPS64R6: # %bb.0: # %entry
1068 ; MIPS64R6-NEXT: jr $ra
1069 ; MIPS64R6-NEXT: andi $2, $4, 255
1070 ;
1071 ; MM32R3-LABEL: and_i16_255:
1072 ; MM32R3: # %bb.0: # %entry
1073 ; MM32R3-NEXT: andi16 $2, $4, 255
1074 ; MM32R3-NEXT: jrc $ra
1075 ;
1076 ; MM32R6-LABEL: and_i16_255:
1077 ; MM32R6: # %bb.0: # %entry
1078 ; MM32R6-NEXT: andi16 $2, $4, 255
1079 ; MM32R6-NEXT: jrc $ra
1080 entry:
378 %r = and i16 255, %b 1081 %r = and i16 255, %b
379 ret i16 %r 1082 ret i16 %r
380 } 1083 }
381 1084
382 define signext i32 @and_i32_255(i32 signext %b) { 1085 define signext i32 @and_i32_255(i32 signext %b) {
383 entry: 1086 ; MIPS-LABEL: and_i32_255:
384 ; ALL-LABEL: and_i32_255: 1087 ; MIPS: # %bb.0: # %entry
385 1088 ; MIPS-NEXT: jr $ra
386 ; GP32: andi $2, $4, 255 1089 ; MIPS-NEXT: andi $2, $4, 255
387 1090 ;
388 ; GP64: andi $2, $4, 255 1091 ; MIPS32R2-LABEL: and_i32_255:
389 1092 ; MIPS32R2: # %bb.0: # %entry
390 ; MM: andi16 $2, $4, 255 1093 ; MIPS32R2-NEXT: jr $ra
391 1094 ; MIPS32R2-NEXT: andi $2, $4, 255
1095 ;
1096 ; MIPS32R6-LABEL: and_i32_255:
1097 ; MIPS32R6: # %bb.0: # %entry
1098 ; MIPS32R6-NEXT: jr $ra
1099 ; MIPS32R6-NEXT: andi $2, $4, 255
1100 ;
1101 ; MIPS64-LABEL: and_i32_255:
1102 ; MIPS64: # %bb.0: # %entry
1103 ; MIPS64-NEXT: jr $ra
1104 ; MIPS64-NEXT: andi $2, $4, 255
1105 ;
1106 ; MIPS64R2-LABEL: and_i32_255:
1107 ; MIPS64R2: # %bb.0: # %entry
1108 ; MIPS64R2-NEXT: jr $ra
1109 ; MIPS64R2-NEXT: andi $2, $4, 255
1110 ;
1111 ; MIPS64R6-LABEL: and_i32_255:
1112 ; MIPS64R6: # %bb.0: # %entry
1113 ; MIPS64R6-NEXT: jr $ra
1114 ; MIPS64R6-NEXT: andi $2, $4, 255
1115 ;
1116 ; MM32R3-LABEL: and_i32_255:
1117 ; MM32R3: # %bb.0: # %entry
1118 ; MM32R3-NEXT: andi16 $2, $4, 255
1119 ; MM32R3-NEXT: jrc $ra
1120 ;
1121 ; MM32R6-LABEL: and_i32_255:
1122 ; MM32R6: # %bb.0: # %entry
1123 ; MM32R6-NEXT: andi16 $2, $4, 255
1124 ; MM32R6-NEXT: jrc $ra
1125 entry:
392 %r = and i32 255, %b 1126 %r = and i32 255, %b
393 ret i32 %r 1127 ret i32 %r
394 } 1128 }
395 1129
396 define signext i64 @and_i64_255(i64 signext %b) { 1130 define signext i64 @and_i64_255(i64 signext %b) {
397 entry: 1131 ; MIPS-LABEL: and_i64_255:
398 ; ALL-LABEL: and_i64_255: 1132 ; MIPS: # %bb.0: # %entry
399 1133 ; MIPS-NEXT: andi $3, $5, 255
400 ; GP32: andi $3, $5, 255 1134 ; MIPS-NEXT: jr $ra
401 ; GP32: addiu $2, $zero, 0 1135 ; MIPS-NEXT: addiu $2, $zero, 0
402 1136 ;
403 ; GP64: andi $2, $4, 255 1137 ; MIPS32R2-LABEL: and_i64_255:
404 1138 ; MIPS32R2: # %bb.0: # %entry
405 ; MM32: andi16 $3, $5, 255 1139 ; MIPS32R2-NEXT: andi $3, $5, 255
406 ; MM32: li16 $2, 0 1140 ; MIPS32R2-NEXT: jr $ra
407 1141 ; MIPS32R2-NEXT: addiu $2, $zero, 0
408 ; MM64: andi $2, $4, 255 1142 ;
409 1143 ; MIPS32R6-LABEL: and_i64_255:
1144 ; MIPS32R6: # %bb.0: # %entry
1145 ; MIPS32R6-NEXT: andi $3, $5, 255
1146 ; MIPS32R6-NEXT: jr $ra
1147 ; MIPS32R6-NEXT: addiu $2, $zero, 0
1148 ;
1149 ; MIPS64-LABEL: and_i64_255:
1150 ; MIPS64: # %bb.0: # %entry
1151 ; MIPS64-NEXT: jr $ra
1152 ; MIPS64-NEXT: andi $2, $4, 255
1153 ;
1154 ; MIPS64R2-LABEL: and_i64_255:
1155 ; MIPS64R2: # %bb.0: # %entry
1156 ; MIPS64R2-NEXT: jr $ra
1157 ; MIPS64R2-NEXT: andi $2, $4, 255
1158 ;
1159 ; MIPS64R6-LABEL: and_i64_255:
1160 ; MIPS64R6: # %bb.0: # %entry
1161 ; MIPS64R6-NEXT: jr $ra
1162 ; MIPS64R6-NEXT: andi $2, $4, 255
1163 ;
1164 ; MM32R3-LABEL: and_i64_255:
1165 ; MM32R3: # %bb.0: # %entry
1166 ; MM32R3-NEXT: andi16 $3, $5, 255
1167 ; MM32R3-NEXT: li16 $2, 0
1168 ; MM32R3-NEXT: jrc $ra
1169 ;
1170 ; MM32R6-LABEL: and_i64_255:
1171 ; MM32R6: # %bb.0: # %entry
1172 ; MM32R6-NEXT: andi16 $3, $5, 255
1173 ; MM32R6-NEXT: li16 $2, 0
1174 ; MM32R6-NEXT: jrc $ra
1175 entry:
410 %r = and i64 255, %b 1176 %r = and i64 255, %b
411 ret i64 %r 1177 ret i64 %r
412 } 1178 }
413 1179
414 define signext i128 @and_i128_255(i128 signext %b) { 1180 define signext i128 @and_i128_255(i128 signext %b) {
415 entry: 1181 ; MIPS-LABEL: and_i128_255:
416 ; ALL-LABEL: and_i128_255: 1182 ; MIPS: # %bb.0: # %entry
417 1183 ; MIPS-NEXT: andi $5, $7, 255
418 ; GP32: andi $5, $7, 255 1184 ; MIPS-NEXT: addiu $2, $zero, 0
419 ; GP32: addiu $2, $zero, 0 1185 ; MIPS-NEXT: addiu $3, $zero, 0
420 ; GP32: addiu $3, $zero, 0 1186 ; MIPS-NEXT: jr $ra
421 ; GP32: addiu $4, $zero, 0 1187 ; MIPS-NEXT: addiu $4, $zero, 0
422 1188 ;
423 ; GP64: andi $3, $5, 255 1189 ; MIPS32R2-LABEL: and_i128_255:
424 ; GP64: daddiu $2, $zero, 0 1190 ; MIPS32R2: # %bb.0: # %entry
425 1191 ; MIPS32R2-NEXT: andi $5, $7, 255
426 ; MM32: andi16 $5, $7, 255 1192 ; MIPS32R2-NEXT: addiu $2, $zero, 0
427 ; MM32: li16 $2, 0 1193 ; MIPS32R2-NEXT: addiu $3, $zero, 0
428 ; MM32: li16 $3, 0 1194 ; MIPS32R2-NEXT: jr $ra
429 ; MM32: li16 $4, 0 1195 ; MIPS32R2-NEXT: addiu $4, $zero, 0
430 1196 ;
431 ; MM64: andi $3, $5, 255 1197 ; MIPS32R6-LABEL: and_i128_255:
432 ; MM64: daddiu $2, $zero, 0 1198 ; MIPS32R6: # %bb.0: # %entry
433 1199 ; MIPS32R6-NEXT: andi $5, $7, 255
1200 ; MIPS32R6-NEXT: addiu $2, $zero, 0
1201 ; MIPS32R6-NEXT: addiu $3, $zero, 0
1202 ; MIPS32R6-NEXT: jr $ra
1203 ; MIPS32R6-NEXT: addiu $4, $zero, 0
1204 ;
1205 ; MIPS64-LABEL: and_i128_255:
1206 ; MIPS64: # %bb.0: # %entry
1207 ; MIPS64-NEXT: andi $3, $5, 255
1208 ; MIPS64-NEXT: jr $ra
1209 ; MIPS64-NEXT: daddiu $2, $zero, 0
1210 ;
1211 ; MIPS64R2-LABEL: and_i128_255:
1212 ; MIPS64R2: # %bb.0: # %entry
1213 ; MIPS64R2-NEXT: andi $3, $5, 255
1214 ; MIPS64R2-NEXT: jr $ra
1215 ; MIPS64R2-NEXT: daddiu $2, $zero, 0
1216 ;
1217 ; MIPS64R6-LABEL: and_i128_255:
1218 ; MIPS64R6: # %bb.0: # %entry
1219 ; MIPS64R6-NEXT: andi $3, $5, 255
1220 ; MIPS64R6-NEXT: jr $ra
1221 ; MIPS64R6-NEXT: daddiu $2, $zero, 0
1222 ;
1223 ; MM32R3-LABEL: and_i128_255:
1224 ; MM32R3: # %bb.0: # %entry
1225 ; MM32R3-NEXT: andi16 $5, $7, 255
1226 ; MM32R3-NEXT: li16 $2, 0
1227 ; MM32R3-NEXT: li16 $3, 0
1228 ; MM32R3-NEXT: li16 $4, 0
1229 ; MM32R3-NEXT: jrc $ra
1230 ;
1231 ; MM32R6-LABEL: and_i128_255:
1232 ; MM32R6: # %bb.0: # %entry
1233 ; MM32R6-NEXT: andi16 $5, $7, 255
1234 ; MM32R6-NEXT: li16 $2, 0
1235 ; MM32R6-NEXT: li16 $3, 0
1236 ; MM32R6-NEXT: li16 $4, 0
1237 ; MM32R6-NEXT: jrc $ra
1238 entry:
434 %r = and i128 255, %b 1239 %r = and i128 255, %b
435 ret i128 %r 1240 ret i128 %r
436 } 1241 }
437 1242
438 define signext i1 @and_i1_32768(i1 signext %b) { 1243 define signext i1 @and_i1_32768(i1 signext %b) {
439 entry: 1244 ; MIPS-LABEL: and_i1_32768:
440 ; ALL-LABEL: and_i1_32768: 1245 ; MIPS: # %bb.0: # %entry
441 1246 ; MIPS-NEXT: jr $ra
442 ; GP32: addiu $2, $zero, 0 1247 ; MIPS-NEXT: addiu $2, $zero, 0
443 1248 ;
444 ; GP64: addiu $2, $zero, 0 1249 ; MIPS32R2-LABEL: and_i1_32768:
445 1250 ; MIPS32R2: # %bb.0: # %entry
446 ; MM: li16 $2, 0 1251 ; MIPS32R2-NEXT: jr $ra
447 1252 ; MIPS32R2-NEXT: addiu $2, $zero, 0
1253 ;
1254 ; MIPS32R6-LABEL: and_i1_32768:
1255 ; MIPS32R6: # %bb.0: # %entry
1256 ; MIPS32R6-NEXT: jr $ra
1257 ; MIPS32R6-NEXT: addiu $2, $zero, 0
1258 ;
1259 ; MIPS64-LABEL: and_i1_32768:
1260 ; MIPS64: # %bb.0: # %entry
1261 ; MIPS64-NEXT: jr $ra
1262 ; MIPS64-NEXT: addiu $2, $zero, 0
1263 ;
1264 ; MIPS64R2-LABEL: and_i1_32768:
1265 ; MIPS64R2: # %bb.0: # %entry
1266 ; MIPS64R2-NEXT: jr $ra
1267 ; MIPS64R2-NEXT: addiu $2, $zero, 0
1268 ;
1269 ; MIPS64R6-LABEL: and_i1_32768:
1270 ; MIPS64R6: # %bb.0: # %entry
1271 ; MIPS64R6-NEXT: jr $ra
1272 ; MIPS64R6-NEXT: addiu $2, $zero, 0
1273 ;
1274 ; MM32R3-LABEL: and_i1_32768:
1275 ; MM32R3: # %bb.0: # %entry
1276 ; MM32R3-NEXT: li16 $2, 0
1277 ; MM32R3-NEXT: jrc $ra
1278 ;
1279 ; MM32R6-LABEL: and_i1_32768:
1280 ; MM32R6: # %bb.0: # %entry
1281 ; MM32R6-NEXT: li16 $2, 0
1282 ; MM32R6-NEXT: jrc $ra
1283 entry:
448 %r = and i1 32768, %b 1284 %r = and i1 32768, %b
449 ret i1 %r 1285 ret i1 %r
450 } 1286 }
451 1287
452 define signext i8 @and_i8_32768(i8 signext %b) { 1288 define signext i8 @and_i8_32768(i8 signext %b) {
453 entry: 1289 ; MIPS-LABEL: and_i8_32768:
454 ; ALL-LABEL: and_i8_32768: 1290 ; MIPS: # %bb.0: # %entry
455 1291 ; MIPS-NEXT: jr $ra
456 ; GP32: addiu $2, $zero, 0 1292 ; MIPS-NEXT: addiu $2, $zero, 0
457 1293 ;
458 ; GP64: addiu $2, $zero, 0 1294 ; MIPS32R2-LABEL: and_i8_32768:
459 1295 ; MIPS32R2: # %bb.0: # %entry
460 ; MM: li16 $2, 0 1296 ; MIPS32R2-NEXT: jr $ra
461 1297 ; MIPS32R2-NEXT: addiu $2, $zero, 0
1298 ;
1299 ; MIPS32R6-LABEL: and_i8_32768:
1300 ; MIPS32R6: # %bb.0: # %entry
1301 ; MIPS32R6-NEXT: jr $ra
1302 ; MIPS32R6-NEXT: addiu $2, $zero, 0
1303 ;
1304 ; MIPS64-LABEL: and_i8_32768:
1305 ; MIPS64: # %bb.0: # %entry
1306 ; MIPS64-NEXT: jr $ra
1307 ; MIPS64-NEXT: addiu $2, $zero, 0
1308 ;
1309 ; MIPS64R2-LABEL: and_i8_32768:
1310 ; MIPS64R2: # %bb.0: # %entry
1311 ; MIPS64R2-NEXT: jr $ra
1312 ; MIPS64R2-NEXT: addiu $2, $zero, 0
1313 ;
1314 ; MIPS64R6-LABEL: and_i8_32768:
1315 ; MIPS64R6: # %bb.0: # %entry
1316 ; MIPS64R6-NEXT: jr $ra
1317 ; MIPS64R6-NEXT: addiu $2, $zero, 0
1318 ;
1319 ; MM32R3-LABEL: and_i8_32768:
1320 ; MM32R3: # %bb.0: # %entry
1321 ; MM32R3-NEXT: li16 $2, 0
1322 ; MM32R3-NEXT: jrc $ra
1323 ;
1324 ; MM32R6-LABEL: and_i8_32768:
1325 ; MM32R6: # %bb.0: # %entry
1326 ; MM32R6-NEXT: li16 $2, 0
1327 ; MM32R6-NEXT: jrc $ra
1328 entry:
462 %r = and i8 32768, %b 1329 %r = and i8 32768, %b
463 ret i8 %r 1330 ret i8 %r
464 } 1331 }
465 1332
466 define signext i16 @and_i16_32768(i16 signext %b) { 1333 define signext i16 @and_i16_32768(i16 signext %b) {
467 entry: 1334 ; MIPS-LABEL: and_i16_32768:
468 ; ALL-LABEL: and_i16_32768: 1335 ; MIPS: # %bb.0: # %entry
469 1336 ; MIPS-NEXT: addiu $1, $zero, -32768
470 ; GP32: addiu $[[T0:[0-9]+]], $zero, -32768 1337 ; MIPS-NEXT: jr $ra
471 ; GP32: and $2, $4, $[[T0]] 1338 ; MIPS-NEXT: and $2, $4, $1
472 1339 ;
473 ; GP64: addiu $[[T0:[0-9]+]], $zero, -32768 1340 ; MIPS32R2-LABEL: and_i16_32768:
474 ; GP64: and $2, $4, $[[T0]] 1341 ; MIPS32R2: # %bb.0: # %entry
475 1342 ; MIPS32R2-NEXT: addiu $1, $zero, -32768
476 ; MM: addiu $2, $zero, -32768 1343 ; MIPS32R2-NEXT: jr $ra
477 ; MM: and16 $2, $4 1344 ; MIPS32R2-NEXT: and $2, $4, $1
1345 ;
1346 ; MIPS32R6-LABEL: and_i16_32768:
1347 ; MIPS32R6: # %bb.0: # %entry
1348 ; MIPS32R6-NEXT: addiu $1, $zero, -32768
1349 ; MIPS32R6-NEXT: jr $ra
1350 ; MIPS32R6-NEXT: and $2, $4, $1
1351 ;
1352 ; MIPS64-LABEL: and_i16_32768:
1353 ; MIPS64: # %bb.0: # %entry
1354 ; MIPS64-NEXT: addiu $1, $zero, -32768
1355 ; MIPS64-NEXT: jr $ra
1356 ; MIPS64-NEXT: and $2, $4, $1
1357 ;
1358 ; MIPS64R2-LABEL: and_i16_32768:
1359 ; MIPS64R2: # %bb.0: # %entry
1360 ; MIPS64R2-NEXT: addiu $1, $zero, -32768
1361 ; MIPS64R2-NEXT: jr $ra
1362 ; MIPS64R2-NEXT: and $2, $4, $1
1363 ;
1364 ; MIPS64R6-LABEL: and_i16_32768:
1365 ; MIPS64R6: # %bb.0: # %entry
1366 ; MIPS64R6-NEXT: addiu $1, $zero, -32768
1367 ; MIPS64R6-NEXT: jr $ra
1368 ; MIPS64R6-NEXT: and $2, $4, $1
1369 ;
1370 ; MM32R3-LABEL: and_i16_32768:
1371 ; MM32R3: # %bb.0: # %entry
1372 ; MM32R3-NEXT: addiu $2, $zero, -32768
1373 ; MM32R3-NEXT: and16 $2, $4
1374 ; MM32R3-NEXT: jrc $ra
1375 ;
1376 ; MM32R6-LABEL: and_i16_32768:
1377 ; MM32R6: # %bb.0: # %entry
1378 ; MM32R6-NEXT: addiu $1, $zero, -32768
1379 ; MM32R6-NEXT: and $2, $4, $1
1380 ; MM32R6-NEXT: jrc $ra
1381 entry:
478 1382
479 %r = and i16 32768, %b 1383 %r = and i16 32768, %b
480 ret i16 %r 1384 ret i16 %r
481 } 1385 }
482 1386
483 define signext i32 @and_i32_32768(i32 signext %b) { 1387 define signext i32 @and_i32_32768(i32 signext %b) {
484 entry: 1388 ; MIPS-LABEL: and_i32_32768:
485 ; ALL-LABEL: and_i32_32768: 1389 ; MIPS: # %bb.0: # %entry
486 1390 ; MIPS-NEXT: jr $ra
487 ; GP32: andi $2, $4, 32768 1391 ; MIPS-NEXT: andi $2, $4, 32768
488 1392 ;
489 ; GP64: andi $2, $4, 32768 1393 ; MIPS32R2-LABEL: and_i32_32768:
490 1394 ; MIPS32R2: # %bb.0: # %entry
491 ; MM: andi16 $2, $4, 32768 1395 ; MIPS32R2-NEXT: jr $ra
492 1396 ; MIPS32R2-NEXT: andi $2, $4, 32768
1397 ;
1398 ; MIPS32R6-LABEL: and_i32_32768:
1399 ; MIPS32R6: # %bb.0: # %entry
1400 ; MIPS32R6-NEXT: jr $ra
1401 ; MIPS32R6-NEXT: andi $2, $4, 32768
1402 ;
1403 ; MIPS64-LABEL: and_i32_32768:
1404 ; MIPS64: # %bb.0: # %entry
1405 ; MIPS64-NEXT: jr $ra
1406 ; MIPS64-NEXT: andi $2, $4, 32768
1407 ;
1408 ; MIPS64R2-LABEL: and_i32_32768:
1409 ; MIPS64R2: # %bb.0: # %entry
1410 ; MIPS64R2-NEXT: jr $ra
1411 ; MIPS64R2-NEXT: andi $2, $4, 32768
1412 ;
1413 ; MIPS64R6-LABEL: and_i32_32768:
1414 ; MIPS64R6: # %bb.0: # %entry
1415 ; MIPS64R6-NEXT: jr $ra
1416 ; MIPS64R6-NEXT: andi $2, $4, 32768
1417 ;
1418 ; MM32R3-LABEL: and_i32_32768:
1419 ; MM32R3: # %bb.0: # %entry
1420 ; MM32R3-NEXT: andi16 $2, $4, 32768
1421 ; MM32R3-NEXT: jrc $ra
1422 ;
1423 ; MM32R6-LABEL: and_i32_32768:
1424 ; MM32R6: # %bb.0: # %entry
1425 ; MM32R6-NEXT: andi16 $2, $4, 32768
1426 ; MM32R6-NEXT: jrc $ra
1427 entry:
493 %r = and i32 32768, %b 1428 %r = and i32 32768, %b
494 ret i32 %r 1429 ret i32 %r
495 } 1430 }
496 1431
497 define signext i64 @and_i64_32768(i64 signext %b) { 1432 define signext i64 @and_i64_32768(i64 signext %b) {
498 entry: 1433 ; MIPS-LABEL: and_i64_32768:
499 ; ALL-LABEL: and_i64_32768: 1434 ; MIPS: # %bb.0: # %entry
500 1435 ; MIPS-NEXT: andi $3, $5, 32768
501 ; GP32: andi $3, $5, 32768 1436 ; MIPS-NEXT: jr $ra
502 ; GP32: addiu $2, $zero, 0 1437 ; MIPS-NEXT: addiu $2, $zero, 0
503 1438 ;
504 ; GP64: andi $2, $4, 32768 1439 ; MIPS32R2-LABEL: and_i64_32768:
505 1440 ; MIPS32R2: # %bb.0: # %entry
506 ; MM32: andi16 $3, $5, 32768 1441 ; MIPS32R2-NEXT: andi $3, $5, 32768
507 ; MM32: li16 $2, 0 1442 ; MIPS32R2-NEXT: jr $ra
508 1443 ; MIPS32R2-NEXT: addiu $2, $zero, 0
509 ; MM64: andi $2, $4, 32768 1444 ;
510 1445 ; MIPS32R6-LABEL: and_i64_32768:
1446 ; MIPS32R6: # %bb.0: # %entry
1447 ; MIPS32R6-NEXT: andi $3, $5, 32768
1448 ; MIPS32R6-NEXT: jr $ra
1449 ; MIPS32R6-NEXT: addiu $2, $zero, 0
1450 ;
1451 ; MIPS64-LABEL: and_i64_32768:
1452 ; MIPS64: # %bb.0: # %entry
1453 ; MIPS64-NEXT: jr $ra
1454 ; MIPS64-NEXT: andi $2, $4, 32768
1455 ;
1456 ; MIPS64R2-LABEL: and_i64_32768:
1457 ; MIPS64R2: # %bb.0: # %entry
1458 ; MIPS64R2-NEXT: jr $ra
1459 ; MIPS64R2-NEXT: andi $2, $4, 32768
1460 ;
1461 ; MIPS64R6-LABEL: and_i64_32768:
1462 ; MIPS64R6: # %bb.0: # %entry
1463 ; MIPS64R6-NEXT: jr $ra
1464 ; MIPS64R6-NEXT: andi $2, $4, 32768
1465 ;
1466 ; MM32R3-LABEL: and_i64_32768:
1467 ; MM32R3: # %bb.0: # %entry
1468 ; MM32R3-NEXT: andi16 $3, $5, 32768
1469 ; MM32R3-NEXT: li16 $2, 0
1470 ; MM32R3-NEXT: jrc $ra
1471 ;
1472 ; MM32R6-LABEL: and_i64_32768:
1473 ; MM32R6: # %bb.0: # %entry
1474 ; MM32R6-NEXT: andi16 $3, $5, 32768
1475 ; MM32R6-NEXT: li16 $2, 0
1476 ; MM32R6-NEXT: jrc $ra
1477 entry:
511 %r = and i64 32768, %b 1478 %r = and i64 32768, %b
512 ret i64 %r 1479 ret i64 %r
513 } 1480 }
514 1481
515 define signext i128 @and_i128_32768(i128 signext %b) { 1482 define signext i128 @and_i128_32768(i128 signext %b) {
516 entry: 1483 ; MIPS-LABEL: and_i128_32768:
517 ; ALL-LABEL: and_i128_32768: 1484 ; MIPS: # %bb.0: # %entry
518 1485 ; MIPS-NEXT: andi $5, $7, 32768
519 ; GP32: andi $5, $7, 32768 1486 ; MIPS-NEXT: addiu $2, $zero, 0
520 ; GP32: addiu $2, $zero, 0 1487 ; MIPS-NEXT: addiu $3, $zero, 0
521 ; GP32: addiu $3, $zero, 0 1488 ; MIPS-NEXT: jr $ra
522 ; GP32: addiu $4, $zero, 0 1489 ; MIPS-NEXT: addiu $4, $zero, 0
523 1490 ;
524 ; GP64: andi $3, $5, 32768 1491 ; MIPS32R2-LABEL: and_i128_32768:
525 ; GP64: daddiu $2, $zero, 0 1492 ; MIPS32R2: # %bb.0: # %entry
526 1493 ; MIPS32R2-NEXT: andi $5, $7, 32768
527 ; MM32: andi16 $5, $7, 32768 1494 ; MIPS32R2-NEXT: addiu $2, $zero, 0
528 ; MM32: li16 $2, 0 1495 ; MIPS32R2-NEXT: addiu $3, $zero, 0
529 ; MM32: li16 $3, 0 1496 ; MIPS32R2-NEXT: jr $ra
530 ; MM32: li16 $4, 0 1497 ; MIPS32R2-NEXT: addiu $4, $zero, 0
531 1498 ;
532 ; MM64: andi $3, $5, 32768 1499 ; MIPS32R6-LABEL: and_i128_32768:
533 ; MM64: daddiu $2, $zero, 0 1500 ; MIPS32R6: # %bb.0: # %entry
534 1501 ; MIPS32R6-NEXT: andi $5, $7, 32768
1502 ; MIPS32R6-NEXT: addiu $2, $zero, 0
1503 ; MIPS32R6-NEXT: addiu $3, $zero, 0
1504 ; MIPS32R6-NEXT: jr $ra
1505 ; MIPS32R6-NEXT: addiu $4, $zero, 0
1506 ;
1507 ; MIPS64-LABEL: and_i128_32768:
1508 ; MIPS64: # %bb.0: # %entry
1509 ; MIPS64-NEXT: andi $3, $5, 32768
1510 ; MIPS64-NEXT: jr $ra
1511 ; MIPS64-NEXT: daddiu $2, $zero, 0
1512 ;
1513 ; MIPS64R2-LABEL: and_i128_32768:
1514 ; MIPS64R2: # %bb.0: # %entry
1515 ; MIPS64R2-NEXT: andi $3, $5, 32768
1516 ; MIPS64R2-NEXT: jr $ra
1517 ; MIPS64R2-NEXT: daddiu $2, $zero, 0
1518 ;
1519 ; MIPS64R6-LABEL: and_i128_32768:
1520 ; MIPS64R6: # %bb.0: # %entry
1521 ; MIPS64R6-NEXT: andi $3, $5, 32768
1522 ; MIPS64R6-NEXT: jr $ra
1523 ; MIPS64R6-NEXT: daddiu $2, $zero, 0
1524 ;
1525 ; MM32R3-LABEL: and_i128_32768:
1526 ; MM32R3: # %bb.0: # %entry
1527 ; MM32R3-NEXT: andi16 $5, $7, 32768
1528 ; MM32R3-NEXT: li16 $2, 0
1529 ; MM32R3-NEXT: li16 $3, 0
1530 ; MM32R3-NEXT: li16 $4, 0
1531 ; MM32R3-NEXT: jrc $ra
1532 ;
1533 ; MM32R6-LABEL: and_i128_32768:
1534 ; MM32R6: # %bb.0: # %entry
1535 ; MM32R6-NEXT: andi16 $5, $7, 32768
1536 ; MM32R6-NEXT: li16 $2, 0
1537 ; MM32R6-NEXT: li16 $3, 0
1538 ; MM32R6-NEXT: li16 $4, 0
1539 ; MM32R6-NEXT: jrc $ra
1540 entry:
535 %r = and i128 32768, %b 1541 %r = and i128 32768, %b
536 ret i128 %r 1542 ret i128 %r
537 } 1543 }
538 1544
539 define signext i1 @and_i1_65(i1 signext %b) { 1545 define signext i1 @and_i1_65(i1 signext %b) {
540 entry: 1546 ; MIPS-LABEL: and_i1_65:
541 ; ALL-LABEL: and_i1_65: 1547 ; MIPS: # %bb.0: # %entry
542 1548 ; MIPS-NEXT: jr $ra
543 ; ALL: move $2, $4 1549 ; MIPS-NEXT: move $2, $4
544 1550 ;
1551 ; MIPS32R2-LABEL: and_i1_65:
1552 ; MIPS32R2: # %bb.0: # %entry
1553 ; MIPS32R2-NEXT: jr $ra
1554 ; MIPS32R2-NEXT: move $2, $4
1555 ;
1556 ; MIPS32R6-LABEL: and_i1_65:
1557 ; MIPS32R6: # %bb.0: # %entry
1558 ; MIPS32R6-NEXT: jr $ra
1559 ; MIPS32R6-NEXT: move $2, $4
1560 ;
1561 ; MIPS64-LABEL: and_i1_65:
1562 ; MIPS64: # %bb.0: # %entry
1563 ; MIPS64-NEXT: jr $ra
1564 ; MIPS64-NEXT: move $2, $4
1565 ;
1566 ; MIPS64R2-LABEL: and_i1_65:
1567 ; MIPS64R2: # %bb.0: # %entry
1568 ; MIPS64R2-NEXT: jr $ra
1569 ; MIPS64R2-NEXT: move $2, $4
1570 ;
1571 ; MIPS64R6-LABEL: and_i1_65:
1572 ; MIPS64R6: # %bb.0: # %entry
1573 ; MIPS64R6-NEXT: jr $ra
1574 ; MIPS64R6-NEXT: move $2, $4
1575 ;
1576 ; MM32R3-LABEL: and_i1_65:
1577 ; MM32R3: # %bb.0: # %entry
1578 ; MM32R3-NEXT: move $2, $4
1579 ; MM32R3-NEXT: jrc $ra
1580 ;
1581 ; MM32R6-LABEL: and_i1_65:
1582 ; MM32R6: # %bb.0: # %entry
1583 ; MM32R6-NEXT: move $2, $4
1584 ; MM32R6-NEXT: jrc $ra
1585 entry:
545 %r = and i1 65, %b 1586 %r = and i1 65, %b
546 ret i1 %r 1587 ret i1 %r
547 } 1588 }
548 1589
549 define signext i8 @and_i8_65(i8 signext %b) { 1590 define signext i8 @and_i8_65(i8 signext %b) {
550 entry: 1591 ; MIPS-LABEL: and_i8_65:
551 ; ALL-LABEL: and_i8_65: 1592 ; MIPS: # %bb.0: # %entry
552 1593 ; MIPS-NEXT: jr $ra
553 ; ALL: andi $2, $4, 65 1594 ; MIPS-NEXT: andi $2, $4, 65
554 1595 ;
1596 ; MIPS32R2-LABEL: and_i8_65:
1597 ; MIPS32R2: # %bb.0: # %entry
1598 ; MIPS32R2-NEXT: jr $ra
1599 ; MIPS32R2-NEXT: andi $2, $4, 65
1600 ;
1601 ; MIPS32R6-LABEL: and_i8_65:
1602 ; MIPS32R6: # %bb.0: # %entry
1603 ; MIPS32R6-NEXT: jr $ra
1604 ; MIPS32R6-NEXT: andi $2, $4, 65
1605 ;
1606 ; MIPS64-LABEL: and_i8_65:
1607 ; MIPS64: # %bb.0: # %entry
1608 ; MIPS64-NEXT: jr $ra
1609 ; MIPS64-NEXT: andi $2, $4, 65
1610 ;
1611 ; MIPS64R2-LABEL: and_i8_65:
1612 ; MIPS64R2: # %bb.0: # %entry
1613 ; MIPS64R2-NEXT: jr $ra
1614 ; MIPS64R2-NEXT: andi $2, $4, 65
1615 ;
1616 ; MIPS64R6-LABEL: and_i8_65:
1617 ; MIPS64R6: # %bb.0: # %entry
1618 ; MIPS64R6-NEXT: jr $ra
1619 ; MIPS64R6-NEXT: andi $2, $4, 65
1620 ;
1621 ; MM32R3-LABEL: and_i8_65:
1622 ; MM32R3: # %bb.0: # %entry
1623 ; MM32R3-NEXT: jr $ra
1624 ; MM32R3-NEXT: andi $2, $4, 65
1625 ;
1626 ; MM32R6-LABEL: and_i8_65:
1627 ; MM32R6: # %bb.0: # %entry
1628 ; MM32R6-NEXT: andi $2, $4, 65
1629 ; MM32R6-NEXT: jrc $ra
1630 entry:
555 %r = and i8 65, %b 1631 %r = and i8 65, %b
556 ret i8 %r 1632 ret i8 %r
557 } 1633 }
558 1634
559 define signext i16 @and_i16_65(i16 signext %b) { 1635 define signext i16 @and_i16_65(i16 signext %b) {
560 entry: 1636 ; MIPS-LABEL: and_i16_65:
561 ; ALL-LABEL: and_i16_65: 1637 ; MIPS: # %bb.0: # %entry
562 1638 ; MIPS-NEXT: jr $ra
563 ; ALL: andi $2, $4, 65 1639 ; MIPS-NEXT: andi $2, $4, 65
564 1640 ;
1641 ; MIPS32R2-LABEL: and_i16_65:
1642 ; MIPS32R2: # %bb.0: # %entry
1643 ; MIPS32R2-NEXT: jr $ra
1644 ; MIPS32R2-NEXT: andi $2, $4, 65
1645 ;
1646 ; MIPS32R6-LABEL: and_i16_65:
1647 ; MIPS32R6: # %bb.0: # %entry
1648 ; MIPS32R6-NEXT: jr $ra
1649 ; MIPS32R6-NEXT: andi $2, $4, 65
1650 ;
1651 ; MIPS64-LABEL: and_i16_65:
1652 ; MIPS64: # %bb.0: # %entry
1653 ; MIPS64-NEXT: jr $ra
1654 ; MIPS64-NEXT: andi $2, $4, 65
1655 ;
1656 ; MIPS64R2-LABEL: and_i16_65:
1657 ; MIPS64R2: # %bb.0: # %entry
1658 ; MIPS64R2-NEXT: jr $ra
1659 ; MIPS64R2-NEXT: andi $2, $4, 65
1660 ;
1661 ; MIPS64R6-LABEL: and_i16_65:
1662 ; MIPS64R6: # %bb.0: # %entry
1663 ; MIPS64R6-NEXT: jr $ra
1664 ; MIPS64R6-NEXT: andi $2, $4, 65
1665 ;
1666 ; MM32R3-LABEL: and_i16_65:
1667 ; MM32R3: # %bb.0: # %entry
1668 ; MM32R3-NEXT: jr $ra
1669 ; MM32R3-NEXT: andi $2, $4, 65
1670 ;
1671 ; MM32R6-LABEL: and_i16_65:
1672 ; MM32R6: # %bb.0: # %entry
1673 ; MM32R6-NEXT: andi $2, $4, 65
1674 ; MM32R6-NEXT: jrc $ra
1675 entry:
565 %r = and i16 65, %b 1676 %r = and i16 65, %b
566 ret i16 %r 1677 ret i16 %r
567 } 1678 }
568 1679
569 define signext i32 @and_i32_65(i32 signext %b) { 1680 define signext i32 @and_i32_65(i32 signext %b) {
570 entry: 1681 ; MIPS-LABEL: and_i32_65:
571 ; ALL-LABEL: and_i32_65: 1682 ; MIPS: # %bb.0: # %entry
572 1683 ; MIPS-NEXT: jr $ra
573 ; ALL: andi $2, $4, 65 1684 ; MIPS-NEXT: andi $2, $4, 65
574 1685 ;
1686 ; MIPS32R2-LABEL: and_i32_65:
1687 ; MIPS32R2: # %bb.0: # %entry
1688 ; MIPS32R2-NEXT: jr $ra
1689 ; MIPS32R2-NEXT: andi $2, $4, 65
1690 ;
1691 ; MIPS32R6-LABEL: and_i32_65:
1692 ; MIPS32R6: # %bb.0: # %entry
1693 ; MIPS32R6-NEXT: jr $ra
1694 ; MIPS32R6-NEXT: andi $2, $4, 65
1695 ;
1696 ; MIPS64-LABEL: and_i32_65:
1697 ; MIPS64: # %bb.0: # %entry
1698 ; MIPS64-NEXT: jr $ra
1699 ; MIPS64-NEXT: andi $2, $4, 65
1700 ;
1701 ; MIPS64R2-LABEL: and_i32_65:
1702 ; MIPS64R2: # %bb.0: # %entry
1703 ; MIPS64R2-NEXT: jr $ra
1704 ; MIPS64R2-NEXT: andi $2, $4, 65
1705 ;
1706 ; MIPS64R6-LABEL: and_i32_65:
1707 ; MIPS64R6: # %bb.0: # %entry
1708 ; MIPS64R6-NEXT: jr $ra
1709 ; MIPS64R6-NEXT: andi $2, $4, 65
1710 ;
1711 ; MM32R3-LABEL: and_i32_65:
1712 ; MM32R3: # %bb.0: # %entry
1713 ; MM32R3-NEXT: jr $ra
1714 ; MM32R3-NEXT: andi $2, $4, 65
1715 ;
1716 ; MM32R6-LABEL: and_i32_65:
1717 ; MM32R6: # %bb.0: # %entry
1718 ; MM32R6-NEXT: andi $2, $4, 65
1719 ; MM32R6-NEXT: jrc $ra
1720 entry:
575 %r = and i32 65, %b 1721 %r = and i32 65, %b
576 ret i32 %r 1722 ret i32 %r
577 } 1723 }
578 1724
579 define signext i64 @and_i64_65(i64 signext %b) { 1725 define signext i64 @and_i64_65(i64 signext %b) {
580 entry: 1726 ; MIPS-LABEL: and_i64_65:
581 ; ALL-LABEL: and_i64_65: 1727 ; MIPS: # %bb.0: # %entry
582 1728 ; MIPS-NEXT: andi $3, $5, 65
583 ; GP32: andi $3, $5, 65 1729 ; MIPS-NEXT: jr $ra
584 ; GP32: addiu $2, $zero, 0 1730 ; MIPS-NEXT: addiu $2, $zero, 0
585 1731 ;
586 ; GP64: andi $2, $4, 65 1732 ; MIPS32R2-LABEL: and_i64_65:
587 1733 ; MIPS32R2: # %bb.0: # %entry
588 ; MM32-DAG: andi $3, $5, 65 1734 ; MIPS32R2-NEXT: andi $3, $5, 65
589 ; MM32-DAG: li16 $2, 0 1735 ; MIPS32R2-NEXT: jr $ra
590 1736 ; MIPS32R2-NEXT: addiu $2, $zero, 0
591 ; MM64: andi $2, $4, 65 1737 ;
592 1738 ; MIPS32R6-LABEL: and_i64_65:
1739 ; MIPS32R6: # %bb.0: # %entry
1740 ; MIPS32R6-NEXT: andi $3, $5, 65
1741 ; MIPS32R6-NEXT: jr $ra
1742 ; MIPS32R6-NEXT: addiu $2, $zero, 0
1743 ;
1744 ; MIPS64-LABEL: and_i64_65:
1745 ; MIPS64: # %bb.0: # %entry
1746 ; MIPS64-NEXT: jr $ra
1747 ; MIPS64-NEXT: andi $2, $4, 65
1748 ;
1749 ; MIPS64R2-LABEL: and_i64_65:
1750 ; MIPS64R2: # %bb.0: # %entry
1751 ; MIPS64R2-NEXT: jr $ra
1752 ; MIPS64R2-NEXT: andi $2, $4, 65
1753 ;
1754 ; MIPS64R6-LABEL: and_i64_65:
1755 ; MIPS64R6: # %bb.0: # %entry
1756 ; MIPS64R6-NEXT: jr $ra
1757 ; MIPS64R6-NEXT: andi $2, $4, 65
1758 ;
1759 ; MM32R3-LABEL: and_i64_65:
1760 ; MM32R3: # %bb.0: # %entry
1761 ; MM32R3-NEXT: li16 $2, 0
1762 ; MM32R3-NEXT: jr $ra
1763 ; MM32R3-NEXT: andi $3, $5, 65
1764 ;
1765 ; MM32R6-LABEL: and_i64_65:
1766 ; MM32R6: # %bb.0: # %entry
1767 ; MM32R6-NEXT: andi $3, $5, 65
1768 ; MM32R6-NEXT: li16 $2, 0
1769 ; MM32R6-NEXT: jrc $ra
1770 entry:
593 %r = and i64 65, %b 1771 %r = and i64 65, %b
594 ret i64 %r 1772 ret i64 %r
595 } 1773 }
596 1774
597 define signext i128 @and_i128_65(i128 signext %b) { 1775 define signext i128 @and_i128_65(i128 signext %b) {
598 entry: 1776 ; MIPS-LABEL: and_i128_65:
599 ; ALL-LABEL: and_i128_65: 1777 ; MIPS: # %bb.0: # %entry
600 1778 ; MIPS-NEXT: andi $5, $7, 65
601 ; GP32: andi $5, $7, 65 1779 ; MIPS-NEXT: addiu $2, $zero, 0
602 ; GP32: addiu $2, $zero, 0 1780 ; MIPS-NEXT: addiu $3, $zero, 0
603 ; GP32: addiu $3, $zero, 0 1781 ; MIPS-NEXT: jr $ra
604 ; GP32: addiu $4, $zero, 0 1782 ; MIPS-NEXT: addiu $4, $zero, 0
605 1783 ;
606 ; GP64: andi $3, $5, 65 1784 ; MIPS32R2-LABEL: and_i128_65:
607 ; GP64: daddiu $2, $zero, 0 1785 ; MIPS32R2: # %bb.0: # %entry
608 1786 ; MIPS32R2-NEXT: andi $5, $7, 65
609 ; MM32-DAG: andi $5, $7, 65 1787 ; MIPS32R2-NEXT: addiu $2, $zero, 0
610 ; MM32-DAG: li16 $2, 0 1788 ; MIPS32R2-NEXT: addiu $3, $zero, 0
611 ; MM32-DAG: li16 $3, 0 1789 ; MIPS32R2-NEXT: jr $ra
612 ; MM32-DAG: li16 $4, 0 1790 ; MIPS32R2-NEXT: addiu $4, $zero, 0
613 1791 ;
614 ; MM64: andi $3, $5, 65 1792 ; MIPS32R6-LABEL: and_i128_65:
615 ; MM64: daddiu $2, $zero, 0 1793 ; MIPS32R6: # %bb.0: # %entry
616 1794 ; MIPS32R6-NEXT: andi $5, $7, 65
1795 ; MIPS32R6-NEXT: addiu $2, $zero, 0
1796 ; MIPS32R6-NEXT: addiu $3, $zero, 0
1797 ; MIPS32R6-NEXT: jr $ra
1798 ; MIPS32R6-NEXT: addiu $4, $zero, 0
1799 ;
1800 ; MIPS64-LABEL: and_i128_65:
1801 ; MIPS64: # %bb.0: # %entry
1802 ; MIPS64-NEXT: andi $3, $5, 65
1803 ; MIPS64-NEXT: jr $ra
1804 ; MIPS64-NEXT: daddiu $2, $zero, 0
1805 ;
1806 ; MIPS64R2-LABEL: and_i128_65:
1807 ; MIPS64R2: # %bb.0: # %entry
1808 ; MIPS64R2-NEXT: andi $3, $5, 65
1809 ; MIPS64R2-NEXT: jr $ra
1810 ; MIPS64R2-NEXT: daddiu $2, $zero, 0
1811 ;
1812 ; MIPS64R6-LABEL: and_i128_65:
1813 ; MIPS64R6: # %bb.0: # %entry
1814 ; MIPS64R6-NEXT: andi $3, $5, 65
1815 ; MIPS64R6-NEXT: jr $ra
1816 ; MIPS64R6-NEXT: daddiu $2, $zero, 0
1817 ;
1818 ; MM32R3-LABEL: and_i128_65:
1819 ; MM32R3: # %bb.0: # %entry
1820 ; MM32R3-NEXT: li16 $2, 0
1821 ; MM32R3-NEXT: li16 $3, 0
1822 ; MM32R3-NEXT: li16 $4, 0
1823 ; MM32R3-NEXT: jr $ra
1824 ; MM32R3-NEXT: andi $5, $7, 65
1825 ;
1826 ; MM32R6-LABEL: and_i128_65:
1827 ; MM32R6: # %bb.0: # %entry
1828 ; MM32R6-NEXT: andi $5, $7, 65
1829 ; MM32R6-NEXT: li16 $2, 0
1830 ; MM32R6-NEXT: li16 $3, 0
1831 ; MM32R6-NEXT: li16 $4, 0
1832 ; MM32R6-NEXT: jrc $ra
1833 entry:
617 %r = and i128 65, %b 1834 %r = and i128 65, %b
618 ret i128 %r 1835 ret i128 %r
619 } 1836 }
620 1837
621 define signext i1 @and_i1_256(i1 signext %b) { 1838 define signext i1 @and_i1_256(i1 signext %b) {
622 entry: 1839 ; MIPS-LABEL: and_i1_256:
623 ; ALL-LABEL: and_i1_256: 1840 ; MIPS: # %bb.0: # %entry
624 1841 ; MIPS-NEXT: jr $ra
625 ; GP32: addiu $2, $zero, 0 1842 ; MIPS-NEXT: addiu $2, $zero, 0
626 1843 ;
627 ; GP64: addiu $2, $zero, 0 1844 ; MIPS32R2-LABEL: and_i1_256:
628 1845 ; MIPS32R2: # %bb.0: # %entry
629 ; MM: li16 $2, 0 1846 ; MIPS32R2-NEXT: jr $ra
630 1847 ; MIPS32R2-NEXT: addiu $2, $zero, 0
1848 ;
1849 ; MIPS32R6-LABEL: and_i1_256:
1850 ; MIPS32R6: # %bb.0: # %entry
1851 ; MIPS32R6-NEXT: jr $ra
1852 ; MIPS32R6-NEXT: addiu $2, $zero, 0
1853 ;
1854 ; MIPS64-LABEL: and_i1_256:
1855 ; MIPS64: # %bb.0: # %entry
1856 ; MIPS64-NEXT: jr $ra
1857 ; MIPS64-NEXT: addiu $2, $zero, 0
1858 ;
1859 ; MIPS64R2-LABEL: and_i1_256:
1860 ; MIPS64R2: # %bb.0: # %entry
1861 ; MIPS64R2-NEXT: jr $ra
1862 ; MIPS64R2-NEXT: addiu $2, $zero, 0
1863 ;
1864 ; MIPS64R6-LABEL: and_i1_256:
1865 ; MIPS64R6: # %bb.0: # %entry
1866 ; MIPS64R6-NEXT: jr $ra
1867 ; MIPS64R6-NEXT: addiu $2, $zero, 0
1868 ;
1869 ; MM32R3-LABEL: and_i1_256:
1870 ; MM32R3: # %bb.0: # %entry
1871 ; MM32R3-NEXT: li16 $2, 0
1872 ; MM32R3-NEXT: jrc $ra
1873 ;
1874 ; MM32R6-LABEL: and_i1_256:
1875 ; MM32R6: # %bb.0: # %entry
1876 ; MM32R6-NEXT: li16 $2, 0
1877 ; MM32R6-NEXT: jrc $ra
1878 entry:
631 %r = and i1 256, %b 1879 %r = and i1 256, %b
632 ret i1 %r 1880 ret i1 %r
633 } 1881 }
634 1882
635 define signext i8 @and_i8_256(i8 signext %b) { 1883 define signext i8 @and_i8_256(i8 signext %b) {
636 entry: 1884 ; MIPS-LABEL: and_i8_256:
637 ; ALL-LABEL: and_i8_256: 1885 ; MIPS: # %bb.0: # %entry
638 1886 ; MIPS-NEXT: jr $ra
639 ; GP32: addiu $2, $zero, 0 1887 ; MIPS-NEXT: addiu $2, $zero, 0
640 1888 ;
641 ; GP64: addiu $2, $zero, 0 1889 ; MIPS32R2-LABEL: and_i8_256:
642 1890 ; MIPS32R2: # %bb.0: # %entry
643 ; MM: li16 $2, 0 1891 ; MIPS32R2-NEXT: jr $ra
644 1892 ; MIPS32R2-NEXT: addiu $2, $zero, 0
1893 ;
1894 ; MIPS32R6-LABEL: and_i8_256:
1895 ; MIPS32R6: # %bb.0: # %entry
1896 ; MIPS32R6-NEXT: jr $ra
1897 ; MIPS32R6-NEXT: addiu $2, $zero, 0
1898 ;
1899 ; MIPS64-LABEL: and_i8_256:
1900 ; MIPS64: # %bb.0: # %entry
1901 ; MIPS64-NEXT: jr $ra
1902 ; MIPS64-NEXT: addiu $2, $zero, 0
1903 ;
1904 ; MIPS64R2-LABEL: and_i8_256:
1905 ; MIPS64R2: # %bb.0: # %entry
1906 ; MIPS64R2-NEXT: jr $ra
1907 ; MIPS64R2-NEXT: addiu $2, $zero, 0
1908 ;
1909 ; MIPS64R6-LABEL: and_i8_256:
1910 ; MIPS64R6: # %bb.0: # %entry
1911 ; MIPS64R6-NEXT: jr $ra
1912 ; MIPS64R6-NEXT: addiu $2, $zero, 0
1913 ;
1914 ; MM32R3-LABEL: and_i8_256:
1915 ; MM32R3: # %bb.0: # %entry
1916 ; MM32R3-NEXT: li16 $2, 0
1917 ; MM32R3-NEXT: jrc $ra
1918 ;
1919 ; MM32R6-LABEL: and_i8_256:
1920 ; MM32R6: # %bb.0: # %entry
1921 ; MM32R6-NEXT: li16 $2, 0
1922 ; MM32R6-NEXT: jrc $ra
1923 entry:
645 %r = and i8 256, %b 1924 %r = and i8 256, %b
646 ret i8 %r 1925 ret i8 %r
647 } 1926 }
648 1927
649 define signext i16 @and_i16_256(i16 signext %b) { 1928 define signext i16 @and_i16_256(i16 signext %b) {
650 entry: 1929 ; MIPS-LABEL: and_i16_256:
651 ; ALL-LABEL: and_i16_256: 1930 ; MIPS: # %bb.0: # %entry
652 1931 ; MIPS-NEXT: jr $ra
653 ; ALL: andi $2, $4, 256 1932 ; MIPS-NEXT: andi $2, $4, 256
654 1933 ;
1934 ; MIPS32R2-LABEL: and_i16_256:
1935 ; MIPS32R2: # %bb.0: # %entry
1936 ; MIPS32R2-NEXT: jr $ra
1937 ; MIPS32R2-NEXT: andi $2, $4, 256
1938 ;
1939 ; MIPS32R6-LABEL: and_i16_256:
1940 ; MIPS32R6: # %bb.0: # %entry
1941 ; MIPS32R6-NEXT: jr $ra
1942 ; MIPS32R6-NEXT: andi $2, $4, 256
1943 ;
1944 ; MIPS64-LABEL: and_i16_256:
1945 ; MIPS64: # %bb.0: # %entry
1946 ; MIPS64-NEXT: jr $ra
1947 ; MIPS64-NEXT: andi $2, $4, 256
1948 ;
1949 ; MIPS64R2-LABEL: and_i16_256:
1950 ; MIPS64R2: # %bb.0: # %entry
1951 ; MIPS64R2-NEXT: jr $ra
1952 ; MIPS64R2-NEXT: andi $2, $4, 256
1953 ;
1954 ; MIPS64R6-LABEL: and_i16_256:
1955 ; MIPS64R6: # %bb.0: # %entry
1956 ; MIPS64R6-NEXT: jr $ra
1957 ; MIPS64R6-NEXT: andi $2, $4, 256
1958 ;
1959 ; MM32R3-LABEL: and_i16_256:
1960 ; MM32R3: # %bb.0: # %entry
1961 ; MM32R3-NEXT: jr $ra
1962 ; MM32R3-NEXT: andi $2, $4, 256
1963 ;
1964 ; MM32R6-LABEL: and_i16_256:
1965 ; MM32R6: # %bb.0: # %entry
1966 ; MM32R6-NEXT: andi $2, $4, 256
1967 ; MM32R6-NEXT: jrc $ra
1968 entry:
655 %r = and i16 256, %b 1969 %r = and i16 256, %b
656 ret i16 %r 1970 ret i16 %r
657 } 1971 }
658 1972
659 define signext i32 @and_i32_256(i32 signext %b) { 1973 define signext i32 @and_i32_256(i32 signext %b) {
660 entry: 1974 ; MIPS-LABEL: and_i32_256:
661 ; ALL-LABEL: and_i32_256: 1975 ; MIPS: # %bb.0: # %entry
662 1976 ; MIPS-NEXT: jr $ra
663 ; ALL: andi $2, $4, 256 1977 ; MIPS-NEXT: andi $2, $4, 256
664 1978 ;
1979 ; MIPS32R2-LABEL: and_i32_256:
1980 ; MIPS32R2: # %bb.0: # %entry
1981 ; MIPS32R2-NEXT: jr $ra
1982 ; MIPS32R2-NEXT: andi $2, $4, 256
1983 ;
1984 ; MIPS32R6-LABEL: and_i32_256:
1985 ; MIPS32R6: # %bb.0: # %entry
1986 ; MIPS32R6-NEXT: jr $ra
1987 ; MIPS32R6-NEXT: andi $2, $4, 256
1988 ;
1989 ; MIPS64-LABEL: and_i32_256:
1990 ; MIPS64: # %bb.0: # %entry
1991 ; MIPS64-NEXT: jr $ra
1992 ; MIPS64-NEXT: andi $2, $4, 256
1993 ;
1994 ; MIPS64R2-LABEL: and_i32_256:
1995 ; MIPS64R2: # %bb.0: # %entry
1996 ; MIPS64R2-NEXT: jr $ra
1997 ; MIPS64R2-NEXT: andi $2, $4, 256
1998 ;
1999 ; MIPS64R6-LABEL: and_i32_256:
2000 ; MIPS64R6: # %bb.0: # %entry
2001 ; MIPS64R6-NEXT: jr $ra
2002 ; MIPS64R6-NEXT: andi $2, $4, 256
2003 ;
2004 ; MM32R3-LABEL: and_i32_256:
2005 ; MM32R3: # %bb.0: # %entry
2006 ; MM32R3-NEXT: jr $ra
2007 ; MM32R3-NEXT: andi $2, $4, 256
2008 ;
2009 ; MM32R6-LABEL: and_i32_256:
2010 ; MM32R6: # %bb.0: # %entry
2011 ; MM32R6-NEXT: andi $2, $4, 256
2012 ; MM32R6-NEXT: jrc $ra
2013 entry:
665 %r = and i32 256, %b 2014 %r = and i32 256, %b
666 ret i32 %r 2015 ret i32 %r
667 } 2016 }
668 2017
669 define signext i64 @and_i64_256(i64 signext %b) { 2018 define signext i64 @and_i64_256(i64 signext %b) {
670 entry: 2019 ; MIPS-LABEL: and_i64_256:
671 ; ALL-LABEL: and_i64_256: 2020 ; MIPS: # %bb.0: # %entry
672 2021 ; MIPS-NEXT: andi $3, $5, 256
673 ; GP32: andi $3, $5, 256 2022 ; MIPS-NEXT: jr $ra
674 ; GP32: addiu $2, $zero, 0 2023 ; MIPS-NEXT: addiu $2, $zero, 0
675 2024 ;
676 ; GP64: andi $2, $4, 256 2025 ; MIPS32R2-LABEL: and_i64_256:
677 2026 ; MIPS32R2: # %bb.0: # %entry
678 ; MM32-DAG: andi $3, $5, 256 2027 ; MIPS32R2-NEXT: andi $3, $5, 256
679 ; MM32-DAG: li16 $2, 0 2028 ; MIPS32R2-NEXT: jr $ra
680 2029 ; MIPS32R2-NEXT: addiu $2, $zero, 0
681 ; MM64: andi $2, $4, 256 2030 ;
682 2031 ; MIPS32R6-LABEL: and_i64_256:
2032 ; MIPS32R6: # %bb.0: # %entry
2033 ; MIPS32R6-NEXT: andi $3, $5, 256
2034 ; MIPS32R6-NEXT: jr $ra
2035 ; MIPS32R6-NEXT: addiu $2, $zero, 0
2036 ;
2037 ; MIPS64-LABEL: and_i64_256:
2038 ; MIPS64: # %bb.0: # %entry
2039 ; MIPS64-NEXT: jr $ra
2040 ; MIPS64-NEXT: andi $2, $4, 256
2041 ;
2042 ; MIPS64R2-LABEL: and_i64_256:
2043 ; MIPS64R2: # %bb.0: # %entry
2044 ; MIPS64R2-NEXT: jr $ra
2045 ; MIPS64R2-NEXT: andi $2, $4, 256
2046 ;
2047 ; MIPS64R6-LABEL: and_i64_256:
2048 ; MIPS64R6: # %bb.0: # %entry
2049 ; MIPS64R6-NEXT: jr $ra
2050 ; MIPS64R6-NEXT: andi $2, $4, 256
2051 ;
2052 ; MM32R3-LABEL: and_i64_256:
2053 ; MM32R3: # %bb.0: # %entry
2054 ; MM32R3-NEXT: li16 $2, 0
2055 ; MM32R3-NEXT: jr $ra
2056 ; MM32R3-NEXT: andi $3, $5, 256
2057 ;
2058 ; MM32R6-LABEL: and_i64_256:
2059 ; MM32R6: # %bb.0: # %entry
2060 ; MM32R6-NEXT: andi $3, $5, 256
2061 ; MM32R6-NEXT: li16 $2, 0
2062 ; MM32R6-NEXT: jrc $ra
2063 entry:
683 %r = and i64 256, %b 2064 %r = and i64 256, %b
684 ret i64 %r 2065 ret i64 %r
685 } 2066 }
686 2067
687 define signext i128 @and_i128_256(i128 signext %b) { 2068 define signext i128 @and_i128_256(i128 signext %b) {
688 entry: 2069 ; MIPS-LABEL: and_i128_256:
689 ; ALL-LABEL: and_i128_256: 2070 ; MIPS: # %bb.0: # %entry
690 2071 ; MIPS-NEXT: andi $5, $7, 256
691 ; GP32: andi $5, $7, 256 2072 ; MIPS-NEXT: addiu $2, $zero, 0
692 ; GP32: addiu $2, $zero, 0 2073 ; MIPS-NEXT: addiu $3, $zero, 0
693 ; GP32: addiu $3, $zero, 0 2074 ; MIPS-NEXT: jr $ra
694 ; GP32: addiu $4, $zero, 0 2075 ; MIPS-NEXT: addiu $4, $zero, 0
695 2076 ;
696 ; GP64: andi $3, $5, 256 2077 ; MIPS32R2-LABEL: and_i128_256:
697 ; GP64: daddiu $2, $zero, 0 2078 ; MIPS32R2: # %bb.0: # %entry
698 2079 ; MIPS32R2-NEXT: andi $5, $7, 256
699 ; MM32-DAG: andi $5, $7, 256 2080 ; MIPS32R2-NEXT: addiu $2, $zero, 0
700 ; MM32-DAG: li16 $2, 0 2081 ; MIPS32R2-NEXT: addiu $3, $zero, 0
701 ; MM32-DAG: li16 $3, 0 2082 ; MIPS32R2-NEXT: jr $ra
702 ; MM32-DAG: li16 $4, 0 2083 ; MIPS32R2-NEXT: addiu $4, $zero, 0
703 2084 ;
704 ; MM64: andi $3, $5, 256 2085 ; MIPS32R6-LABEL: and_i128_256:
705 ; MM64: daddiu $2, $zero, 0 2086 ; MIPS32R6: # %bb.0: # %entry
706 2087 ; MIPS32R6-NEXT: andi $5, $7, 256
2088 ; MIPS32R6-NEXT: addiu $2, $zero, 0
2089 ; MIPS32R6-NEXT: addiu $3, $zero, 0
2090 ; MIPS32R6-NEXT: jr $ra
2091 ; MIPS32R6-NEXT: addiu $4, $zero, 0
2092 ;
2093 ; MIPS64-LABEL: and_i128_256:
2094 ; MIPS64: # %bb.0: # %entry
2095 ; MIPS64-NEXT: andi $3, $5, 256
2096 ; MIPS64-NEXT: jr $ra
2097 ; MIPS64-NEXT: daddiu $2, $zero, 0
2098 ;
2099 ; MIPS64R2-LABEL: and_i128_256:
2100 ; MIPS64R2: # %bb.0: # %entry
2101 ; MIPS64R2-NEXT: andi $3, $5, 256
2102 ; MIPS64R2-NEXT: jr $ra
2103 ; MIPS64R2-NEXT: daddiu $2, $zero, 0
2104 ;
2105 ; MIPS64R6-LABEL: and_i128_256:
2106 ; MIPS64R6: # %bb.0: # %entry
2107 ; MIPS64R6-NEXT: andi $3, $5, 256
2108 ; MIPS64R6-NEXT: jr $ra
2109 ; MIPS64R6-NEXT: daddiu $2, $zero, 0
2110 ;
2111 ; MM32R3-LABEL: and_i128_256:
2112 ; MM32R3: # %bb.0: # %entry
2113 ; MM32R3-NEXT: li16 $2, 0
2114 ; MM32R3-NEXT: li16 $3, 0
2115 ; MM32R3-NEXT: li16 $4, 0
2116 ; MM32R3-NEXT: jr $ra
2117 ; MM32R3-NEXT: andi $5, $7, 256
2118 ;
2119 ; MM32R6-LABEL: and_i128_256:
2120 ; MM32R6: # %bb.0: # %entry
2121 ; MM32R6-NEXT: andi $5, $7, 256
2122 ; MM32R6-NEXT: li16 $2, 0
2123 ; MM32R6-NEXT: li16 $3, 0
2124 ; MM32R6-NEXT: li16 $4, 0
2125 ; MM32R6-NEXT: jrc $ra
2126 entry:
707 %r = and i128 256, %b 2127 %r = and i128 256, %b
708 ret i128 %r 2128 ret i128 %r
709 } 2129 }